JPH0945900A - Misfet and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a hyperfine MISFET in manufacturing process by a method wherein a side wall insulator is formed of heat-melting insulating film, silicon is selectively and epitaxially grown for the formation of upheaval source.drain regions, and a recess provided to a facet region is filled up with side wall insulator. SOLUTION: An active region 3 surrounded with a field insulating film 2 on a silicon substrate and a gate electrode 4 insulated from the silicon substrate through the intermediary of a gate insulating film are provided. Upheaval source.drain regions 5 are formed in the prescribed region of the active region 3, and a facet 6 is formed on each end of the source.drain regions 5. The facets 6 and the side walls of the gate electrode 4 are coated with side wall insulator 7 which contains impurities high in concentration and is heat-melting. Therefore, impurities contained in the side wall insulator 7 are thermally diffused into the substrate to form source.drain diffusion layers. As mentioned above, the side wall insulator 7 is made to serve both as a spacer insulating film and an impurity diffusion source, so that a manufacturing process can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type FET and a method of manufacturing the same, and more particularly to a MIS type FET having source / drain regions raised from the main surface of a semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the progress of fine processing technology, it becomes possible to manufacture fine MIS type FETs having a gate length of less than 0.1 μm. However, in a device with a gate length of about 0.1 μm, in order to suppress the short channel effect,
The depth of the source / drain junction region is about 50 nm, which is extremely shallow.

In a usual impurity ion implantation method, boron, which is a P-type impurity of conductivity type, undergoes accelerated diffusion when subjected to heat treatment for activating the impurities to broaden the impurity distribution range to about 50 nm. It is difficult to form a shallow junction. Further, if the junction depth is shallow, not only the layer resistance of the source / drain increases but also it becomes difficult to form a contact hole for electrical connection with the wiring.

Therefore, as a method of forming a shallow junction region, various methods of raising the source / drain regions from the surface of the semiconductor substrate have been studied. The method of raising the source / drain regions will be described with reference to the technique disclosed in Japanese Patent Application Laid-Open No. 2-222153.

6A to 6C are cross-sectional views in the order of manufacturing steps of a MIS-type FET having a raised structure disclosed in Japanese Patent Laid-Open No. 2-222153. As shown in FIG. 6A, the semiconductor substrate 1
The field insulating film 102 is selectively formed on 01. Then, the gate insulating film 103 is formed on the semiconductor substrate, and the gate electrode 104 is formed on the gate insulating film by using polycrystalline silicon containing impurities such as phosphorus.

A sidewall space insulator 105 is formed of an oxide on the sidewall of the gate electrode 104. Here, the thickness is 20 nm to 90 nm. After that, an extremely shallow junction region 106 is formed by the first ion implantation. The junction region 106 contains 5 × 10 ¹⁷ / cm ³ of either an N type conductivity type impurity (eg, arsenic, phosphorus, or antimony) or a P type impurity type (eg, boron).
To 1 × 10 ²⁰ / cm ³ of surface density.

Next, as shown in FIG. 6B, raised source / drain regions 107 are formed by selectively depositing epitaxial silicon in a layer having a thickness in the range of 100 nm to 200 nm. . Here, the field insulating film 102 and the raised source / drain regions 107
And a small facet surface 108 is formed between
Further, the facet surface 1 is formed between the raised source / drain regions 107 and the sidewall space insulator 105.
09 is formed.

Next, as shown in FIG. 6C, the side wall space insulator 105 and the raised source / drain region 1 are formed.
07, a first side wall spacer 110 is formed so as to embed the facet surface 109. Similarly, the field insulating film 102 and the raised source / drain region 10 are formed.
Second side wall spacers 111, which bury the facet surfaces 108 between them, are also formed. The first and second side wall spacers are simultaneously formed by depositing an insulating film with a thickness of about 100 nm to 200 nm over the entire region to be the transistor and subsequently performing etch back by dry etching.

Next, as shown in FIG. 6 (d), impurities are introduced again by the second ion implantation and a heat treatment is performed. Here, the implantation impurities at this stage are the same as the impurities for the first ion implantation. In this way, the shallow junction 112 is formed.

Next, the raised source / drain region 10
Low resistance silicide layers 113 and 114 are formed on the surfaces of the gate electrode 104 and the gate electrode 104, respectively. The silicide layers 113 and 114 are manufactured by depositing a titanium film on the entire structure shown in FIG. 6D and performing heat treatment in a nitrogen atmosphere to react the exposed silicon with the titanium film.
This is done by forming a titanium silicide layer.

In this conventional technique, the first side wall spacer 1
10 and the second side wall spacer 111 are formed on the facet surfaces 108 and 109 in the second ion implantation described above.
The shallow junction 11 by eliminating the impurity ion implantation through the recess of
It has a role of preventing the second diffusion region from becoming deep locally. Alternatively, these spacers have a role of preventing the formation of a spike-like defective bonding region due to the formation of the silicide layer on the surface of the semiconductor substrate through the concave portions of the facet surfaces 108 and 109 in the above-described step of forming the silicide layer. Have.

[0012]

In the MISFET having the source / drain regions having such a raised structure, the facet surface as described above is formed at the end of the epitaxial silicon layer. And, the formation of the concave portion by this facet surface, unless some measures are taken,
As described above, the formation of the deep diffusion region or the formation of the spike-like defective bonding region is caused.

Further, in the conventional technique, new sidewall spacers, that is, the first sidewall spacer and the second sidewall spacer are formed to fill the recess formed by the facet surface. In this case, the MIS type FET is used. In addition to increasing the number of manufacturing steps, it becomes difficult to control the impurity concentration of the source / drain regions. Then, it becomes difficult to realize an ultra-fine MIS type FET.

An object of the present invention is to provide a simple method for solving the above-mentioned problems and to facilitate the manufacture of a highly reliable and ultra-fine MIS type FET.

[0015]

For this purpose, the MI of the present invention is used.
In the S-type FET, a gate insulating film formed on a main surface of a semiconductor substrate, a gate electrode formed on the gate insulating film, and one conductivity formed on the main surface of the semiconductor substrate with the gate electrode sandwiched therebetween. A source / drain diffusion layer of the same type, and a semiconductor thin film layer doped with the same conductivity type impurity is selectively formed on the main surface of the semiconductor substrate in the region where the source / drain diffusion layer is formed. A facet surface is formed on an end portion of the semiconductor thin film facing the side wall surface of the gate electrode, and the facet surface and the side wall surface of the gate electrode are a sidewall insulator containing a high concentration impurity and having thermal fluidity. It is covered.

Then, the manufacturing method comprises the steps of forming a gate electrode on the gate insulating film on the main surface of the semiconductor substrate and then forming the side wall insulator on the side wall surface of the gate electrode.
A step of selectively growing a semiconductor thin film layer on a main surface of a semiconductor substrate in a region where a source / drain diffusion layer is formed; Coating a surface with the thermally fluidized sidewall insulator.

Here, the temperature at which the semiconductor thin film layer is selectively grown is set to a temperature lower than the temperature at which the sidewall insulator is thermally fluidized.

Alternatively, the impurity of one conductivity type is thermally diffused into the semiconductor substrate from the semiconductor thin film layer and the heat-flowed side wall insulator to form a source / drain diffusion layer.

Alternatively, the method includes a step of forming a refractory metal silicide layer on the surface of the semiconductor thin film layer.

Alternatively, after heat-flowing the side wall insulator and covering the facet surface with the heat-flowing side wall insulator, the one conductivity type impurity is ion-implanted into the semiconductor thin film layer to form the semiconductor thin film layer and the semiconductor thin film layer. The method includes doping the semiconductor substrate with an impurity of one conductivity type and the gate electrode with the same impurity.

As described above, according to the present invention, the MIS type FET
The source / drain regions are raised from the surface of the semiconductor substrate, and one kind of sidewall insulator is formed on the sidewall surface of the gate electrode. Then, by the subsequent heat treatment, the aforementioned sidewall insulator is buried in the recess between the sidewall surface of the gate electrode and the raised source / drain region by thermal flow. Further, the impurities contained in the sidewall insulator are thermally diffused in the semiconductor substrate to form the source / drain diffusion layers. Thus, one type of sidewall insulator serves as an insulating film for spacers and an impurity diffusion source, which shortens the manufacturing process of the MIS type FET.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a MIS type FET for explaining an embodiment of the present invention.

As shown in FIG. 1, the MIS type FE of the present invention
T1 is formed as follows. That is, the active region 3 surrounded by the field insulating film 2 on the silicon substrate and the gate electrode 4 insulated from the silicon substrate via the gate insulating film are formed. Here, the gate electrode 4 is composed of tungsten polycide. And the active region 3
The raised source / drain regions 5 are formed in predetermined regions. Here, this raised source / drain region 5
Is formed by selective epitaxial growth of silicon and contains impurities such as arsenic, phosphorus or boron.

At the ends of the raised source / drain regions 5, facet surfaces 6 as described above are formed.
Then, the reflow spacer 7 which covers the facet surface 6 and extends along the side wall of the gate electrode 4 is formed. Here, the reflow spacer 7 is assumed to be composed of a sidewall insulator containing arsenic, phosphorus or boron.
Then, the impurities are diffused from the reflow spacer 7 containing the impurities to the surface of the silicon substrate, and the MIS type FE
The junction region of the source / drain regions of T is formed on the surface of the silicon substrate.

Next, a method of manufacturing such a MIS type FET will be described with reference to FIGS. 2 and 3 are cross-sectional views in order of the steps, showing the first manufacturing method of the present invention. Here, these cross-sectional views correspond to the cross section taken along the line AB in FIG.

As shown in FIG. 2A, a field insulating film 12 is selectively formed on the surface of a silicon substrate 11 having a crystal plane orientation of (100). This field insulating film 12
First, an insulating film such as a silicon oxide film is buried in a groove formed in this region by dry etching, and is flattened by a chemical mechanical polishing (CMP) method. Alternatively, it is a thick silicon oxide film selectively thermally oxidized on the surface of the silicon substrate by the method of recess LOCOS.

Next, the gate insulating film 13 is formed on the surface of the silicon substrate 11. Here, the gate insulating film 13 is a silicon oxide film having a film thickness of about 6 nm formed by thermal oxidation. Then, the gate electrode 14 is formed on the gate insulating film 13. Here, the gate electrode 14 is formed of polycide of a refractory metal such as tungsten polycide. Here, when the MIS type FET is a P-channel type, the tungsten polycide contains boron. In the case of the N-channel type, phosphorus or arsenic is contained.

Further, a film thickness of 20 is formed on the gate electrode 14.
A protective insulating film 15 composed of a silicon nitride film of nm thickness is formed. Here, the gate electrode 14 or the protective insulating film 15 is formed by film deposition by a known chemical vapor deposition (CVD) method and fine processing by dry etching.

Next, an impurity-containing insulating film 16 having a film thickness of about 50 nm and having thermal fluidity (thermal reflow) is formed by direct contact with the main surface of the silicon substrate 11 by the CVD method. Here, when the MIS-type FET is a P-channel type, the impurity-containing insulating film 16 is a BSG film (silicon oxide film containing boron glass), and the amount of boron in the film is 10 mol%.
It is set to be a degree. When the MIS type FET is an N channel type, the impurity-containing insulating film 16 is an AsSG film (silicon oxide film containing arsenic) or a PSG film (silicon oxide film containing phosphorus glass),
The amount of these impurities in the film is set to be 10 to 12 mol%.

Next, the impurity-containing insulating film 16 having the structure of FIG. 2A is etched back by anisotropic dry etching. By this etch back, as shown in FIG. 2B, a sidewall spacer 17 having a film thickness of about 50 nm to be a sidewall insulator is formed on the sidewall portions of the gate insulating film 13, the gate electrode 14, and the protective insulating film 15. Here, a mixed gas of CF ₄ , CHF _3, and CO is used as a reaction gas for dry etching. Under such dry etching conditions, the etching rate ratio between the impurity-containing insulating film 16 and the protective insulating film 15 is 30 or more, and the protective insulating film 15 is hardly etched in this etching back step. Further, the etching rate ratio between the impurity-containing insulating film 16 and the field insulating film 12 is 10 or more. Therefore, the surface of the field insulating film 12 is etched by about 10 nm by performing overetching of about 200% in the above-mentioned etchback process. Here, in such an etch back, the surface of the silicon substrate 11 is not etched at all. Thus, as shown in FIG. 2B, the surface of the silicon substrate is exposed and the silicon end portion 18 is formed.

Next, as shown in FIG. 2C, the film thickness is 1
A raised source / drain region 19 of about 00 nm is formed. The raised source / drain region 19 is a single crystal silicon film formed by selective epitaxial growth of silicon by a low pressure CVD method. . Here, the growth temperature is set to 750 to 800 ° C. At such a temperature, the above-mentioned thermal reflow of the impurity-containing insulating film does not occur. Also, as reaction gas, SiH ₂ Cl ₂ and HC
l of mixed gas is used. Then, in a P-channel type field of the MIS type FET, B ₂ H ₆ is mixed into the reaction gas to deposit an epitaxial silicon layer containing a high concentration of boron. When the MIS type FET is an N channel type, AsH ₃ is mixed in the reaction gas to deposit an epitaxial silicon layer containing arsenic at a high concentration. Here, the concentrations of these impurities are set to be 10 ¹⁹ to 10 ²⁰ / cm ³ .

In such selective epitaxial growth, in the region adjacent to the sidewall spacer 17, the {311} plane, which is a crystal plane having the same value as the (311) plane, or similarly the {11} plane.
A facet surface 20 such as a 1} surface is formed. Further, at the silicon end portion 18 described above, the silicon layer grows so as to cover a part of the field insulating film 12 {100}.
A raised end 21 which is a surface is formed.

Next, heat treatment is performed at about 850 ° C. in a nitrogen atmosphere to thermally reflow the side wall spacers 17 and then, as shown in FIG.
The reflow spacer 22 shown in (a) is formed and the facet surface 20 is embedded.

Next, as shown in FIG.
Impurities are introduced into the surface of the silicon substrate by a rapid heating method at about ° C to form the junction region 23. Here, the diffusion sources of these impurities are the raised source / drain region 19 and the reflow spacer 22.

Here, the step of thermally reflowing the side wall spacers 17 and the step of forming the bonding region 23 may be performed in one heat treatment step. In this case, the heat treatment is performed at a temperature of 900
It is performed in a heat treatment furnace at ℃.

Next, the gate electrode 14 shown in FIG.
The upper protective insulating film 15 is removed. Then, low resistance silicide layers 24 and 25 are formed on the surfaces of the raised source / drain regions 19 and the gate electrode 14, respectively.
The formation of the silicide layers 24 and 25 is shown in FIG.
The titanium film is deposited on the entire structure of (1) and heat treatment is performed in a nitrogen atmosphere to react the exposed silicon with the titanium film to form a titanium / silicide layer. Here, the titanium nitride formed on the surface of the field insulating film 12 and the surface of the reflow spacer 22 is selectively removed.

According to the manufacturing method of the present invention, the facet surface, which has been a problem in the raising method, is easily buried by thermally reflowing the side wall spacers 17. Further, the depth of the junction region from the raised surface of the source / drain region 19 can be set to about 150 nm, which is the same value as that of the conventional MIS type FET, so that the increase of layer resistance and contact resistance can be prevented.

Further, since the depth of the junction region from the surface of the silicon substrate is effectively reduced by the film thickness of the raised region, the value is about 50 nm and punch-through between the source and the drain is easily prevented. Like

In this manufacturing method, the facet surface 20 generated in the selective epitaxial growth of silicon shown in FIG. 2 (c) may extend to a position far away from the side wall spacer 17 and widen. In this case,
It should be noted that the following is effective for the reflow spacer 22 shown in FIG. 3A to cover the facet surface 20 described above. That is, FIG.
The thickness of the protective insulating film 15 shown in (a) is increased to about 300 nm. By doing so, the height of the side wall including the gate electrode 14 increases, and the height of the side wall spacer 17 also increases.
When thermal reflow of the side wall spacers 17 is performed in this state, the side wall spacers 17 flow widely in the lateral direction. Then, the reflow spacer 22 completely covers the wide facet surface 20 as described above.

Next, a second manufacturing method of the present invention will be described with reference to FIGS. 4 and 5. 4 and 5 show the M of the present invention.
It is sectional drawing in the manufacturing process order of IS type FET. Here, these cross-sectional views correspond to the cross section taken along the line AB in FIG.

As shown in FIG. 4A, the field insulating film 32 is selectively formed on the surface of the silicon substrate 31 having the crystal plane orientation (100). Next, the gate insulating film 33 is formed on the surface of the silicon substrate 31. Here, the gate insulating film 33 is a silicon oxide film formed by thermal oxidation. Then, the gate electrode 34 is formed on the gate insulating film 33. Here, the gate electrode 34 is tungsten polycide. Here, the tungsten polycide contains no impurities.

Further, a first protective insulating film 35 made of a silicon nitride film is formed on the gate electrode 34. Here, the gate electrode 34 and the first protective insulating film 35
Is formed by deposition of a film by a known CVD method and fine processing by dry etching.

Next, a silicon oxide thin film 36 having a thickness of 20 nm is formed by the CVD method. Then, the junction region 37 is formed by ion implantation of arsenic impurities or boron impurities.

Next, the impurity-containing insulating film 38 having a film thickness of about 30 nm is formed by the CVD method. Here, the impurity-containing insulating film 38 is the BSG film described in the first manufacturing method, and the amount of boron in the film is set to be about 10 mol%.

Next, the impurity-containing insulating film 38 having the structure of FIG. 4A is etched back in the same manner as in the first manufacturing method. By this etch back, as shown in FIG. 4B, the side wall spacer 39 having a film thickness of about 50 nm is formed on the gate insulating film 33,
The silicon oxide thin film 36 is formed on the side walls of the gate electrode 34 and the first protective insulating film 35. Here, a mixed gas of CHF ₃ and CO is used as a reaction gas for dry etching. Under such dry etching conditions, the etching rates of the impurity-containing insulating film 38 and the silicon oxide thin film 36 are almost the same. Therefore, in the above-mentioned etch back process, the silicon oxide thin film 36 is also etched to form the second protective insulating film 40. Further, over-etching is performed to etch the surface of the field insulating film 32 by about 10 nm. Here, in such an etch back, the surface of the silicon substrate 31 is not etched at all. Thus, as shown in FIG. 4B, the surface of the silicon substrate is exposed and the silicon end portion 41 is formed.

Next, as shown in FIG. 4C, the film thickness is 2
A raised source / drain region 42 of about 00 nm is formed. The raised source / drain regions 42 are formed by selective epitaxial growth of silicon by the low pressure CVD method. Here, the raised source / drain regions 42 do not contain impurities. The temperature of this epitaxial growth is set to 750 to 800 ° C. At such a temperature, the above-mentioned thermal reflow between the impurity-containing insulation does not occur. A mixed gas of SiH ₂ Cl ₂ and HCl is used as the reaction gas.

In such selective epitaxial growth, the crystal plane {31
A facet surface 43, which is a small surface such as a 1} surface or a {111} surface, is formed. In addition, the silicon end 4 described above
In No. 1, the silicon layer grows so as to cover a part of the field insulating film 32, and the raised end portion 44 which is the {100} plane is formed.

Next, heat treatment is performed at about 850 ° C. in a nitrogen atmosphere to thermally reflow the side wall spacers 39, and then, as shown in FIG.
The reflow spacer 45 shown in (a) is formed and the facet surface 43 is embedded. Then, arsenic or boron ions are implanted to introduce these impurities into the gate electrode 34 and the rising source / drain regions 42. Next, as shown in FIG. 5B, impurities are introduced into the surface of the silicon substrate by a rapid heating method at about 1000 ° C. to form a junction region 37a.

Next, the gate electrode 34 shown in FIG.
The upper first protective insulating film 35 is removed. Then, on the surface of the raised source / drain region 42 and the gate electrode 34,
Low resistance silicide layers 46 and 47 are formed, respectively. The production of the silicide layers 46 and 47 is similar to that described in the first production method.

In the manufacturing method of the present invention, the same material is used for the above-mentioned reflow spacer in the N-channel type MIS type FET and the P-channel type MIS type FET. Therefore, the reflow spacer in CMOS can be formed in the same process, and the whole manufacturing process can be shortened.

[0051]

As described above, according to the present invention, the sidewall insulator is formed by the insulating film having the thermal reflow property, and then the silicon is selectively epitaxially grown to form the raised source / drain regions. Then, the above-mentioned sidewall insulator is reflowed by heat treatment, and the recess in the facet region formed by selective epitaxial growth is filled with this sidewall insulator.

Therefore, the manufacturing process of the ultra-fine MIS type FET is shortened as compared with the case of the conventional technique.

The layer resistance of the source / drain regions of the MOS transistor and the contact resistance with the wiring are reduced.
Further, formation of a deep diffusion layer or a defective junction region caused by the ion implantation process of impurities for forming the source / drain regions and the silicidation process is prevented.

An extremely shallow junction can be formed on the surface of the semiconductor substrate below the sidewall insulator by selecting an insulating film containing an impurity of the same conductivity type as the source / drain region as the sidewall insulator. As a result, the short channel effect of the MIS type FET can be suppressed.

In this way, a highly reliable M
Manufacturing of the IS type FET is facilitated.

[0056]

[Brief description of drawings]

FIG. 1 is a plan view of a MIS-type FET for explaining the present invention.

2A to 2D are cross-sectional views in order of the processes, for illustrating the first manufacturing method of the present invention.

3A to 3D are cross-sectional views in order of the processes, for illustrating the first manufacturing method of the present invention.

FIG. 4 is a cross-sectional view in process order for explaining a second manufacturing method of the present invention.

FIG. 5 is a cross-sectional view in process order for explaining a second manufacturing method of the present invention.

6A to 6C are cross-sectional views in the order of manufacturing steps for explaining a conventional technique.

[Explanation of symbols]

1 MIS type FET 2, 12, 32, 102 Field insulating film 3 Active region 4, 14, 34, 104 Gate electrode 5, 19, 42, 107 Raised source / drain region 6, 20, 43, 108, 109 Facet surface 7,22,45 Reflow spacer 11,31 Silicon substrate 13,33,103 Gate insulating film 15 Protective insulating film 16,38 Impurity containing insulating film 17,39 Side wall spacer 18,41 Silicon edge 21,44 Raised edge 23 , 37, 37a, 106 Junction region 24, 25, 46, 47, 113, 114 Silicide layer 35 First protective insulating film 36 Silicon oxide thin film 40 Second protective insulating film 101 Semiconductor substrate 105 Side wall space insulator 110 First side wall Spacer 111 Second sidewall spacer 112 Shallow junction

Claims (6)

[Claims] 1. A gate insulating film formed on a main surface of a semiconductor substrate, a gate electrode formed on the gate insulating film, and one conductivity formed on the main surface of the semiconductor substrate with the gate electrode interposed therebetween. A source / drain diffusion layer of the same type, and a semiconductor thin film layer doped with the same conductivity type impurity is selectively formed on the main surface of the semiconductor substrate in the region where the source / drain diffusion layer is formed. A facet surface is formed at an end of the semiconductor thin film facing a side wall surface of the gate electrode, and the facet surface and the side wall surface of the gate electrode are a side wall insulator containing a high concentration impurity and having thermal fluidity. A MIS type FET characterized by being covered. 2. A step of forming a gate electrode on a gate insulating film on a main surface of a semiconductor substrate and then forming the side wall insulator on a side wall surface of the gate electrode, and a step of forming a source / drain diffusion layer. A step of selectively growing a semiconductor thin film layer on the main surface of the semiconductor substrate; and, after the growth of the semiconductor thin film layer, the sidewall insulator is thermally fluidized by heat treatment to cover the facet surface with the thermally fluidized sidewall insulator. A method of manufacturing a MIS-type FET, comprising: 3. The M according to claim 2, wherein a temperature at which the semiconductor thin film layer is selectively grown is set to a temperature lower than a temperature at which the sidewall insulator is thermally fluidized.
Method for manufacturing IS-type FET. 4. The source / drain diffusion layer is formed by thermally diffusing the one conductivity type impurity into the semiconductor substrate from the semiconductor thin film layer and the heat-flowed side wall insulator. 2. The method for manufacturing a MIS type FET described in 2. 5. The MISFET according to claim 2, further comprising a step of forming a refractory metal silicide layer on a surface of the semiconductor thin film layer.
Manufacturing method. 6. The sidewall insulator is thermally fluidized to cover the facet surface with the thermally fluidized sidewall insulator, and then the one conductivity type impurity is ion-implanted into the semiconductor thin film layer,
3. The method of manufacturing a MIS-type FET according to claim 2, wherein the semiconductor thin film layer and the semiconductor substrate are doped with an impurity of one conductivity type and the gate electrode is also doped with the same impurity.