JPS6352476A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a bad state of contact resistance by a method wherein a semiconductor nitride film which is formed at a comparatively low temperature is provided between a metal electrode and a protective insulating film. CONSTITUTION:After a metal electrode 3 has been formed, an SiN film 9 with a thickness of 1000-2000 Angstrom is formed by a reaction by making use of plasma discharge and used as a passivation film. This SiN film 9 is formed at about 260 deg.C. An SOG (spin on glass) coating 5 is formed such that it is about 1000Angstrom thick above a gate electrode and also buries steps at the sides of the gate electrode, and the coating is then baked. Because the SiN film 9 formed at a low temperature exists, it is possible to prevent that the surface of the metal electrode 3 is oxidized during a subsequent heat-treatment process and that the contact resistance in relation other wiring parts connected with the surface is increased.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention is directed to MOsFETs (insulated gate field effect transistors) having high melting point metals, and particularly relates to technology for reducing contact resistance between the metal electrodes and wiring metals. [Prior art] In a semiconductor device, when electrical continuity is established between a lower electrode and an upper electrode (wiring) through a through-hole in an interlayer insulating film, a microelectrode is formed on the lower electrode surface of a miniaturized through-hole portion. Techniques for preventing an increase in contact resistance due to generated substances are described in Nikkei McGraw-Hill, September 1985 issue N.
I K K E IMICRODEVICES p
, 77 etc. t'Mc.

In this case, the lower layer electrode is Affl-8i, and the heat treatment conditions are changed to prevent Si precipitation in the through hole portion.

By the way, as a miniaturization technology for MOsFET, source
MOs that use Mo (molybdenum), a high-melting point metal, as the gate electrode, to which self-alignment technology for drain diffusion can be applied, and which can ensure a low resistance value as an electrode.
A FET has been developed by the inventor.

It is necessary to connect the AJ3 wiring as the upper electrode to the 'tea (lower electrode) of this MO game, and the SiO! AJ3 is vapor-deposited through the holes in the interlayer film of the system, but oxidation of the Mo electrode surface becomes a problem at that time. Here, we will describe the electrode connection technology that is being considered by the present inventor. Note that this technique is not necessarily a known technique and is not a surname technique.

Hereinafter, a detailed explanation will be given with reference to FIGS. 6 to 9.

tl) A gate oxide film 2 is thermally generated on a Si substrate 1, a metal Mo electrode 3 is formed on it, and a source/drain N4 is formed by self-alignment (Fig. 6), (2) 5OG (spin・Apply a film 5 (on glass) to a thickness of about 1000 mm (Fig. 7), and deposit a PSG (phosphorous silicate glass) film 6 (by KCVD method on 31 pieces) (Fig. 8). .

[Problem that the invention seeks to solve]

In the above process, moisture etc. are evaporated and removed by 5o (4 cloth (tK baking), but the moisture during baking is SOG & 2 moisture absorption up to the PSG deposit, 5OGH at the PSG deposit temperature (430C) is used as water vapor as a separated gas and as a PSG deposit gas. S iN4.P Hs,
The metal electrode is oxidized by the influence of the acidic atmosphere caused by the O gas, and an oxide film 7 is formed (FIG. 9). Furthermore, the PSG film serves as a lid by the post-PSGS body deposition process 11 (9001:), which further promotes oxidation of the metal dL electrode.

Like this gold'g4'#! A connected above this so that the L pole would be oxidized! The contact resistance with the wiring 8 becomes large, and therefore the gate resistance becomes large, and the 10SFET
This will affect the characteristics of

The present invention has been made to overcome the above-mentioned problems, and its purpose is to reduce the contact resistance between metal electrodes and other metal electrodes that are easily oxidized, and to reduce the contact resistance between metal electrodes and other metal electrodes.
The purpose is to improve the performance of ET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the illustrated drawings.

[Means for solving problems]

A brief general description of representative inventions disclosed in this publication is as follows.

That is, a metal electrode is formed on the surface of the semiconductor substrate, a semiconductor nitride film is formed under relatively low temperature conditions so as to cover the metal fitting 11, and a protective insulation film mainly composed of semiconductor oxide is formed on the semiconductor nitride film. It forms a film.

[Effect]

According to the above means, the presence of the nitride film generated at a low temperature prevents the surface of the metal electrode from being oxidized during subsequent heat treatment, prevents an increase in contact resistance with other wiring connected to the metal electrode, and It accomplishes its purpose.

〔Example〕

FIGS. 1 to 5 show one embodiment of the present invention, and are process cross-sectional views showing the manufacturing process of an MO gate MO3FET.

Hereinafter, each process will be explained in order according to the drawings.

(Prepare the llsi substrate 1, and deposit the gate oxide film (Sin)
Gold s41!2 was thermally generated, sputtered Mo on it to a thickness of about 450 mm, and patterned using photoresist. Forms pole 3. Thereafter, impurity ions are implanted using the electrode 3 as a mask, and annealing is performed to form source/drain regions 4 in a self-aligned manner (FIG. 1).

(After forming the metal electrode 21, SiN (silicon nitride) produced by reaction using plasma discharge is formed to a thickness of 1000 to 2000 Å as a badge base 1 film.
figure). The formation temperature of this SiN is about 2600℃. In addition to this plasma SiN, a coating of another substance that does not itself contain O2, does not emit decomposition gas during high-temperature heat treatment, and can completely eliminate intake from the outside may be used.

(3) After this, SOG is formed by a coating method, and an SOG film 5 with a thickness of about 100 OA is formed on the upper surface of the gate electrode so as to fill the step on the side of the gate, and then baked (Fig. 3).
.

(41 On top of this, PSG is applied by CVD (chemical vapor deposition) method.
The film 6 is deposited to a thickness of about 900 OA. Then, the PSG was densified by 7 anneals at 900C (Figure 4).

(5) After this, contact holes (through holes) are drilled using a wet method (hydrofluoric acid) and a dry method. The upper A chisel electrode (wiring) 8 is formed by vapor depositing and patterning (FIG. 5).

In the above process, the presence of plasma SiN blocks the desorption gas from the SOG film and the oxidizing atmosphere during the formation of the PSG film in step (41).

Further, when annealing is performed at 900C for subsequent densification, the SiN film prevents oxidation of MO due to the gas desorbed from SOG at the high temperature at that time.

In this way, 5L of gold was obtained by plasma SiN at the time of SOG coating and beta padding and subsequent heat treatment.
By being able to prevent the oxidation of the IT electrode, it is possible to eliminate the defect of increased contact resistance with the Ai electrode, thereby eliminating the increase in bulk resistance, and improve the performance of the MOSFET.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, as a metal electrode, M in addition to M.

Similar effects can be obtained when applied to MOSFETs and MO3-ICs using silicide, W (tungsten), W silicide, etc.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, by covering the metal electrode with plasma SiN before the puff coating treatment, oxidation caused by the above treatment can be inhibited and contact resistance defects can be prevented.

[Brief explanation of drawings]

FIG. 1 to FIG. 5 are MO8FE showing one embodiment of the present invention.
It is a process sectional view of T process. FIGS. 6 to 9 are cross-sectional views of the conventional MO3FET process. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Gate oxide film, 3... Metal electrode, 4... Source/drain, 5... SOG
m, 6...PSG film, 7...gelatinized film, 8...person 1
Den et al., 9...Plasma SiN film. Agent Patent Attorney Katsuo Ogawa Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. A semiconductor device in which an electrode made of metal is formed on the surface of a semiconductor substrate, and a protective insulating film is formed covering this electrode, the semiconductor device comprising: between the metal electrode and the protective insulating film; A semiconductor device characterized in that a semiconductor nitride film formed at a relatively low temperature is interposed in the semiconductor device. 2. In the semiconductor device according to claim 1, the electrode is made of molybdenum. 3. A method for manufacturing a semiconductor device, characterized in that an electrode made of metal is formed on a semiconductor substrate, and a semiconductor nitride film is generated by a plasma method before forming a protective insulating film on the metal electrode.