JPS62118525A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62118525A
JPS62118525A JP25897685A JP25897685A JPS62118525A JP S62118525 A JPS62118525 A JP S62118525A JP 25897685 A JP25897685 A JP 25897685A JP 25897685 A JP25897685 A JP 25897685A JP S62118525 A JPS62118525 A JP S62118525A
Authority
JP
Japan
Prior art keywords
film
wiring
titanium
tungsten
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25897685A
Other languages
Japanese (ja)
Inventor
Masafumi Shishino
宍野 政文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP25897685A priority Critical patent/JPS62118525A/en
Publication of JPS62118525A publication Critical patent/JPS62118525A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the mutual diffusion between silicon atoms and tungsten atoms as wiring material from occurring while forming the wiring structure resistant to high temperature heat-treatment by a method wherein two layers comprising a titanium nitride layer and a titanium tungsten alloy layer are formed on the connecting part of a diffused layer and a wiring layer formed on a silicon substrate. CONSTITUTION:A titanium film 3 is formed in a contact hole part 4 connecting a silicon substrate 1 with a first wiring and then nitrogen is injected in the interface between the silicon substrate 1 and the titanium film 3 later to form a tungsten film 6. Then titanium nitride, a compound of titanium and implanted nitrogen is formed on the interface between silicon and titanium film by high temperature heat-treatment. Furthermore, an alloy of titanium and tungsten is formed on the interface between the tungsten film and the titanium film. These layers are so effective for diffusion barrier that the tungsten film 6 as the first wiring connecting to the silicon substrate after formation can be heat- treated at high temperature. Resultantly, when a BPSG film 10 flowing at low temperature is applied for the interlayer insulator between the first wiring 6 and the second wiring 12, the BPSG film can be flattened easily.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関し、詳しくは、熱処
理に対し安定な配線構造をもった半導体装置の製造方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a wiring structure that is stable against heat treatment.

従来の技術 シリコン基板上に形成した拡散層と配線との接続穴であ
るコンタクトホール部に、化学気相成長2ベーノ 法(CVD法)によりタングステンシリサイド膜を形成
した後、連続してタングステン膜を形成し、微細なコン
タクトホールをタングステンシリサイド膜およびタング
ステン膜で埋め、第一の配線を形成した後、さらに第二
の配線を形成した場合の例を第2図(a)〜(C)の工
程順断面図により、説明を行う。
Conventional technology After forming a tungsten silicide film by chemical vapor deposition (CVD) in a contact hole, which is a connection hole between a diffusion layer and wiring formed on a silicon substrate, a tungsten film is continuously deposited. An example of the case where a fine contact hole is filled with a tungsten silicide film and a tungsten film, a first wiring is formed, and then a second wiring is further formed is shown in the steps shown in FIGS. 2(a) to (C). The explanation will be given using forward sectional views.

捷ず、第2図(a)に示すようにシリコン基板1に形成
した拡散層2土に絶縁膜3をCVD法により形成した後
、拡散層2に接続するコンタクトホール4を形成する。
As shown in FIG. 2(a), an insulating film 3 is formed on the diffusion layer 2 formed on the silicon substrate 1 by the CVD method, and then a contact hole 4 connected to the diffusion layer 2 is formed.

つぎに、反応ガスにSiH4、WF6を用い、化学気相
成長法によりタングステンシリサイド膜13を形成する
。その後、反応ガスを8iH4、WF6から、WF6と
H2に換え、連続してタングステン膜6を形成する。つ
ぎに、タングステンシリサイド膜13とタングステン膜
6からなる配線のパターンニングを行う。その後、第2
図(0)に示すように、タングステン膜6上に層間絶縁
を行うための硼燐硅酸ガラス(BPSG )膜10を形
成し、高温中でのアニールによりBPSG膜1Qのフロ
ーを行う1.最後に、タングステン膜と第二の配線との
接続を行う/とめの第二のコンタクトホール11を形成
1./こ後、第二の配線A」Fl−Cあるアルミニウム
膜124・スパッタ法で形成!2、パターンニングを行
い第二の配線を形成する。。
Next, a tungsten silicide film 13 is formed by chemical vapor deposition using SiH4 and WF6 as reaction gases. Thereafter, the reaction gases are changed from 8iH4 and WF6 to WF6 and H2, and a tungsten film 6 is continuously formed. Next, patterning of the wiring made of the tungsten silicide film 13 and the tungsten film 6 is performed. Then the second
1. As shown in Figure (0), a borophosphosilicate glass (BPSG) film 10 for interlayer insulation is formed on the tungsten film 6, and a flow of the BPSG film 1Q is performed by annealing at a high temperature. Finally, a second contact hole 11 is formed to connect the tungsten film and the second wiring.1. /After this, the second wiring A"Fl-C aluminum film 124 is formed by sputtering method! 2. Perform patterning to form the second wiring. .

発明が解決し」、つとする問題点 上記方法により、シリコン基板と接触1゛る第一・の配
線を形成l−1第二の配線との層間絶縁膜であるBPS
G膜のフロー4800℃程度の品温で行いBPSG膜の
平和化を行った場合、第2図(C) Vこ示すように、
′シリコン基板と第一の配線とか接触するコンタクトホ
ール部において、シリコン基板中のシリコンとタングス
テンj摸中のタングステンの反応が起り、タングステン
シリサイド層が形成される。このシリサイド化に3:す
、シリコン基枦への侵食が進み、シリコン基板と第一・
の配線とか短絡(−でし甘う。そのため、上記の従来の
方法では、高温の熱処理かできない、。
Problems to be Solved by the Invention By the method described above, a first wiring is formed in contact with a silicon substrate.
When the flow of the G film is carried out at a temperature of about 4800°C and the BPSG film is pacified, as shown in Figure 2 (C) V,
'At the contact hole portion where the silicon substrate contacts the first wiring, a reaction occurs between silicon in the silicon substrate and tungsten in the tungsten sample, and a tungsten silicide layer is formed. This silicidation leads to further erosion of the silicon substrate, and the silicon substrate and the first
The wiring may be short-circuited (-). Therefore, with the conventional method described above, only high-temperature heat treatment is possible.

本発明に1」=記問題点をiff決するものであり、多
層配線を必要とする超LSIにおいて非常に有効な半導
体装置の製造方法を提(jJする。
The present invention solves the above problems and provides a method for manufacturing a semiconductor device that is very effective in VLSI requiring multilayer wiring.

問題点を解決するだめの手段 本発明し1、シリコン基板と第一の配線とを接続するコ
ンタクトポール部にチタン膜を形成した後、シリコン基
板とチタン膜の界面に窒素を注入1〜、その後タングス
テン膜を形成するものであり、高温の熱処理により、シ
リコンとチタン膜との界面に、チタンと注入した窒素と
の化合物であるチタンナイトライドが形成される。さら
に、タングステン膜とチタン膜との界面には、チタンと
タングステンの合金が形成される。つ1す、シリコン基
板と、配線であるタングステン膜との間に、チタンナイ
トライド層とチタン・タングステンの合金層との二層を
形成するものである。
Means to Solve the Problems According to the present invention, 1. After forming a titanium film on the contact pole portion that connects the silicon substrate and the first wiring, nitrogen is injected into the interface between the silicon substrate and the titanium film. A tungsten film is formed, and titanium nitride, which is a compound of titanium and implanted nitrogen, is formed at the interface between silicon and titanium film by high-temperature heat treatment. Further, an alloy of titanium and tungsten is formed at the interface between the tungsten film and the titanium film. First, two layers, a titanium nitride layer and a titanium-tungsten alloy layer, are formed between the silicon substrate and the tungsten film that is the wiring.

作用 チタンナイトライドおよびチタンとタングステンとの合
金(たとえば、Ti6W2 、 Ti4W6 、 Ti
2WBなど)Ctシリコン原子と、配線材料であるタン
グステン原子との相互拡散を防止する効果、つまり拡散
障壁としての効果が極めて犬である。本発明57・− の場合、シリコン基板十にチタンナイトライド層とチタ
ンQタングステン合金層との二層を・同時に形成するこ
とができるため、これらがシリコン原子とタングステン
原子との反応の防11Vc極めて有効な手段となり、高
温の熱処理に十分面1えうる配線構造となる。
Working titanium nitride and alloys of titanium and tungsten (e.g. Ti6W2, Ti4W6, Ti
2WB, etc.) The effect of preventing interdiffusion between Ct silicon atoms and tungsten atoms, which are the wiring material, is extremely effective, that is, the effect as a diffusion barrier. In the case of the present invention 57.-, two layers, a titanium nitride layer and a titanium Q-tungsten alloy layer, can be simultaneously formed on a silicon substrate, so that the reaction between silicon atoms and tungsten atoms is extremely prevented by Vc. This is an effective means and results in a wiring structure that can be sufficiently covered for high-temperature heat treatment.

実施例 以下本発明の一実施例を用いて、本発明を具体的に詳述
する。第1図(IL)〜(d)は本発明を用いて二層配
線を形成した場合の半導体集積回路の製造T程順断面図
である。
EXAMPLE Hereinafter, the present invention will be specifically explained in detail using an example of the present invention. FIGS. 1(IL) to 1(d) are sequential cross-sectional views of the manufacturing process of a semiconductor integrated circuit in which two-layer wiring is formed using the present invention.

まず、第1図偽)に示すようにシリコン基板1に形成し
た拡散層21:Pc0VD法により厚さ約1.0μm絶
縁膜3を形成12だ後、拡散層2と電気的に接続するだ
めのコンタクトポール4を形成する。
First, as shown in FIG. 1, a diffusion layer 21 is formed on a silicon substrate 1. After forming an insulating film 3 with a thickness of approximately 1.0 μm using the Pc0VD method, a A contact pole 4 is formed.

つぎに、第2図(b)r:示1ように600人厚0チタ
ン5をスパッタ法により形成した後、全面に、イオン注
入法により、加速電圧10KeV、ドーズ量I X 1
016/ dの条件で窒素を注入し、拡散層2とチタン
6との界面のミキシングを行う。つぎに、6八−/ 第1図(C)に示すように、減圧CVD法により約1 
、0 pm厚タングステン膜6を全面に形成する。反応
ガスには、WF6およびH2を用いる。反応湯度d1約
350°C,反応圧力は、400!ITorrである。
Next, as shown in FIG. 2(b)r: 1, after forming a 600 mm thick layer of titanium 5 by sputtering, the entire surface was implanted by ion implantation at an acceleration voltage of 10 KeV and a dose of I x 1.
Nitrogen is implanted under the conditions of 0.016/d to mix the interface between the diffusion layer 2 and titanium 6. Next, as shown in Figure 1(C), approximately 1
, 0 pm thick tungsten film 6 is formed on the entire surface. WF6 and H2 are used as reaction gases. The reaction temperature d1 is about 350°C, and the reaction pressure is 400! It is ITorr.

1だ、タングステン膜の成長が表面反応律速型の条件で
タングステン膜6を形成しているため、第1図(C)に
示すように、約1 、OIim X 1 、0μmの微
細なコンタクトホール部は、タングステン膜6で埋−ま
ってし捷う。つぎに、タングステン膜6を配線としてパ
ターンニングを行った後、第1 図(d)に示すように
、第一の配線であるタングステン膜6と第二の配線との
絶縁を行うため、CVD法により、約1,0μmのBP
SG膜1o全1oする。ポロンおよびリン濃度は、それ
ぞれ4wt%、JWtチである。BPSG膜1o全1o
でメルトフローする拐料である。本実施例では、800
°CでIIP8G膜のフローおよび焼きしめを行った。
1. Since the tungsten film 6 is formed under conditions where the growth of the tungsten film is rate-determined by surface reaction, as shown in FIG. is filled with the tungsten film 6 and then removed. Next, after patterning is performed using the tungsten film 6 as a wiring, as shown in FIG. BP of about 1.0 μm
SG film 1o total 1o. Poron and phosphorus concentrations are 4 wt% and JWt, respectively. BPSG film 1o total 1o
It is a filtrate that melts and flows. In this example, 800
Flow and baking of the IIP8G film was performed at °C.

その彼、第一の配線と第二の配線との電気的な接続が必
要な部分に、バイアホール11を形成する。最後に、第
二の配線である約1.0μm厚のアルミニウム膜12を
スパッタ法で形成後、パターン二ング丁イ′f!合・経
て、第二の配線の形成う、・兇了する、11だ、タンク
ステン企士リブテンに置き換えてもほとA7ど同じ作用
・効果かある5、発明の効果 本発明によノ1〜は、シリコン基板上に形成した拡散層
と配線との接続部に、シリコン原イに対(7、拡散K”
+”となるチタンシイ1ライド層」、・よびブタンとタ
ングステンの合金層4′セルフアライン(自己整合)で
形成することが容易であり、シリコン基板と接続I7て
いる第一の配線であるタングステン膜を形成17/こ後
の11′II (1,を処坤がh]能となる。そのため
、第一の配線と第一ミの配線との層間絶縁に低温でフロ
ーするBPSG膜を月1いた場合、BPSG膜の平J!
1化が容易にできる。通常の低温のプロセスの場合、層
間絶縁膜のイJ[)化に、エッチバック法やシリカ膜の
塗イti /!−:なと繁剋1な工程を必要とするのに
対し、本発明を用いた」易合、高温中でのフローにより
一″l’、 J’ji化が可能なため、超LSIの多層
配線の形成が極めて容易である。
Then, a via hole 11 is formed in a portion where electrical connection between the first wiring and the second wiring is required. Finally, after forming the second wiring, an aluminum film 12 with a thickness of approximately 1.0 μm, by sputtering, patterning is performed. After that, the formation of the second wiring is completed. 11. Even if it is replaced with Tanksten Ribten, it will have almost the same effect and effect as A7. 5. Effects of the invention According to the present invention 1 ~ is applied to the silicon original layer (7, diffusion K") at the connection part between the diffusion layer formed on the silicon substrate and the wiring
``Titanium film 1 ride layer'', and butane and tungsten alloy layer 4', which is easy to form with self-alignment, and which is the first wiring connected to the silicon substrate I7. After forming 17/11'II (1, the processing becomes h] function. Therefore, a BPSG film that flows at low temperature is applied once a month to the interlayer insulation between the first wiring and the first wiring. In the case, the flat J of BPSG film!
Can be easily integrated into one. In the case of normal low-temperature processes, the interlayer insulating film can be made into a dielectric by using an etch-back method or by applying a silica film. -: In contrast to the process that requires a large number of steps, the present invention can be easily fabricated by flow at high temperatures, making it possible to fabricate multi-layered VLSIs. Forming wiring is extremely easy.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の半導体装置の製造方法を示
す二Iニ程断面図、第2図は従来の半導体装置の製造方
法を示す工程断面図である。 6・ チタン、6  タングステン膜、7−・・・チタ
ンシリサイド層、8・・・チタンナイトライド層、9 
・・・チタンタングステン層。
FIG. 1 is a 2-I cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device. 6. Titanium, 6 Tungsten film, 7-... Titanium silicide layer, 8... Titanium nitride layer, 9
...Titanium tungsten layer.

Claims (2)

【特許請求の範囲】[Claims] (1)シリコン基板上にチタン膜を形成する工程と、上
記シリコン基板とチタン膜界面に窒素を注入する工程と
、上記チタン膜上に高融点金属膜を形成することを備え
たことを特徴とする半導体装置の製造方法。
(1) A feature comprising the steps of forming a titanium film on the silicon substrate, injecting nitrogen into the interface between the silicon substrate and the titanium film, and forming a high melting point metal film on the titanium film. A method for manufacturing a semiconductor device.
(2)高融点金属膜が、モリブデンまたはタングステン
からなる特許請求の範囲第1項記載の半導体装置の製造
方法
(2) A method for manufacturing a semiconductor device according to claim 1, wherein the high melting point metal film is made of molybdenum or tungsten.
JP25897685A 1985-11-19 1985-11-19 Manufacture of semiconductor device Pending JPS62118525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25897685A JPS62118525A (en) 1985-11-19 1985-11-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25897685A JPS62118525A (en) 1985-11-19 1985-11-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62118525A true JPS62118525A (en) 1987-05-29

Family

ID=17327628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25897685A Pending JPS62118525A (en) 1985-11-19 1985-11-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62118525A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6421942A (en) * 1987-07-17 1989-01-25 Hitachi Ltd Manufacture of semiconductor device
JPH03218626A (en) * 1989-11-14 1991-09-26 Mitsubishi Electric Corp Wiring contact structure of semiconductor device and manufacture thereof
US5847459A (en) * 1994-08-31 1998-12-08 Fujitsu Limited Multi-level wiring using refractory metal

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6421942A (en) * 1987-07-17 1989-01-25 Hitachi Ltd Manufacture of semiconductor device
JPH03218626A (en) * 1989-11-14 1991-09-26 Mitsubishi Electric Corp Wiring contact structure of semiconductor device and manufacture thereof
US5847459A (en) * 1994-08-31 1998-12-08 Fujitsu Limited Multi-level wiring using refractory metal
US6204167B1 (en) 1994-08-31 2001-03-20 Fujitsu Limited Method of making a multi-level interconnect having a refractory metal wire and a degassed oxidized, TiN barrier layer

Similar Documents

Publication Publication Date Title
US4398335A (en) Multilayer metal silicide interconnections for integrated circuits
US4866009A (en) Multilayer wiring technique for a semiconductor device
US5093710A (en) Semiconductor device having a layer of titanium nitride on the side walls of contact holes and method of fabricating same
US4488166A (en) Multilayer metal silicide interconnections for integrated circuits
JPS61226959A (en) Semiconductor device and manufacture thereof
EP0194950A2 (en) High temperature interconnect system for an integrated circuit
JPH0370137A (en) Element linking metal wiring layer in semiconductor integrated circuit and manufacture thereof
JPH0464226A (en) Electronic device having metallic fluoride film
JPS62118525A (en) Manufacture of semiconductor device
JPH0194657A (en) Electrode and wiring for semiconductor device
JP3111466B2 (en) Method of manufacturing semiconductor device having plated wiring layer
JP3998937B2 (en) Method for producing TaCN barrier layer in copper metallization process
JPH04196122A (en) Manufacture of semiconductor device
JPS6399546A (en) Manufacture of semiconductor device
JPH02170424A (en) Manufacture of semiconductor device
JPS6213051A (en) Manufacture of semiconductor device
KR930001896B1 (en) Metal line structure of semiconductor apparatus and building method thereof
JPH0677162A (en) Semiconductor device and its manufacture
JPH02222139A (en) Semiconductor device
JPH0245958A (en) Semiconductor device
JPS63147346A (en) Semiconductor integrated circuit device
JPH027543A (en) Connecting electrode formation
JPH0714833A (en) Manufacture of semiconductor device
JPS6352476A (en) Semiconductor device and manufacture thereof
JPH01286447A (en) Semiconductor device and its manufacture