JPH05121727A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JPH05121727A
JPH05121727A JP27943791A JP27943791A JPH05121727A JP H05121727 A JPH05121727 A JP H05121727A JP 27943791 A JP27943791 A JP 27943791A JP 27943791 A JP27943791 A JP 27943791A JP H05121727 A JPH05121727 A JP H05121727A
Authority
JP
Japan
Prior art keywords
film
aluminum
contact hole
silicon alloy
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27943791A
Other languages
Japanese (ja)
Inventor
Kaoru Narita
薫 成田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27943791A priority Critical patent/JPH05121727A/en
Publication of JPH05121727A publication Critical patent/JPH05121727A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To provide the contact-structure and manufacturing method thereof in simple manufacturing steps and at low resistance even if a semiconductor element is miniaturized. CONSTITUTION:A wiring structure is downward composed of an aluminum base wiring material film 108, an aluminum silicon alloy 107 and a barrier film 104 while the contact part is filled up with the aluminum-silicon alloy film 107. Firstly, polycrystalline silicon is buried in a contact hole and then an aluminum film is formed and heat-treated at 400 deg.C-500 deg.C to be alloyed for the formation of this aluminum-silicon alloy film 107. Through these procedures, the heat treatment at high temperature can be eliminated to mitigate the effect thereof on an element such as transistor, etc., in comparison with the case of filling up the contact hole with the polycrystalline silicon thereby enabling the buried-in contact using a barrier metal to be formed due to the applicable heat-treatment at lower temperature so that the element even if miniaturized may be manufactured in simple steps at low resistance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置、特に配線の
接合部の構造及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a wiring joint and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来の半導体装置の配線間接合は、例え
ば図4に示す様な構造及び製造方法をとっていた。すな
わち、図4(a)に示す様に半導体基体1の一主表面部
の、拡散層2上の層間絶縁膜3にコンタクト孔3Aを開
孔し、次に図4(b)に示す様に、多結晶シリコン膜5
をCVD法により形成し、コンタクト孔3Aを埋め込
み、次に、拡散層2が例えばN型の場合は、多結晶シリ
コン膜4に、リンを900℃前後の温度で熱拡散する
か、イオン注入により、リンを注入後、800℃〜90
0℃の温度で熱処理する等の方法によって、導電性をも
たせ、次に図4(c)に示す様に多結晶シリコン膜5を
全面エッチングし、コンタクト孔内のみに多結晶シリコ
ンを残し、次に図4(d)に示す様に、アルミニウム膜
6をスパッタ法によって形成していた。
2. Description of the Related Art A conventional interconnection between wirings of a semiconductor device has a structure and a manufacturing method as shown in FIG. That is, as shown in FIG. 4 (a), a contact hole 3A is formed in the interlayer insulating film 3 on the diffusion layer 2 on one main surface portion of the semiconductor substrate 1, and then as shown in FIG. 4 (b). , Polycrystalline silicon film 5
Is formed by a CVD method to fill the contact hole 3A, and then, when the diffusion layer 2 is, for example, an N type, phosphorus is thermally diffused into the polycrystalline silicon film 4 at a temperature of about 900 ° C. or by ion implantation. , Phosphorus after injection, 800 ℃ ~ 90
Conductivity is imparted by a method such as heat treatment at a temperature of 0 ° C., and then the polycrystalline silicon film 5 is entirely etched as shown in FIG. 4C to leave the polycrystalline silicon only in the contact holes. As shown in FIG. 4D, the aluminum film 6 was formed by the sputtering method.

【0003】[0003]

【発明が解決しようとする課題】この従来の半導体装置
の配線間接合の構造及び製造方法は、多結晶シリコンに
導電性をもたせるために、800℃〜900℃の熱処理
が必要となるため、工程が繁雑となり、トランジスタな
どの素子の微細化に悪影響を及ぼすばかりでなく、コン
タクト部にバリアメタル膜(上述の熱処理でシリコンと
反応する)を用いることが困難となり、コンタクト抵抗
のばらつき等の問題がおこり、コンタクトの微細化に不
利であるという問題点がある。
This conventional structure and manufacturing method for the interconnection between wirings of a semiconductor device requires a heat treatment at 800 ° C. to 900 ° C. in order to impart conductivity to the polycrystalline silicon. Not only has an adverse effect on the miniaturization of elements such as transistors, but also makes it difficult to use a barrier metal film (which reacts with silicon in the above heat treatment) in the contact portion, which causes problems such as variations in contact resistance. However, there is a problem that it is disadvantageous in miniaturization of contacts.

【0004】[0004]

【課題を解決するための手段】本発明の半導体装置は、
半導体チップの所定の導電領域を被覆する絶縁膜と、前
記絶縁膜の前記導電領域上に開孔されたコンタクト孔
と、前記コンタクト孔部で前記導電領域と接触して前記
絶縁膜に被着されたバリアメタル膜と、前記コンタクト
孔を前記バリアメタル膜を介して埋め込んで形成された
アルミニウム−シリコン合金膜および前記アルミニウム
−シリコン合金膜を被膜するアルミニウム系配線材料膜
からなる上層配線とを有するというものである。
The semiconductor device of the present invention comprises:
An insulating film that covers a predetermined conductive region of a semiconductor chip, a contact hole formed on the conductive region of the insulating film, and a contact hole portion that contacts the conductive region and is deposited on the insulating film. A barrier metal film, and an upper layer wiring composed of an aluminum-silicon alloy film formed by burying the contact hole via the barrier metal film and an aluminum-based wiring material film coating the aluminum-silicon alloy film. It is a thing.

【0005】又、本発明の半導体装置の製造方法は、導
電領域を有する半導体チップの表面を絶縁膜で被覆する
工程と、前記絶縁膜の前記導電領域上にコンタクト孔を
開口する工程と、前記コンタクト孔部で前記導電領域と
接触するバリアメタル膜を形成する工程と、前記コンタ
クト孔を前記バリアメタル膜を介して埋め込む多結晶シ
リコン膜を堆積する工程と、前記多結晶シリコン膜にア
ルミニウム膜を被着する工程と、前記多結晶シリコン膜
と前記アルミニウム膜とを反応させてアルミニウム−シ
リコン合金膜に変換する熱処理工程と、前記アルミニウ
ム−シリコン合金膜にアルミニウム系配線材料膜を被着
する工程と、前記アルミニウム系配線材料膜および前記
アルミニウム−シリコン合金膜とをパターニングして上
層配線を形成するというものである。
Further, the method of manufacturing a semiconductor device of the present invention comprises the steps of covering the surface of a semiconductor chip having a conductive region with an insulating film, forming a contact hole on the conductive region of the insulating film, Forming a barrier metal film in contact with the conductive region in the contact hole portion, depositing a polycrystalline silicon film filling the contact hole through the barrier metal film, and forming an aluminum film on the polycrystalline silicon film. A step of depositing, a heat treatment step of reacting the polycrystalline silicon film and the aluminum film to convert into an aluminum-silicon alloy film, and a step of depositing an aluminum-based wiring material film on the aluminum-silicon alloy film. Patterning the aluminum-based wiring material film and the aluminum-silicon alloy film to form an upper wiring. It is intended to refer.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0007】図1(a)〜(c)及び図2(a),
(b)は、本発明の一実施例をその製造工程に沿って説
明するための工程順断面図である。
1A to 1C and 2A,
(B) is a process order cross-sectional view for explaining one embodiment of the present invention along with its manufacturing process.

【0008】まず、図1(a)に示す様に、半導体基体
101上に形成された拡散層102(導電領域)上の層
間絶縁膜103(半導体基体表面のゲート酸化膜上に設
けてもよい。)に0.5μm×0.5μmのコンタクト
孔103Aを開孔し、バリアメタル層104として、下
層にチタン膜約30nm、上層に窒化チタン膜約100
nmの2層構造をスパッタ法により形成する。
First, as shown in FIG. 1A, an interlayer insulating film 103 on a diffusion layer 102 (conductive area) formed on a semiconductor substrate 101 (a gate oxide film on the surface of the semiconductor substrate) may be provided. 0.5 .mu.m.times.0.5 .mu.m contact holes 103A are formed in the above.
A two-layer structure of nm is formed by the sputtering method.

【0009】次に図1(b)に示す様に、多結晶シリコ
ン膜105を、厚さ約300nm、CVD法により形成
しコンタクト孔103Aを埋め込む。
Next, as shown in FIG. 1B, a polycrystalline silicon film 105 having a thickness of about 300 nm is formed by a CVD method to fill the contact hole 103A.

【0010】次に、図1(c)に示す様に、アルミニウ
ム膜103を厚さ約100nm程度形成する。次に、水
素雰囲気中で温度400℃〜500℃の熱処理を30分
程度行ない、多結晶シリコン膜105と、第1のアルミ
ニウム膜106とを反応させ、図2(a)に示すよう
に、アルミニウム−シリコン合金膜107に変換させ
る。この水素雰囲気中の熱処理は、通常、トランジスタ
素子等安定化のためにアルミニウム配線形成後行なわれ
る水素アニールも兼ねている。
Next, as shown in FIG. 1C, an aluminum film 103 having a thickness of about 100 nm is formed. Next, heat treatment at a temperature of 400 ° C. to 500 ° C. is performed in a hydrogen atmosphere for about 30 minutes to react the polycrystalline silicon film 105 with the first aluminum film 106, and as shown in FIG. -Convert to the silicon alloy film 107. This heat treatment in a hydrogen atmosphere also serves as hydrogen annealing that is usually performed after the formation of aluminum wiring for stabilizing transistor elements and the like.

【0011】次に、図2(b)に示す様に、Al−1%
Si−0.5%Cuからなるアルミニウム系配線材料膜
108を厚さ400nm程度スパッタ法により形成す
る。次に、アルミニウム系配線材料膜108、アルミニ
ウム−シリコン合金膜107およびバリアメタル膜10
4の3層膜をフォトリソグラフィー法及びドライエッチ
ング法によってパターニングして上層配線を形成するこ
とにより、本発明の半導体装置の構造を得る。コンタク
ト部にバリアメタル膜を使用しているのでばらつきの少
ない良好なコンタクトを実現できる。また、コンタクト
の形成に不純物の導入を必要としないのでトランジスタ
などの素子を形成したのちに、半導体チップを高温にさ
らさなくてよいので微細化が容易となる。
Next, as shown in FIG. 2 (b), Al-1%
An aluminum-based wiring material film 108 made of Si-0.5% Cu is formed by a sputtering method to have a thickness of about 400 nm. Next, the aluminum-based wiring material film 108, the aluminum-silicon alloy film 107, and the barrier metal film 10
The structure of the semiconductor device of the present invention is obtained by patterning the three-layer film of No. 4 by the photolithography method and the dry etching method to form the upper wiring. Since the barrier metal film is used in the contact portion, a good contact with less variation can be realized. Further, since it is not necessary to introduce impurities to form contacts, it is not necessary to expose the semiconductor chip to high temperature after forming elements such as transistors, so that miniaturization is facilitated.

【0012】図3(a)〜(c)は、本発明の第2の実
施例を製造工程に沿って説明するための工程順断面図で
ある。
3A to 3C are sectional views in order of steps for explaining the second embodiment of the present invention along with the manufacturing steps.

【0013】第1の実施例と同様にして、図1(b)に
示すように、多結晶シリコン膜105を形成後、これを
全面エッチングし図3(a)に示す様に多結晶シリコン
膜205をコンタクト孔内のみに残す。
Similar to the first embodiment, after the polycrystalline silicon film 105 is formed as shown in FIG. 1B, the entire surface is etched to form the polycrystalline silicon film as shown in FIG. 3A. 205 is left only in the contact hole.

【0014】次に図3(b)に示す様にアルミニウム膜
206を形成し、第1の実施例と同様の熱処理を行なう
ことによって、図3(c)に示す様に、コンタクト孔と
その近傍にアルミニウム−シリコン合金膜207を形成
し、次に第1の実施例と同様にアルミニウム系配線材料
膜208を形成し、パターニングして上層配線を形成す
る。
Next, an aluminum film 206 is formed as shown in FIG. 3 (b), and the same heat treatment as in the first embodiment is performed, so that the contact hole and its vicinity are formed as shown in FIG. 3 (c). Then, an aluminum-silicon alloy film 207 is formed thereon, and then an aluminum-based wiring material film 208 is formed in the same manner as in the first embodiment and patterned to form an upper wiring.

【0015】第2の実施例の場合、全面エッチング工程
の追加が必要であるが、配線層の縦方向の厚さが薄く形
成できるため、微細化にさらに有利となる。
In the case of the second embodiment, it is necessary to add an entire surface etching step, but since the thickness of the wiring layer in the vertical direction can be formed thin, it is further advantageous for miniaturization.

【0016】以上導電領域が拡散層の場合について説明
したが、下層配線と上層配線とのコンタクト部に本発明
を適用しうることは当業者に明らかであろう。
Although the case where the conductive region is the diffusion layer has been described above, it will be apparent to those skilled in the art that the present invention can be applied to the contact portion between the lower layer wiring and the upper layer wiring.

【0017】[0017]

【発明の効果】以上説明したように本発明は、コンタク
ト孔を、アルミニウム−シリコン合金膜で埋め込む構造
をとり、この構造を実現するために、まず、多結晶シリ
コンでコンタクト孔を埋め込み、次に、アルミニウム膜
を形成し、低い温度(400℃〜500℃)で熱処理を
行う方法をとっているので、従来の多結晶シリコン膜に
よるコンタクト埋込みにおいて多結晶シリコン膜に導電
性をもたせるために必要な高い温度(800℃〜900
℃)の熱処理が不要となり、トランジスタなどの素子に
与える悪影響が無くなり、また、高い温度の熱処理に弱
いバリアメタル膜を使用することも可能となる。アルミ
ニウム−シリコン合金の低抵抗性およびバリアメタル膜
の効果も相まって、コンタクトサイズを縮小しても、低
い抵抗のコンタクトが実現できる。また、アルミニウム
とシリコンを合金化する熱処理を水素雰囲気中で行なう
と、通常の水素アニールを兼ねることができるため、よ
り製造工程を簡略化できるという効果もある。
As described above, according to the present invention, the contact hole is filled with the aluminum-silicon alloy film. In order to realize this structure, the contact hole is first filled with polycrystalline silicon, and then the contact hole is filled with polycrystalline silicon. Since an aluminum film is formed and a heat treatment is performed at a low temperature (400 ° C. to 500 ° C.), it is necessary to give conductivity to the polycrystalline silicon film when the contact is filled with the conventional polycrystalline silicon film. High temperature (800 ℃ -900
The heat treatment at (.degree. C.) is not necessary, the adverse effect on elements such as transistors is eliminated, and it is possible to use a weak barrier metal film for heat treatment at high temperature. Due to the low resistance of the aluminum-silicon alloy and the effect of the barrier metal film, a contact with low resistance can be realized even if the contact size is reduced. In addition, when the heat treatment for alloying aluminum and silicon is performed in a hydrogen atmosphere, it is possible to also serve as a normal hydrogen anneal, so that there is an effect that the manufacturing process can be further simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を説明するための(a)
〜(c)に分図して示す工程順断面図である。
FIG. 1A is a view for explaining the first embodiment of the present invention.
FIG. 4C is a sectional view in order of the processes, which is divided into FIGS.

【図2】第1の実施例を説明するため(a),(b)に
分図して示す工程順断面図である。
2A to 2C are cross-sectional views in order of the processes, which are divided into (a) and (b) for explaining the first embodiment.

【図3】第2の実施例を説明するため(a)〜(c)に
分図して示す工程順断面図である。
3A to 3C are cross-sectional views in order of the processes, which are divided into (a) to (c) for describing the second embodiment.

【図4】従来例を説明するため(a)〜(d)に分図し
て示す工程順断面図である。
4A to 4D are cross-sectional views in order of the processes, which are divided into (a) to (d) for describing a conventional example.

【符号の説明】[Explanation of symbols]

1,101,201 半導体基体 2,102,202 拡散層 3,103,203 層間絶縁膜 3A,103A コンタクト孔 104,204 バリアメタル膜 5,105,205 多結晶シリコン膜 6,106,306,406 アルミニウム膜 107,207 アルミニウム−シリコン合金膜 108,208 アルミニウム系配線材料膜 1, 101, 201 Semiconductor substrate 2, 102, 202 Diffusion layer 3, 103, 203 Interlayer insulating film 3A, 103A Contact hole 104, 204 Barrier metal film 5, 105, 205 Polycrystalline silicon film 6, 106, 306, 406 Aluminum Film 107,207 Aluminum-silicon alloy film 108,208 Aluminum-based wiring material film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップの所定の導電領域を被覆す
る絶縁膜と、前記絶縁膜の前記導電領域上に開口された
コンタクト孔と、前記コンタクト孔部で前記導電領域と
接触して前記絶縁膜に被着されたバリアメタル膜と、前
記コンタクト孔を前記バリアメタル膜を介して埋め込ん
で形成されたアルミニウム−シリコン合金膜および前記
アルミニウム−シリコン合金膜を被覆するアルミニウム
系配線材料膜からなる上層配線とを有することを特徴と
する半導体装置。
1. An insulating film covering a predetermined conductive region of a semiconductor chip, a contact hole opened on the conductive region of the insulating film, and the insulating film contacting the conductive region at the contact hole portion. An upper layer wiring composed of a barrier metal film deposited on the substrate, an aluminum-silicon alloy film formed by embedding the contact hole through the barrier metal film, and an aluminum-based wiring material film covering the aluminum-silicon alloy film. And a semiconductor device.
【請求項2】 導電領域を有する半導体チップの表面を
絶縁膜で被覆する工程と、前記絶縁膜の前記導電領域上
にコンタクト孔を開口する工程と、前記コンタクト孔部
で前記導電領域と接触するバリアメタル膜を形成する工
程と、前記コンタクト孔を前記バリアメタル膜を介して
埋め込む多結晶シリコン膜を堆積する工程と、前記多結
晶シリコン膜にアルミニウム膜を被着する工程と、前記
多結晶シリコン膜と前記アルミニウム膜とを反応させて
アルミニウム−シリコン合金膜に変換する熱処理工程
と、前記アルミニウム−シリコン合金膜にアルミニウム
系配線材料膜を被着する工程と、前記アルミニウム系配
線材料膜および前記アルミニウム−シリコン合金膜とを
パターニングして上層配線を形成することを特徴とする
半導体装置の製造方法。
2. A step of coating a surface of a semiconductor chip having a conductive region with an insulating film, a step of forming a contact hole on the conductive region of the insulating film, and a step of contacting the conductive region at the contact hole portion. A step of forming a barrier metal film, a step of depositing a polycrystalline silicon film filling the contact hole with the barrier metal film interposed therebetween, a step of depositing an aluminum film on the polycrystalline silicon film, and a step of depositing the polycrystalline silicon film. A heat treatment step of reacting a film with the aluminum film to convert it into an aluminum-silicon alloy film; a step of depositing an aluminum-based wiring material film on the aluminum-silicon alloy film; the aluminum-based wiring material film and the aluminum A method for manufacturing a semiconductor device, characterized by patterning a silicon alloy film to form an upper wiring .
JP27943791A 1991-10-25 1991-10-25 Semiconductor device and manufacturing method thereof Pending JPH05121727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27943791A JPH05121727A (en) 1991-10-25 1991-10-25 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27943791A JPH05121727A (en) 1991-10-25 1991-10-25 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JPH05121727A true JPH05121727A (en) 1993-05-18

Family

ID=17611059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27943791A Pending JPH05121727A (en) 1991-10-25 1991-10-25 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH05121727A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786210A (en) * 1993-09-14 1995-03-31 Nec Corp Manufacture of semiconductor device
US5691571A (en) * 1994-12-28 1997-11-25 Nec Corporation Semiconductor device having fine contact hole with high aspect ratio
US5847461A (en) * 1995-05-05 1998-12-08 Applied Materials, Inc. Integrated circuit structure having contact openings and vias filled by self-extrusion of overlying metal layer
USRE40748E1 (en) * 1999-03-15 2009-06-16 Sony Corporation Process for producing semiconductor device
JP2015162620A (en) * 2014-02-28 2015-09-07 三菱電機株式会社 Silicon carbide semiconductor device manufacturing method and silicon carbide semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786210A (en) * 1993-09-14 1995-03-31 Nec Corp Manufacture of semiconductor device
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