JPS60224229A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60224229A
JPS60224229A JP59078566A JP7856684A JPS60224229A JP S60224229 A JPS60224229 A JP S60224229A JP 59078566 A JP59078566 A JP 59078566A JP 7856684 A JP7856684 A JP 7856684A JP S60224229 A JPS60224229 A JP S60224229A
Authority
JP
Japan
Prior art keywords
layer
film
phosphorus
insulating film
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59078566A
Other languages
Japanese (ja)
Inventor
Izumi Tezuka
手塚 泉
Shuichi Sakurai
修一 桜井
Toru Inaba
稲葉 透
Masato Matsumoto
正人 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP59078566A priority Critical patent/JPS60224229A/en
Publication of JPS60224229A publication Critical patent/JPS60224229A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC

Abstract

PURPOSE:To stop decreasing of moisture resistance due to the influence of phosphorus to the first wiring layer without altering the present process by forming the first layer wiring of wirings through an inorganic insulating film containing no phosphorus on an inorganic insulating film which contains phosphorus oxide glass layer on the surface. CONSTITUTION:A glass (PSG) film 7 which contains high density phosphorus oxide is formed on the surface of a silicon oxide 2 for coating the surface of a semiconductor element formed on the other portion of the surface of a substrate 1. An inorganic insulating film 8 which does not contains phosphorus, formed on the film 7 is made, for example, of glass (SOG) by coating and silicon oxide by CVD not doped with nitride or phosphorus due to plasma discharging. The first layer wirings made of aluminum are formed as an electrode contacted with low resistance with the element, and partly extended on the film 8.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置に関するものであって、特にパッシ
ベイション膜にポリイミド系樹脂を使用したアルミニウ
ム多層配線構造を有する半導体装置の耐湿性向上技術忙
関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and more particularly to a technology for improving moisture resistance of a semiconductor device having an aluminum multilayer wiring structure using a polyimide resin for a passivation film.

〔背景技術〕[Background technology]

ICやLSI等の半導体装置において、1チツプあたり
の素子数が増大する忙伴い、素子間を接続するためのア
ルミニウム配線を2層あるいはそれ以上の多層構造とす
ることが行われている。
2. Description of the Related Art As the number of elements per chip increases in semiconductor devices such as ICs and LSIs, aluminum wiring for connecting elements is now formed into a multilayer structure of two or more layers.

本発明者においては、第1図圧水すよう忙シリコン半導
体基体10表面にシリコン酸化膜2で覆われたトランジ
スタ等の半導体素子を形成し、上記シリコン酸化膜2の
上に第1層のアルミニウム配線3を形成し、第1層配線
3の上をポリイミド系樹脂からなる層間膜4で覆い、層
間膜4上に第2層アルミニウム配線5を形成し、さらに
この上をポリイミド系樹脂からなる保護膜6を形成した
2層配線構造を採用している。
In the present inventor, a semiconductor element such as a transistor covered with a silicon oxide film 2 is formed on the surface of a silicon semiconductor substrate 10 as shown in FIG. A wiring 3 is formed, the first layer wiring 3 is covered with an interlayer film 4 made of polyimide resin, a second layer aluminum wiring 5 is formed on the interlayer film 4, and a protective layer made of polyimide resin is formed on the interlayer film 4. A two-layer wiring structure in which a film 6 is formed is adopted.

ポリイミド系樹脂は配線の上に形成して表面の平坦性を
確保でき、高い耐熱性を有するので眉間膜や保護膜忙使
われているが、層間の隙間を通じて側面から水が侵入す
ることによるアルミニウム配線腐食が問題となっている
Polyimide resin can be formed on top of the wiring to ensure surface flatness, and it has high heat resistance, so it is often used as a glabellar membrane or protective film, but aluminum Wiring corrosion is a problem.

そこで本発明者により、2層配線構造において、第2層
(上層)のアルミニウム配線材料に耐湿性の高いシリコ
ンを含んだアルミニウムを使うことにより上からの水の
侵入に対するアルミニウム配線腐食を防止する方法が提
案された(特開昭57−154857 )。
Therefore, the present inventor has devised a method for preventing aluminum wiring corrosion due to water intrusion from above by using aluminum containing highly moisture-resistant silicon as the second layer (upper layer) aluminum wiring material in a two-layer wiring structure. was proposed (Japanese Patent Application Laid-Open No. 57-154857).

しかし、第1層(下層)のアルミニウム配線3では、シ
リコン入りアルミニウムを使う場合、シリコン残滓が生
じる問題があり、またトランジスタの一部がシ目ットキ
舎バリアとして使われる場合のバリアハイドを低値に保
つために純アルミニウムが使われるため、側面方向(チ
ップ周辺方向)からの水の侵入による配線腐食の問題は
依然として解決されていないことがわかった。
However, in the first layer (lower layer) of the aluminum wiring 3, when aluminum containing silicon is used, there is a problem in that silicon residue is generated, and when a part of the transistor is used as a barrier, the barrier hydride has a low value. Because pure aluminum is used to maintain the temperature of the chip, the problem of wiring corrosion due to water intrusion from the sides (around the chip) remains unresolved.

本発明者はこのような第1層のアルミニウム配線不良の
原因を追求したところ、特にチップ周辺部の第1層アル
ミニウム配#I3に腐食が起りやすく、この第1層の配
線が形成されるシリコン酸化膜表面の7オスシリケート
ガラス(PSG)膜7のリン濃度に関係があることが判
った。
The inventor of the present invention investigated the cause of such defects in the first layer aluminum wiring, and found that corrosion is particularly likely to occur in the first layer aluminum wiring #I3 around the chip, and that the silicon on which this first layer wiring is formed It was found that there is a relationship with the phosphorus concentration of the 7-osilicate glass (PSG) film 7 on the surface of the oxide film.

現在のポリイミド樹脂を層間膜に甲いた2層配線構造を
有する半導体製造において、第1層アルミニウム配線の
下地は4mol のリン濃度をもつPSGgで、これは
npn)?ンジスタのエミッタ拡散後に素子表面に生成
される約12mo1 程度のリンガラスを含むシリコン
酸化物(Sift)であり、現在、第1層配線に使用さ
れている純アルミニウムは下地のリンの影響を受け易い
ため耐湿性が低下することがわかった。
In current semiconductor manufacturing that has a two-layer wiring structure with polyimide resin as an interlayer film, the base of the first layer aluminum wiring is PSGg with a phosphorus concentration of 4 mol, which is npn)? Sift is silicon oxide (Sift) containing about 12 mo1 of phosphorous glass that is generated on the device surface after the emitter diffusion of the resistor, and the pure aluminum currently used for the first layer wiring is easily affected by the underlying phosphorus. It was found that this resulted in a decrease in moisture resistance.

一方、第2層配線圧はシリコン入りのアルミニウムを用
いることにより耐湿性を向上しており、したがって第1
層アルミニウム配線によってICの寿命が左右されると
いえることがわかった。
On the other hand, the moisture resistance of the second layer wiring is improved by using silicon-containing aluminum, and therefore the first layer
It has been found that the life span of an IC can be determined by the layered aluminum wiring.

〔発明の目的〕[Purpose of the invention]

本発明は上記した点にかんがみてなされたもので、ポリ
イミド系樹脂で覆われた第1層アルミニウム配線の耐湿
性を向上できる半導体装置技術を提供することにある。
The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a semiconductor device technology that can improve the moisture resistance of a first layer aluminum wiring covered with a polyimide resin.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概贋
を簡単に説明すれば下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、半導体基体の一主面に複数の半導体素子が形
成され、上記半導体素子は表面にリン酸化物ガラス層を
含む無機絶縁膜(リンガラス)で覆われ、この無機絶縁
膜上に1層又は複数層のアルミニウム配線が形成され、
これら配線上や配線間はポリイミド樹脂などの有機絶縁
膜で覆われてなる半導体装置において、上記表面にリン
酸化物ガラス層を含む無機絶縁膜の上にリンを含まない
無機絶縁膜を介して上記配線のうち第1層(下層)の配
線を形成することにより、現在のプロセスを変更するこ
となく、第1層配線へのリンの影響による耐湿性の低下
を阻止し耐湿性の向上ができ、発明の目的を達成できる
That is, a plurality of semiconductor elements are formed on one main surface of a semiconductor substrate, the semiconductor elements are covered with an inorganic insulating film (phosphorus glass) containing a phosphorous oxide glass layer on the surface, and one or more layers are formed on the inorganic insulating film. Multiple layers of aluminum wiring are formed,
In a semiconductor device in which the wiring is covered with an organic insulating film such as polyimide resin, an inorganic insulating film that does not contain phosphorus is placed on the surface of the inorganic insulating film that includes a phosphorus oxide glass layer. By forming the first layer (lower layer) of the wiring, it is possible to prevent the deterioration of moisture resistance due to the influence of phosphorus on the first layer wiring and improve the moisture resistance without changing the current process. The purpose of the invention can be achieved.

〔実施例〕〔Example〕

第2図は本発明の一実施例を示すものであって、ポリイ
ミド系樹脂を層間膜に使用した2層配線構造を有する半
導体装置の縦断面図である。
FIG. 2 shows one embodiment of the present invention, and is a longitudinal sectional view of a semiconductor device having a two-layer wiring structure using polyimide resin as an interlayer film.

1はシリコン半導体基体であって、図示されないが基体
10表面の他の部分忙トランジスタ等の半導体素子が形
成されている。2は上記半導体素子の表面を覆うシリコ
ン酸化物(Sin、)膜である。このシリコン酸化物2
0表面に高濃度のリン酸化物を含むガラス(PSG)膜
7が形成されている。8はリンを全く含まない無機絶縁
膜8で、例えば塗布によるガラス(SOG)プラズマ放
電によるナイトライド(シリコン窒化物)又はリンが全
くドープされないCVD(気相化学堆積)Kよるシリコ
ン酸化物(Sift)からなる。
Reference numeral 1 denotes a silicon semiconductor substrate, and although not shown, semiconductor elements such as busy transistors are formed on other parts of the surface of the substrate 10 . 2 is a silicon oxide (Sin) film covering the surface of the semiconductor element. This silicon oxide 2
A glass (PSG) film 7 containing a high concentration of phosphorous oxide is formed on the surface of the substrate. Reference numeral 8 denotes an inorganic insulating film 8 containing no phosphorus, such as glass (SOG) by coating, nitride (silicon nitride) by plasma discharge, or silicon oxide (Sift) by CVD (vapor phase chemical deposition) K, which is not doped with phosphorus at all. ).

6はアルミニウム(主として純アルミニウム)からなる
第1層配線で半導体素子に低抵抗接触する電極として形
成され一部は無機絶縁膜8上忙延在する。
Reference numeral 6 denotes a first layer wiring made of aluminum (mainly pure aluminum), which is formed as an electrode that makes low resistance contact with the semiconductor element, and a portion thereof extends over the inorganic insulating film 8 .

4はポリイミド樹脂からなる層間絶縁膜である。4 is an interlayer insulating film made of polyimide resin.

5はアルミニウム又はシリコン入りアルミニウムからな
る第2層配線て一部は層間膜4のスルーホールを通して
第2層配線忙接続される。
Reference numeral 5 denotes a second layer wiring made of aluminum or silicon-containing aluminum, and a portion thereof is connected to the second layer wiring through a through hole in the interlayer film 4.

6はポリイミド樹脂からなるプロテクション(保護用)
膜である。
6 is protection made of polyimide resin (for protection)
It is a membrane.

基体上のシリコン酸化膜2の表面のリン酸化物ガラス7
のリンにより、その上圧形成された第1層配線のアルミ
ニウムの粒界の腐食を促進させると考えられるが、本発
明のようにこのリン酸化物のガラス7の上にリンを全く
含まないプラズマナイトライドのようなリンを全く含ま
ない無機絶縁膜で覆っであることにより、その上に形成
されたアルミニウム配#3において下地のリンの影響を
阻止し、耐湿性が向上できる。
Phosphate glass 7 on the surface of silicon oxide film 2 on the substrate
It is thought that the phosphorus accelerates the corrosion of the aluminum grain boundaries of the first layer wiring formed under the upper pressure, but as in the present invention, plasma containing no phosphorus is applied to the phosphorus oxide glass 7 By covering with an inorganic insulating film such as nitride that does not contain any phosphorus, the influence of the underlying phosphorus can be prevented on the aluminum wiring #3 formed thereon, and the moisture resistance can be improved.

第3図反型第7図は本発明の他の実施例を示すものであ
り、半導体基体の一主表面にnpn )ランジスタを有
するIC(半導体集積回路)の製造プロセスの一部工程
断面図である。以下、各工程忙従って説明する。
Figure 3 shows another embodiment of the present invention, and is a partial step sectional view of the manufacturing process of an IC (semiconductor integrated circuit) having an NPN (npn) transistor on one main surface of a semiconductor substrate. be. Each process will be explained below.

(1)第3図圧水すように1通常のバイボー?ICのプ
ロセスに従ってp−型シリコン基板9上忙n+型埋込層
10を埋め込んだ形でn−型シリコン層11をエピタキ
シャル成長させ、表面酸化膜12をマスクにボロン(B
)イオン打込み拡散してp型アイソレーション部13を
形成する。
(1) 1 normal bibo as shown in figure 3 pressure water? In accordance with the IC process, an n-type silicon layer 11 is epitaxially grown on a p-type silicon substrate 9 with an n+-type buried layer 10 buried therein, and boron (B) is grown using the surface oxide film 12 as a mask.
) A p-type isolation section 13 is formed by ion implantation and diffusion.

(2)ホトレジスト処理により表面酸化膜12の一部を
窓開し、選択的不純物イオン打込ろ工程を経て一つのn
″″型シリコン領域11内に第4図に示すようにnpn
 )?ンジスタのペースとなるp層領域14及びコレク
ターコンタクトとなるn+型領領域15形成する。これ
らの工程で素子周辺フィールド部の酸化膜は12000
 A程度に厚くなる。
(2) A part of the surface oxide film 12 is opened by photoresist treatment, and one n.
In the "" type silicon region 11, as shown in FIG.
)? A p layer region 14 which will serve as a transistor pace and an n+ type region 15 which will serve as a collector contact are formed. Through these steps, the oxide film in the peripheral field area of the device is reduced to 12,000 yen.
The thickness will be about A.

このあと、同図に示すようにエミッタ及びコレクタ・コ
ンタクト部の酸化膜を取り除き、リンを含む酸素雰囲気
中で、加熱することにより全面忙高濃度リン酸化物を含
むガラス(PSG)層16をデポジットし、窓開部を通
じて半導体内にリンを拡散することによりエミッタn+
型領域17を得る。酸化膜表面のPSG層(厚さ300
A程度)16は金属不純物によるpn接合汚染防止用と
してこのまま残存させる。
After that, as shown in the same figure, the oxide film on the emitter and collector contacts is removed, and a glass (PSG) layer 16 containing highly concentrated phosphorus oxide is deposited on the entire surface by heating in an oxygen atmosphere containing phosphorus. By diffusing phosphorus into the semiconductor through the window opening, the emitter n+
A mold area 17 is obtained. PSG layer on the surface of the oxide film (thickness 300
A) 16 is left as is to prevent contamination of the pn junction by metal impurities.

+3] CV D (気相化学堆積法)によるリンのド
ープされないシリコン酸化物を第5図圧水すよ5KPS
Gの形成された基体全面に堆積し、ノン参ドープSin
、膜18をxooo1程度の厚さに形成する。このあと
、コンタクトホトエッチを行って各領域の電極取出し部
を窓開する。この場合、コンタクト部以外のノンドープ
Si0g膜はアルミニウム配線を少なくとも周辺部から
囲むように残し、他の不要部を四時忙取除いてもよい。
+3] Silicon oxide which is not doped with phosphorus by CVD (vapor phase chemical deposition method) is heated to 5KPS in Figure 5.
G is deposited on the entire surface of the substrate, and non-sulfur-doped Sin
, the film 18 is formed to a thickness of about xooo1. After this, contact photoetching is performed to open the electrode extraction portions in each region. In this case, the non-doped SiOg film other than the contact portion may be left so as to surround at least the peripheral portion of the aluminum wiring, and other unnecessary portions may be removed at any time.

141 アルミニウムを全面に蒸着(又はスパッタ)し
、パターニングエッチして第6図に示すように各半導体
領域にコンタクトするアルミニウム電極19を形成する
。このアルミニウム電極の一部は酸化膜上に延在してア
ルミニウム配線として使用される。
141 Aluminum is deposited (or sputtered) on the entire surface and patterned and etched to form aluminum electrodes 19 in contact with each semiconductor region as shown in FIG. A portion of this aluminum electrode extends over the oxide film and is used as an aluminum wiring.

(5)全面忙ポリイミド樹脂を塗布し、ベーク後の最終
の厚さが1.75〜z、0μmの保護絶縁膜20を形成
する。このポリイミド樹脂膜はポリイミド樹脂のプレポ
リマー溶液、又は半型合物溶液(たとえば、N−チメチ
ルー2−ピロリドンもしくは・N・N−ジメチル−アセ
トアミドなどの溶液とする)をスピンナ塗布(1〜2回
)した後、溶媒成分を蒸発させ、さらに200〜300
℃でベーク(熱処理)することにより重合硬化させて上
記被膜を形成する。
(5) Apply polyimide resin to the entire surface to form a protective insulating film 20 having a final thickness of 1.75 to 0 μm after baking. This polyimide resin film is made by applying a prepolymer solution of polyimide resin or a half-form compound solution (for example, a solution of N-thimethyl-2-pyrrolidone or .N.N-dimethyl-acetamide) using a spinner (once or twice). ), the solvent component is evaporated, and further 200 to 300
The film is polymerized and cured by baking (heat treatment) at .degree. C. to form the above-mentioned film.

この実施例において、ノンドープCVD・SiO2膜は
現在のパイボー2ICプロセス技術では容易に形成する
ことが可能であるから、リンの影響を防止させることが
でき、耐湿性が向上する。
In this embodiment, since the non-doped CVD SiO2 film can be easily formed using the current Pivot 2 IC process technology, the influence of phosphorus can be prevented and the moisture resistance is improved.

以上本発明者忙よってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施側圧限定される
ものではな(、その要旨を逸脱しない範囲で種々変更可
能である。
Although the invention made by the present inventors has been specifically explained based on examples, the present invention is not limited to the above-mentioned implementation pressure (and various changes can be made without departing from the gist thereof).

たとえば、PSG層の土に形成するリンを含まない無機
絶縁膜としては、液状のシリカ系ガラスを回転塗布法に
より塗布しベークするととにより、ガラス被膜を形成す
る方法あるいはプラズマ放電電界中でシリコンと窒素を
反応させて得られる8 iN(窒化シリコン)をデポジ
ットさせる方法を用いて同様圧リンの影響を防止し耐湿
性を向上することができる。
For example, an inorganic insulating film that does not contain phosphorus to be formed on the soil of the PSG layer can be formed by coating liquid silica-based glass using a spin coating method and baking it to form a glass film, or by coating silicon in a plasma discharge electric field. By using a method of depositing 8 iN (silicon nitride) obtained by reacting nitrogen, the influence of pressure phosphorus can be similarly prevented and the moisture resistance can be improved.

〔効 果〕〔effect〕

本発明によれば表面酸化膜上のリン酸化物を含むガラス
層を覆うよ5にリンのドープされない無機絶縁膜を形成
した半導体装雪圧おけるアルミエラム配線の耐湿試験を
行なった結果、耐湿性がシリコン入りアルミニウム等の
ごとき耐蝕性電極材料とl’&W同一レベルにまで改善
されることが認められた。
According to the present invention, as a result of conducting a moisture resistance test of an aluminum Elam wiring in a semiconductor snowboard in which an inorganic insulating film not doped with phosphorus was formed to cover a glass layer containing phosphorus oxide on a surface oxide film, the moisture resistance was confirmed. It was found that the l'&w was improved to the same level as corrosion-resistant electrode materials such as silicon-containing aluminum.

ポリイミド系樹脂を用いた半導体装置℃は、特IC2層
配線構造の場合、2層目の配線にはシリコン入りアルミ
ニウムを用いることにより、耐食性を確保できるが、一
層目の配線は素子!性の影響(たとえばシロットバリア
ダイオード付きトランジスタの■、又はアルミニウム配
線と素子コンタクト部の「目あき」によるシリコンエッ
チによる特性の影響)を受け易く、シリコン入りアルミ
化は困難である。そのような問題も本発明によれば一層
目の無機絶縁膜を形成すること忙より簡易な方法で解決
できるとと忙なった。
Semiconductor devices using polyimide resin have a special IC two-layer wiring structure, and corrosion resistance can be ensured by using silicon-containing aluminum for the second layer wiring, but the first layer wiring can be used for elements! It is difficult to use silicon-containing aluminum because it is easily affected by characteristics (for example, characteristics caused by silicon etching due to "opening" of a transistor with a Shirotto barrier diode or "opening" between the aluminum wiring and the element contact part). According to the present invention, such problems can be solved by a simpler method than the process of forming the first inorganic insulating film.

〔利用分野〕[Application field]

本発明はポリイミド系樹脂を層間膜、保護膜として用い
たアルミニウム2層配線構造又はアルミニウム1層配線
構造を有する半導体装置の全て忙適用することができる
The present invention can be applied to all semiconductor devices having a two-layer aluminum wiring structure or a single-layer aluminum wiring structure using a polyimide resin as an interlayer film or a protective film.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は2層配線構造を有する半導体装置の一例を示す
一部縦断面図である。 第2図は本発明の一実施例を示すものであって、2層配
線構造を有する半導体装置の一部縦断面図である。 第3図は本発明の他の一実施例を示すものであって、一
層配線構造のnpn )9ンジスタを有する半導体装置
の製造プロセスの工程断面図である。 第4図は同じくエミッタ拡散を示す工程断面図、第5図
は同じくノンド−プ絶縁膜形成を示す断面図、 第6図は同じく電極を形成した状態を示す断面図、 第7図は同じくパッジベージロン膜を塗布した状態を示
す断面図である。 1・・・シリコン半導体基体、2・・・表面酸化膜、3
・・・第1層アルミニウム配si(電極)、4・・・ポ
リイミド樹脂からなる層間膜、5・・・第2層アルミニ
ウム配線、6・・・ポリイミド樹脂からなる保腹膜、7
・・・リン酸化物を含むガラス、8・・・CVD*Si
O。 膜、9・・・p−型シリコン基板、10・・・n+型埋
込層、11・・・n−型シリコン層(エピタキシャル層
)、12・・・表面酸化膜、13・・・p型アイソレー
ジ目ン部、14・・・ベースpm!領域、i5・・・コ
レクタコンタクトn+型領域、16・・・P2O層、1
7・・・エミッタn+型領域、18・・ツンドーブ5i
Oz膜、19・・アルミニウム配線、20・・・ポリイ
ミド膜、。 第 1 図 第 2 図 第 5 図 第 6 図 第 7 図
FIG. 1 is a partial longitudinal sectional view showing an example of a semiconductor device having a two-layer wiring structure. FIG. 2 shows an embodiment of the present invention, and is a partial vertical sectional view of a semiconductor device having a two-layer wiring structure. FIG. 3 shows another embodiment of the present invention, and is a cross-sectional view of a manufacturing process of a semiconductor device having a single-layer wiring structure (NPN)9 transistor. Fig. 4 is a process cross-sectional view showing emitter diffusion, Fig. 5 is a cross-sectional view showing non-doped insulating film formation, Fig. 6 is a cross-sectional view showing electrode formation, and Fig. 7 is a process cross-sectional view showing emitter diffusion. FIG. 3 is a cross-sectional view showing a state in which a film is applied. DESCRIPTION OF SYMBOLS 1... Silicon semiconductor base, 2... Surface oxide film, 3
... First layer aluminum wiring (electrode), 4... Interlayer membrane made of polyimide resin, 5... Second layer aluminum wiring, 6... Peritoneal membrane made of polyimide resin, 7
...Glass containing phosphorous oxide, 8...CVD*Si
O. Film, 9...p-type silicon substrate, 10...n+ type buried layer, 11...n-type silicon layer (epitaxial layer), 12...surface oxide film, 13...p type Isolation eye section, 14...Base pm! Region, i5...Collector contact n+ type region, 16...P2O layer, 1
7...Emitter n+ type region, 18...Tundob 5i
Oz film, 19...aluminum wiring, 20...polyimide film. Figure 1 Figure 2 Figure 5 Figure 6 Figure 7

Claims (1)

【特許請求の範囲】 1、半導体基体の一生面に複数の半導体素子が形成され
、上記半導体素子は表面にリン酸化物ガラス層を含む無
機絶縁膜で覆われ、上記無機絶縁膜上Vc1層又は複数
層のアルミニウムを主成分とする配線を有し、上記配線
上、又は及び配線間は有機の絶縁膜で覆われてなる半導
体装置であって、上記表面のリン酸化物ガラス層を含む
無機絶縁膜の上圧リンを含まない無機絶縁膜を介して、
上記配線のうちの第1層(下層)の配線を具備している
ことを特徴とする半導体装置。 2 上記有機の絶縁膜はポリイミド系樹脂からなる特許
請求の範囲第1項に記載の半導体装置。
[Claims] 1. A plurality of semiconductor elements are formed on the entire surface of a semiconductor substrate, the semiconductor element is covered with an inorganic insulating film containing a phosphorous oxide glass layer on the surface, and a Vc1 layer or a Vc1 layer is formed on the inorganic insulating film. A semiconductor device having multiple layers of wiring mainly composed of aluminum and covered with an organic insulating film on the wiring or between the wirings, the inorganic insulation including a phosphorous oxide glass layer on the surface. Through the upper pressure of the film, an inorganic insulating film that does not contain phosphorus,
A semiconductor device comprising a first layer (lower layer) of the wirings described above. 2. The semiconductor device according to claim 1, wherein the organic insulating film is made of polyimide resin.
JP59078566A 1984-04-20 1984-04-20 Semiconductor device Pending JPS60224229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59078566A JPS60224229A (en) 1984-04-20 1984-04-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59078566A JPS60224229A (en) 1984-04-20 1984-04-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60224229A true JPS60224229A (en) 1985-11-08

Family

ID=13665442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59078566A Pending JPS60224229A (en) 1984-04-20 1984-04-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60224229A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61288430A (en) * 1985-06-17 1986-12-18 New Japan Radio Co Ltd Semiconductor device
JPS62205630A (en) * 1986-03-06 1987-09-10 Seiko Epson Corp Semiconductor device
JPS637650A (en) * 1986-06-27 1988-01-13 Nippon Telegr & Teleph Corp <Ntt> Substrate wiring structure of semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61288430A (en) * 1985-06-17 1986-12-18 New Japan Radio Co Ltd Semiconductor device
JPS62205630A (en) * 1986-03-06 1987-09-10 Seiko Epson Corp Semiconductor device
JPS637650A (en) * 1986-06-27 1988-01-13 Nippon Telegr & Teleph Corp <Ntt> Substrate wiring structure of semiconductor integrated circuit

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