JPS637650A - Substrate wiring structure of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress interconnection delay and to decrease the amount of cross talk at the same time, by providing a first insulating layer, which is formed on a semiconductor substrate, and providing a second insulating layer, which has a smaller dielectric constant than the dielectric constant of the first insulating layer. CONSTITUTION:The outer surfaces of each interconnection 6 on a semiconductor substrate 4 are formed with insulating layers 5 and 7 in this interconnection structure. The dielectric constant of the insulating layer 7 is made smaller than the dielectric constant of the insulating layer 5. As the interconnection 6, an Al interconnection is used. As the insulating layer 5, an SiO2 layer, which has been actually used, is applied. As the insulating layer 7, a macromolecular material having a low dielectric constant such as, c.g., polytetrafluoroethylene (-[CF2CF2]-) or polyethylene, is applied. The dielectric constant of the SiO2 layer as the insulating layer 5 is 3.9. The dielectric constants of the polytetrafluoroethylene and the polyethylene as the insulating layer 7 are about 2.1 and 2.2, respectively. Therefore, even if the thickness of the insulating layer 5 beneath the interconnection is equal to the size between the interconnections or even if the size between the interconnections is smaller, the capacitance between the interconnections can be made smaller than the capacitance between the interconnections and the ground.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a substrate wiring structure of a semiconductor integrated circuit, and in particular to a transmission wiring that reduces delay and crosstalk in a high-density and high-speed semiconductor integrated circuit. be.

[Conventional technology]

In semiconductor integrated circuits, there has been remarkable progress in increasing density and speed. Recently, problems related to wiring, rather than C1 devices, have been attracting more attention as problems that limit the performance of LSIs. There are two main problems. The first point concerns a delay time determined by the product of wiring resistance and wiring capacitance. For example, A.K.
Shiina (A, ni, 5inha '5peed Llmi
tationa due to Int@rconn@
ctTim@Con5tants ln VLSI I
integrated C1rcuits, ”IEE
EvoL, EDL-31, NO, 4Apr, 198
2. pp 90-92. ) et al. determined the electrical characteristics of interconnects by numerical calculation using the two-dimensional Laplace-cut equation, and reported that in submicron LSIs, the delay time due to interconnects is greater than the device speed.

Also, K. C. Saraswato (K, C, Saras)
wat” gffect of Seatingof
Interconnection on the T
ime Damy of 'VLSI C1rcuit
s, 'IIJEE vot, ED-29, No, 4. A
pr, 1982. pp645-650) etc. are 0.5
They also report that the performance of LSIs below the μm rule is determined by wiring technology. In order to reduce the delay time caused by wiring, research has been carried out on low-resistance wiring metal materials and low dielectric constant insulating films. however,
As for materials that satisfy the above conditions, materials exceeding At and 5ift K are still under development from the viewpoint of compatibility with LSI processes, that is, adhesion, processability, heat resistance, insulation, and reliability. It has not been. s10! A polyimide film is well known as an insulating film that can be used instead of a film, but the dielectric constant of the polyimide film is as high as 3 to 4 depending on its composition.

The second point is a problem regarding crosstalk. The reason why the @ story occurs is that in the wiring structure formed on the semiconductor substrate 3, as shown in an example of the conventional wiring structure in FIG. This phenomenon tends to occur when the film thickness a of layer 1 and the inter-wiring film thickness s become approximately the same. The reason for this is that the inter-wiring capacitance becomes equal to or larger than the ground capacitance of the wiring. - As is well known, the guideline for activity is given by the following formula.

CM / (Cs10M) Here, Cs is the capacitance to ground t, and cM is the capacitance between wirings.

From this equation, it can be seen that when C820M is used, a potential of 1 h of the potential of the guiding wire is induced in the guided wire. Reduce the amount of crosstalk -? As a means of reducing the thickness a of the insulating layer,
There is a way to increase Cs. However, this method is undesirable because it increases wiring delay. Another method is to make the film gc of the wiring 2 thinner. However, this method is not preferable because it increases wiring resistance and increases wiring delay. Furthermore, as another method for reducing the amount of crosstalk, the conventional arrangement shown in Fig. 6 is used. As in other examples of the Ia structure, there is one in which a ground plane 9 made of a metal material is provided on an insulating film on which wiring is stacked. The greatest feature of this method is that crosstalk between different wiring layers can be prevented when wiring is multilayered. However, this method also increases the wiring capacitance.

[Problem that the invention seeks to solve]

Conventional wiring structures have the disadvantage of not being able to suppress wiring delays and crosstalk, which increase as density increases. Therefore, countermeasures are needed to prevent wiring reliability from deteriorating as the density increases, to suppress wiring delays, and to reduce the amount of crosstalk at the same time.

[Means for solving problems]

The present invention solves the conventional problems, and while ensuring the reliability of the wiring equivalent to the conventional wiring structure, that is, the adhesion with the substrate,
The present invention provides a transmission wiring structure that reduces delay and crosstalk, which are major problems in high-density and high-speed semiconductor integrated circuits.In the wiring structure on a semiconductor substrate, a first insulating layer formed on the semiconductor substrate; It is characterized by comprising a wiring formed on a first insulating layer and a second insulating layer existing between the wirings and having a dielectric constant smaller than the dielectric constant of the first insulating layer. shall be.

[Effect]

Conventional interconnect structures have used insulating layers of a single dielectric constant. In contrast, the main feature of the present invention is that the insulating layer under the wiring and the insulating layer buried between the wirings have different dielectric constants, and the dielectric constant of the insulating layer under the wiring is different from that of the insulating layer buried between the wirings. By lowering the dielectric constant of the insulating layer between the wires, the capacitance between the wires is reduced, delay time is reduced, and the ratio of the capacitance between the wires to the ground capacitance is reduced.
This method differs greatly from conventional technology in that crosstalk is less likely to occur. In the present invention, the adhesiveness between the wiring layer and the substrate is
Since this is ensured by the insulating material of the insulating layer below the wiring layer, the requirements for adhesion between the insulating material buried between the wiring layers and the wiring layer are relaxed, making it possible to select a low dielectric constant material from a wide range of materials. becomes possible. Examples will be described below based on the drawings.

〔Example〕

A first embodiment of the wiring structure of the present invention is shown in FIG. 1st
The figure shows a wiring structure in which a wiring 6 on a semiconductor substrate 4 is surrounded by an insulating layer 5.7. The dielectric constant of the insulating layer 7 is smaller than that of the insulating layer 5.-1 In the present invention, an At wiring is used as the wiring 6, and an integrated StO1 layer is used as the insulating layer 5.

As the insulating layer 7, for example, polytetrafluoroethylene (
-(CFtCFt)-), a low dielectric constant polymer material such as silica or polyethylene is applied. 810 as insulating layer 5
The dielectric constant of the two layers is about 9, and the dielectric constants of polytetrafluoroethylene and polyethylene as the insulating layer 7 are about 2.1 and 22, respectively. Therefore, the insulating layer 5 under the wiring
Even if the film thickness of the wiring and the dimension between the wirings are equal, or even if the dimension between the wirings is smaller, the capacitance to the ground 120 of the wiring can also be made smaller than the capacitance between the wirings. In other words, this wiring structure has the same adhesion between the wiring layer and the substrate as the conventional wiring structure, and is a structure in which crosstalk is less likely to occur even when wiring is mounted at high density. In the structure shown in Fig. 1, if the present invention is applied when the insulating film thickness under the wiring, the distance between the wiring layers, and the distribution ball 7'' - thickness C are equal, the comparison will be made with the case where only r stow is used as the insulating layer. Then, the total capacity and crosstalk amount are 25 to 36 inches.
It should be reduced by about %.

Next, a second embodiment of the wiring structure of the present invention is shown in FIG. In the second embodiment, insulating layers 5, 7.8 are formed around the wiring layer as shown in FIG. It is a structure. The dielectric constant of the insulating layer 7 is smaller than that of the insulating layers 5 and 8. Compared to a conventional structure provided with a ground plane, this structure not only reduces the total wiring capacitance, but also reduces the ratio of inter-wiring capacitance to ground capacitance, and reduces crosstalk between wiring.

The manufacturing methods for some specific examples of the wiring structure of the present invention will be exemplified and described below. First, what is the arrangement of the first embodiment? Some specific examples with IA structures are shown in FIGS. 3(&) to (e). In FIG. 3(a), material for wiring 6 is deposited on an insulating layer 9j%5 formed on a semiconductor substrate 4. In FIG. In this example, as the insulating film 5, a 5ift film formed by the CVD method was formed to have a thickness of 0.5 μm.

Methods for depositing this insulating film include, in addition to the CvD method, a sputtering method, a plasma CvD method, a spin-on method, etc., and it goes without saying that the present invention can be achieved by employing any of these methods. The wiring material has a specific resistance of 2.9 x 10-60-
A is as small as a leapfrog and is compatible with LSI processes.
/,It was adopted. At is prepared by a sputtering method.
A thickness of 5 μm was deposited. In addition to the sputtering method, there are various methods for depositing the wiring material, such as vapor deposition, CVD, and plasma CVD, and it goes without saying that the present invention can be achieved using any of these methods. In FIG. 6(b), after the resist pattern is formed by a phosphorography process, the resist pattern is etched by dry etching.
The insulating layer 5 and the material of the wiring 6 are etched at the same time. In the present invention, a two-layer resist of 5NR (silicone negative type resist)/AZ resist was used as a resist to form a fine pattern. The film thickness of the resist is SNR 0.15 μm + AZ resist 1.011 m. The phosphorography was performed using the EB writing method, and after pattern formation, the SNR was developed, the AZ resist was etched using OS plasma, the At was dry etched with No. 002, and the CF resist was etched.
4 and H! Sin was etched by etching. Figure 3 (
In the embodiment b), the insulating layer 5 was completely removed by the thickness of the film, but the etching may be stopped midway through the process. In FIG. 3(e), an insulating layer 7 having a dielectric constant smaller than that of the insulating layer 5 is embedded. Methods for embedding the insulating layer include plasma polymerization, spin-on deposition, and vapor deposition. In this example, polytetrafluoroethylene (-[CF, CF,)-> was applied as an insulator by a spin-on method, and buried by baking.

Polytetrafluoroethylene ((CFtCFt)-)
has a dielectric constant of 2.1 (I MHz) and a heat resistance of 30
It has a heat resistance of about 0°C, which is higher than that of polyethylene (about 200°C), and is a material that better meets the purpose of the present invention.

Next, some specific examples having the wiring structure of the second embodiment of the present invention are shown in FIGS. 4(A) to 4(d).

FIG. 4(a) shows an insulating layer 5 deposited on a semiconductor substrate 4,
Next, the material for the wiring 6 and the insulating layer 8 are successively deposited. In this embodiment, a Sigh film with a thickness of α5 μm formed by CVD method was used as the insulating layer 5.8, and an At film with a thickness α5 μm formed by sputtering method was used as the wiring material. FIG. 4(b) shows that EB writing is performed on the same SNR/Az two-layer resist as in the first embodiment, and after the SNRN image is developed, the AZ resist is etched with two plasmas to form a pattern, and then CF4 and H1 The upper insulating layer 8 made of Sin is etched in an atmosphere, then the wiring layer 6 made of At is etched in CCt, and then the lower insulating layer 5 made of 5iot is etched in a CF4 and H1 atmosphere. , after which the two-layer resist was removed. Figure 4 (C) is
The insulating layer 7 is buried between the lines in the same manner as in the first embodiment.

FIG. 4(d) shows a structure in which the surface is made flat by nip-packing using Ar sputtering. Fourth
In FIG. 6, a ground brain 9 made of a metal material is deposited. In this example, At is deposited to a thickness of 0.2 μm by sputtering.

〔Effect of the invention〕

When the wiring structure of the present invention is applied when the thickness of the wiring layer, the distance between the wirings, and the distance between the wiring and the substrate are all equal, the insulating layer 7 is made of polytetrafluoroethylene with a dielectric constant of Z1,
The advantage of using 5iot with a dielectric constant of 6.9 as the insulating layer 5 is to ensure the same adhesion to the substrate as in the conventional structure, while reducing total wiring capacitance and crosstalk compared to the conventional structure in which all the insulating layers are SSOx. Both amounts can be reduced by about 30%.

Further, in a structure in which a ground plane exists to prevent crosstalk between upper and lower wiring layers when wiring is multilayered in the wiring structure of one embodiment of the present invention, the insulating layer 7 is made of polyamide with a dielectric constant of 2.1. Insulating layer 5 of tetrafluoroethylene
．． By using Sin as 8, the relative permittivity of the insulating layer 7 is reduced to approximately 1/2 of that of the insulating layers 5 and 8, which reduces the wiring capacitance increased due to the provision of the AL ground plane in the upper layer. At the same time, the ratio of the inter-wiring capacitance to the ground capacitance can be further reduced, thereby realizing a reduction in the amount of crosstalk in the - layer.

As described above, the present invention solves the problems of delay and crosstalk in wiring, which affect the performance of VLSIs based on the submicron rule.

[Brief explanation of the drawing]

FIG. 1 shows a first embodiment of the wiring structure of the present invention, FIG. 2 shows a second embodiment of the wiring structure of the present invention, and FIGS. 3(a) to (e)
) is a specific example having the wiring structure of the first embodiment of the present invention, FIG. 4 (&) to (@) are specific examples having the wiring structure of the second embodiment of the present invention, FIG. is an example of a conventional wiring structure, and FIG. 6 is another example of a conventional wiring structure. 1... Insulating layer 2... Wiring 3... Semiconductor substrate 4... Semiconductor substrate 5... Insulating layer (dielectric for soldiers) 6... Wiring 7... Insulating layer (dielectric work gloves) ) 8... Insulating layer (dielectric critical) 9... Ground brain

Claims (2)

[Claims] (1) In a wiring structure on a semiconductor substrate forming a semiconductor integrated circuit, a first insulating layer formed on the semiconductor substrate;
and a second insulating layer having a relative permittivity smaller than the relative permittivity of the first insulating layer, which is present at least between the interconnects. substrate wiring structure of semiconductor integrated circuits. (2) A substrate for a semiconductor integrated circuit according to claim 1, wherein the first insulating layer is made of a silicon oxide film, and the second insulating layer is made of polytetrafluoroethylene or polyethylene. Wiring structure.