GB2208119A - Method and structure for achieving low contact resistance to aluminium and its alloys - Google Patents

Description

11 2r) e- U 8 '119 METHOD AND STRUCTURE FOR ACHIEVING LOW CONTACT

RESISTANCE TO ALUMINUM AND ITS ALLOYS The present invention is related to processes used in the fabrication of integrated circuit devices, particularly those devices exhibiting via openings less than one or two microns in diameter. More particularly, the present invention is related to a process and its resulting structure in which selectively deposited tungsten is caused to exhibit low contact resistance to aluminum. Accordingly, the present invention provides a mechanism for achieving low resistance contact between metallization layers in inte- grated circuit devices, particularly very large scale integrated circuit devices.

As the dimensions of circuit features employed in integrated circuit devices have shrunk to one micron and below, the problem of putting metal in the openings in dielectric materials so as to make electrical contact between conductors lying in different layers has become more difficult. It is desirable to have the dimensions of these openings as small as the feature size in order to make the density of devices on the chip as high as possible. On the other hand, the thickness of the dielectric layer that insulates one layer of conductor from the other is not generally decreased in proportion to the shrinkage in the lateral dimension due to other considerations such as interlayer capacitance. The result of this situation is the presence of via openings with depth to diameter ratios that have increased to values of one or more. It is difficult to effectively fill such high aspect ratio openings with conductive plug material. Even wide angle physical deposition processes, such as sputtering, have difficulty filling these openings with sufficient metal coverage on the walls of the openings to provide desirably reliable circuits. Chemical vapor deposition, especially selective vapor deposition that initiates growth on an underlying conductor at the bottom of an opening without growth on a dielectric surface is, however, one means to solve this problem. A thick, selective tungsten process has been employed to fill vias in which a first metallization layer of molybdenum is employed. These processes have been shown to exhibit low contact resistance because of the use of molybdenum. Such processes are described, for example, in "Proceedings of the Symposium on Multilevel Metallization, Interconnection and Contact Technologies" by R.W. Stoll and R.H. Wilson, Proceedings Vol. 87-4, The Electrochemical SocieLy, Pennington, NJ, 1987, page 232 and IEEE Electron Devices Letters, EDL-8, 55 (1987) by D.M. Brown et al. In such processes, a second layer of metal such as aluminum is employed and in the future, it will be desirable to add even another layer of metal which would also require via openings to aluminum patterns. Furthermore, most integrated circuit manufacturing processes use aluminum or its alloys as a first level of metal and, consequently, have vias to aluminum for two level metal processes. It is therefore seen that both at present and in the future, there is a definite desire for the formation of reliable low resistance contacts to aluminum and its alloys through via openings in dielectric layers.

Making low resistance contacts to aluminum with a second level of aluminum is a problem that usually requires a sputter etch step to remove aluminum oxide from the surface before depositing a second level of aluminum in a via. Previously reported literature (T. Moriya et al., IEEE !Q 1 Technical Digest, IEDM (IEEE, New York, 1983) page $50)) states that when selective tungsten is deposited on aluminum, that a high contact resistance results. This high contact resistance.has been confirmed by other workers in this field. It would be desirable to achieve low contact resistance between selective tungsten and aluminum so that selective tungsten process could be used to fill vias to aluminum conductive patterns, especially in integrated circuit applications.

In accordance with a preferred embodiment of the present invention, a process for making low resistance contact to aluminum through via openings in a dielectric layer overlying the aluminum (especially on an integrated circuit wafer) comprises the process step of selectively depositing tungsten in the via opening at a wafer temperature greater than about 350'C. However, the temperature employed is not so high as to damage the aluminum. In particular, the present invention indicates that there is a significant change in contact resistance occurring at a critical temperature between approximately 275'C and 3500C. Moreover, for the purposes of avoiding hillock formation in aluminum structures, the present invention is preferably practiced at a temperature less than approximately 450C.

The process of the present invention results in a structure with unique properties. In particular, the structure that results includes a tungsten plug in the via opening exhibiting a specific contact resistance, to the aluminum at the bottom of the opening, of less than approximately 2 x 10ohm-cm2. The process and the resulting structure are particularly applicable to the construction of multilayer conductive patterns in VLSI circuit applications.

1 Thus by appropriately performing the invention it becomes possible:

to deposit tungsten in via openings so as to form low resistance contact with aluminum and/or its alloys at the bottom of a via opening; to fabricate very large scale integrated circuit devices in which via openings having a high aspect ratio are employed; to provide a method for filling via openings having a high depth-to-diameter ratio; to provide means for making low resistance contact between conductive layers in an integrated circuit device; to promote the fabrication of multilevel integrated circuit devices, particularly those employing aluminum and its alloys; and to selectively deposit tungsten in via openings less than about 1 or 2 microns in diameter in a manner so as to achieve low specific contact resistance to aluminum and/or its alloys at the bottom of via openings.

The invention, both as to organization and method of practice, together with various objects and advantages thereof, may be better understood by reference to the following description taken in connection with the accompanying drawing in which:

1 The figure illustrates a multilayer structure such as might be fabricated in accordance with the process of the present invention.

Four inch diameter wafers were oxidized and then covered with a sputtered layer of aluminum or aluminum with 2% silicon to a thickness of approximately 5,000 angstroms. The film was patterned with a test structure used for the first level of metal in a two level metal CMOS process. A silicon dioxide layer, either 0.4 or 0.8 micrometers thick, was then deposited at a temperature of approximately 3800C by plasma enhanced chemical vapor deposition (PECVD). Openings to the underlying metal were formed using projection photolithography and reactive ion etching. The resist used was removedin an unheated oxygen plasma apparatus and the wafers were cleaned in hot PRS1000, a product manufactured by the J.T. Baker Chemical Company of Pennsylvania. Immediately prior to loading the wafers in a tungsten deposition system, some of the wafers were immersed for 30 seconds in a 1% solution of hydrofluoric acid which removed approximately a few hundred angstroms of aluminum. The etch was followed by a rinse in deionized water. These wafers are referred to herein as etched wafers. Other wafers were given no further treatment and are referred to herein as unetched wafers. After this preparation, the wafers were loaded into one of four systems capable of depositing selective tungsten on metals using the hydrogen reduction of tungsten hexafluoride. One of the systems was the cold wall experimental system designated herein as R. Two of the systems were modified cold wall reactors of the type sold commercially for deposition of tungsten silicide or blanket tungsten and designated herein as GI and G2. The fourth - -6- reactor system was a hot wall tube furnace of conventional design and designated herein as T. In all of the reactor systems, the wafers were heated to the desired temperature in a hydrogen atmosphere at pressures in the range of from about 0.4 to 1.1 Torr. Tungsten hexafluoride was introduced for a period of time chosen to approximately fill the openings in the oxide to the underlying metal except for the tube furnace in which only 0.1 micrometers of tungsten was deposited. For the tube furnace, the wafer temperature was assumed to be at the temperature of a thermocouple inserted into a sheath inside the furnace. For the other systems, the wafers were placed on a heated surface and consequently, were heated only from one side so that, at these reduced pressures, the wafer temperature was considerably less than the temperature of the heater surface. In these systems, the wafer temperature was inferred from the tungsten growth rate using the kinetic data of Broadbent and Ramiller (Journal of the Electrochemical Societ, Vol 131, page 1427 (1984)). Following the tungsten deposition, the wafers were cleaned with PRSIOOO and an aluminum film 0.8 micrometers in thickness was sputtered on the wafer and subsequently patterned to complete a circuit suitable for electrical testing. Finally, the wafers were annealed for one hour at a temperature of 4000C in hydrogen.

The contact resistance of the metal-one/tungsten plug/metal-two structure was measured with 1.8 micrometer diameter vias using a Kelvin structure and 4 point measure ment. Table I shows the mean values of more than 35 measurements on each wafer for the processes indicated. The results indicate the criticality of the temperature and/or deposition rate employed herein as is seen in Table I.' J 1 1 11 TABLE 1

Growth Mean Contact Surface System Temperature Rate (A1cm) Resistance Metal One Preparation T 275 22 25.7 AIll% Si unetched T 275 22 149.0 AI/1% Si etched G1 308 42 4.o AIll% Si etched G1 308 42 4.4 AIll% Si etched G1 354 115 1.3 AIll% Si etched G1 354 115 69.7 AIll% si etched G1 382 200 0.5 AIll% Si etched G1 382 200 0.2 AIll% Si etched G1 393 300 0.2 AI etched G1 393 300 0.2 AIll% Si etched G1 417 375 0.1 AI/1% Si etched G1 417 375 0.1 AIll% Si etched G2 440 550 0.1 AI etched 1 G2 440 550 0.4 AI/170 Si etched G1 460 750 0.1 AI/170 Si etched G1 460 750 0.1 AI/17, Si etched R 472 1500 0.2 AI etched R 472 1500 0.4 AIll% S; etched R 500 2200 0.3 AIll% Si unetched R 500 2200 0.1 AIll% Si etched R 528 3200 0.1 AI etched R 528 3200 0.3 AIll% S1 etched 4 It is clear that as the temperature and deposition rate are increased, the observed resistance decreases until the temperature is about 3500C or the deposition rate is about 120 angstroms per minute. Above these values, the resistance is about constant. It is also indicated that the surface preparation of the underlying surface is not a controlling factor in producing the desired low contact resistance. Additionally, there is no apparent difference in results between the use of aluminum and aluminum alloyed with 1% silicon.

It is also noted that significant hillock formation in the aluminum was observed for the higher temperature processes, but not for those processes carried out at temperatures below 4500C. This is consistent with what is to be expected for these temperatures. Other alloying elements with aluminum or layered structures with aluminum allow for the use of higher temperatures and the accompanying higher deposition rates without excessive hillock formation. In any event, it is desired that the processes carried out herein are not carried out at temperatures so high as to damage aluminum structures. In particular, the process herein is carried out at a temperature of less than approximately 6000C. It is certainly even more preferable to carry out the process herein at a temperature less than approximately 4500C to avoid hillock formation.

A structure produced in accordance with the process of the present invention is shown in the figure referred to above. In particular, it is seen that lower level metallization pattern 12 comprising aluminum or an aluminum alloy is disposed on a layer of dielectric material 15, disposed on substrate 10 which typically comprises a semiconductor material, such as silicon. Disposed over metallization pattern 12 is an additional layer of -1 i dielectric material 11, typically comprising silicon oxide. In accordance with the process described above, tungsten plug 14 is deposited in an aperture in dielectric 11 so as to form a low resistance contact with metallization 12. An upper level metallization pattern 13 may also then be deposited and patterned so as to be in contact with tungsten plug 14. The upper level metallization layer 13 may comprise aluminum or other conductive materials such as are conventionally employed in VLSI circuit manufacture. in particular, metallization layer 13 may comprise molybdenum.

Accordingly, it is seen from above that a process for making low resistance contact to aluminum and its alloys is effective and is easily carried out in conventionally employed VLSI processing systems. It is further seen that the process described herein extends the usefulness of selectively deposited tungsten and renders the fabrication of micron and submicron circuits significantly easier. It is also seen that the process herein contributes significantly to the fabrication of multilayered conductive pat- terning in VLSI circuits using aluminum and its alloys. This is a particularly desirable feature of the present invention since aluminum is an otherwise desirable metallization material. Lastly, it is seen that the process and the resulting structure of the present invention fulfills all of the objectives indicated above.

While the invention has been described in detail herein in accord with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art.

A

Claims (18)

CLAIMS:

1. A process for making low resistance contact to aluminum or aluminum alloys through a via opening in a dielectric layer overlying said aluminum material on a wafer, said process comprising the step of:

depositing tungsten in said via opening and in contact with said aluminum material, said deposition occurring at a temperature greater than approximately 3500C but not at a temperature so high as to damage said aluminum material.

2. The process of claim I in which said deposition temperature is less than approximately 6000C.

3. The method of claim I in which said deposition temperature is not so high as to cause hillock formation.

4. The process of claim I in which said deposi- tion temperature is less than approximately 4500C.

S. The process of claim I further including the process step of pretreating said wafer in an acid bath to selectively etch said aluminum material through said via opening prior to said deposition of tungsten.

6. The method of claim 5 in which said acid is hydrofluoric acid.

7. The process of claim I in which said selective deposition is carried out in a hot wall reactor.

S. The process of claim I in which said selective deposition is carried out in a cold wall reactor.

9. The process of claim I in which said aluminum contains silicon.

20. The process of claim 9 in which said silicon is present in an amount of approximately 1% by weight.

11. The method of claim I in which said tungsten deposition occurs at a rate greater than about 120 angstroms per minute.

12. The method of claim I in which said deposition is selective.

13. The low resistance contact made in accordance with the process of claim 1.

14. A multilevel structure for use in integrated circuits, said structure comprising:

a layer including conductive patterns of aluminum material; an insulative layer overlying said conductive patterns and having at least one aperture therein disposed so as to expose at least some of said aluminum material; a tungsten plug disposed in said opening, said plug exhibiting a specific contact resistance to said aluminum material of less than approximately 2 x 20- 8 ohm-cm'.

15. The structure of claim 14 in which said aluminum material includes silicon.

16. The structure of claim 15 in which said silicon is present in the amount of 2% by weight. 20

17. The multilevel structure of claim 14 further including an additional layer of conductive patterning disposed so as to be in electrical contact with an upper surface of said tungsten plug.

18. A process for making low resistance contact to aluminum or aluminum alloy through a via opening in a dielectric layer by deposition of tungsten at a temperature greater than approximately 350 0 C substantially as hereinbefore described.

Publis'llied 1986 at The Paten Of:iCe. State Hcuse. 66 H;9,-, HO'bernLondOn WC1R 4TP- FLir.-- er cop,.em may =n T..e PaLen.

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