GB1596907A

GB1596907A - Manufacture of semiconductor devices

Info

Publication number: GB1596907A
Application number: GB2286378A
Authority: GB
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1978-05-25
Filing date: 1978-05-25
Publication date: 1981-09-03

Description

(54) 1'HE MANUFACTURE OF SEMICONDUCTOR DEVICES (71) We, FUJITSU LIMITED, a Japanese Corporation, of 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to methods of manufacturing semiconductor devices.

For the purposes of construction of systems such as an electronic computer or an information processing unit, which are of small dimensions and which have a high degree of reliability, highly integrated circuits are required. Furthermore, as the capacity of such systems is increased, multi-wiring-layer structures are required to be used in the formation of the integrated circuits. Because conventional wiring pattern for connecting circuit components in a highly integrated circuit can become very complex, a multi-wiring-layer structure is therefore used. In a multi-wiring-layer structure, a plurality of wiring layers are formed in a multilayer structure, with an insulating layer sandwiched in between each pair of adjacent wiring layers.

Wiring connections formed between adjacent wiring layers are provided via contact holes which are provided in the insulating layer sandwiched between the wiring layers. Generally, aluminium Al is used to provide the wiring layers, and silicon dioxide SlO2 or phosphorous silicate glass (PSG) is used to provide the insulating layers located between adjacent wiring layers.

A multi-layer wiring structure has been formed by first depositing aluminium Al which is used for the lower wiring layer, patterning the aluminium layer, forming a layer for insulating an upper wiring layer and the lower wiring layer, forming a contact hole in the insulating layer, depositing the aluminium M which is used for the upper wiring layer and patterning this aluminium Al layer. In a multilayer structure formed by such a method, electrically defective connections between the upper and the lower aluminium Al layers can occur in the contact holes. The reason for such defective connections is believed to be that an alumina M2 03 layer which is formed on the surface of the lower aluminium Al layer in the contact hole when oxidation occurs on the surface of the lower aluminium Al layer, or that a residium formed in the contact hole, acts as an insulating material in the contact hole.

Especially when small contact holes are formed in a highly integrated circuit it has been found that defective connections between the upper and lower aluminium A1 layers can occur frequently and can prevent successful achievement of a high degree of integration for the circuit.

According to the present invention there is provided a method of manufacturing a semiconductor device, wherein a contact hole is provided in an insulating layer formed between a first wiring layer, having aluminium as a main constituent thereof, and a second wiring layer, having aluminium as a main constituent thereof, the first wiring layer being provided beneath the second wiring layer, and wherein there is provided, at least in the said contact hole, a layer of a metal reactive with aluminium, and of a thickness in the range from lO0A to lOO0A, and heating to a temperature above 300"C is effected to cause the said metal to react with the aluminium of the first wiring layer.

The use of a method embodying the present invention can provide for the successful manufacture of a device having a multi-layer wiring structure without the need for complex manufacturing processes and with a low incidence of defective connections between upper and lower wiring layers.

In embodiments of the present invention the method employed may be briefly stated as follows; a metal which is reactive with aluminium Al is deposited on a lower metal wiring layer composed mainly of aluminium Al in a contact hole and an upper metal wiring layer is formed on the contact hole and heat treatment is applied to the substrate. Hereinafter, more details of method embodying the present invention will be explained.

A layer of a metal which is reactive with aluminium Al is formed in a contact hole between upper and lower wiring layers which are composed mainly of aluminium A1, and this metal layer is reacted with the lower wiring layer by means of a heat treatment, thereby breaking any very thin insulating film which has been formed on the surface of the lower wiring layer in the contact hole, thereby to remove possible causes of defective connections in the contact hole. Metals which are employed for reaction with aluminium Al are preferably platinum Pt, gold Au, titanium Ti, chromium Cr, molybdenum Mo, and tungsten W. In embodiments of this invention a layer of such a metal of a thickness between 100A to 1000A is formed in a contact hole. For the wiring layers, aluminium Al layers, alloy layers composed of aluminium Al and silicon Si, or alloy layers composed of aluminium Al and copper Cu can be used. Embodiments of the present invention can also be used in cases in which wiring layers are composed of a thin polycrystal silicon layer and an aluminium Al layer formed on the thin polycrystal silicon layer. It will therefore be understood that embodiments of the present invention can be used when wiring layers include aluminium Al as a main component. The thickness of such wiring layers including aluminium is preferably in the range of from 5000A to 15000A. In addition, heat treatment effected in accordance with a method embodying the present invention is carried out at above 300 C. However, the temperature will depend upon the type of metal used to react with the wiring layer material. As heat treatments at such temperatures are generally carried out when a chemical vapour deposition process is used to form an insulating film, or when other processes involving heat treatments are used, it is not necessary to provide a heat treatment step specifically for causing reaction between wiring layer material and the reactive metal.

Reference will now be made, by way of example, to the accompanying drawings, in which :- Figure 1 is a schematic plan view illustrating part of an integrated circuit having a multiwiring-layer structure which may be manufactured by a method embodying the present invention; Figure 2 shows four schematic cross-sectional views illustrating respective stages of manufacture in accordance with a method of manufacturing a semiconductor device embodying the present invention; Figure 3 shows four schematic cross-sectional views illustrating respective stages of manufacture in accordance with another method of manufacturing a semiconductor device embodying the present invention; and Figure 4 shows a schematic cross-sectional view illustrating a modification of the method of manufacturing a semiconductor device illustrated in Figure 3.

Figure 1 shows a multi-wiring-layer structure for an integrated circuit. A first layer 1 (a lower layer); one aluminium wiring layer, and a second layer 2 (an upper layer), another aluminium wiring layer, are connected via contact holes 3 which are formed in an insulation film which is formed between the first and second layers 1 and 2. In an integrated circuit having a high density of circuit elements, the width of condutors of the first aluminium wiring layer 1 is about 3tj, the width of conductors of the second aluminium wiring layer 2 is about 4 to 6,u, and the sectional area (the area as seen in a plan view as in Figure 1) of the contact hole is about 3 ,u x 3 ij. The minimum distance between connections (contact hole locations), on the first aluminium wiring layer, is about 2 to 3 ,u.

In Figure 2, cross-sectional views (a), (b), (c) and (d) illustrate manufacturing stages in a method embodying the present invention.

Figure 2(a) shows a cross-sectional view of a substrate on which a first layer of an aluminium wiring layer structure has been formed. In Figure 2(a), there are shown substrate 11 (for exxample, a P-type silicon substrate) with a diffusion layer 12 (for example, an n±type diffusion layer). First aluminium wiring layer 14 is formed on an insulating layer 13 which covers the surface of the substrate 11. The first aluminium wiring layer 1 4 is brought into contact with the diffusion layer 12 (i.e. the substrate) via a contact window which is formed in the insulating layer 13. The thickness of the aluminium wiring layer 14 is between 5000 and 1 0000A.

Next, a silicon dioxide SiO2 film or a phosphorous silicate glass film 15 for insulating one from the other the first wiring layer and a second aluminium wiring layer is formed on the substrate by using a chemical vapour deposition method. This insulating film may alternatively be a polyimide film or an aluminium oxide A1203 rilm. Next, a photo-resist layer 16 is formed on the insulating film 15, windows for forming contact holes are provided in the photo-resist layer 16 and the insulating layer 15 is etched by using the photo-resist layer 16 as a masking layer. Figure 2(b) shows the layer structure achieved after the photoetching process is finished. In the structure of Figure 2(b), the thickness of the insulation layer 15 is about 5000 to 1 s00oA. Thus, as shown in figure 2(b) the contact hole is formed. The manufacturing steps shown in Figures 2(a) and 2(b) are the same as is in previously-proposed process.

Next, as shown in Figure 2(c), a platinum layer 17 is formed on the photo-resist layer 16, and on the first aluminium wiring layer 14, by means of a sputtering method or a vacuum evaporation method. The thickness of the formed platinum layer 17 is in the range 100 to 1 000A. As shown in Figure 2(c), the platinum layer 17 is formed on the photo-resist layer 16 and on the portion of the first aluminium wiring layer 14 exposed in the contact hole. As the levels of the photo-resist and the first aluminium wiring layer are different in height on the substrate, that part of the platinum layer formed on the first aluminium wiring layer 14 in the contact hole is separate from that part of the platinum layer formed on the photo-resist layer 16, as shown in Figure 2(c).

When the photo-resist layer 16 is removed by a solvent, that portion of the platinum layer 17 on the photo-resist layer 16 is removed at the same time. Therefore, only that portion of the platinum layer 17 on the first aluminium wiring layer 14 is left in place. Next, as shown in Figure 2(d), the second aluminium wiring layer 18 is formed by a process of vacuum evaporation of aluminium, to a thickness of 5000 to lOOOOA and by patterning the aluminium layer. The second aluminium wiring layer 15 covers the contact hole and contacts with the portion of the platinum layer 17 therein. When heat treatment is carried out above 30000C with respect to the substrate shown in Figure 2(d), the first aluminium wiring layer 14 and the second aluminium wiring layer 18 react violently with the remaining portion of the platinum layer 17. If any very thin insulating film exists between two layers, this insulating film is broken down and very good contact can be obtained between the two layers 14 and 18. As the volume of the portion of the platinum layer 17 in the contact hole is very small as compared with the volumes of the first and second aluminium layers 14 and 18, the above-mentioned reaction does not give rise to any deleterious effect on the manufactured device. The above-mentioned heat treatment is not necessary as a distinct manufacturing step if succeeding processing includes heat treatment above 300"C. Such heat treatment may be provided in succeeding processing as a heat treatment for obtaining an ohmic contact between the first aluminium wiring layer 14 and the diffusion layer 12 (or the substrate 11), or a heat treatment in chemical vapour deposition for forming a protective insulating film. The method of manufacture embodying the present invention illustrated in Figure 2 is effective when a metal such as platinum Pt, which is very difficult to treat by an etching method, is used for the metal layer 17.

In Figure 3, (a), (b), (c) and (d) are respective cross-sectional views illustrating respective manufacturing stages in another method embodying the present invention. Figure 3(a) is a cross-sectional view of a substrate on which a first aluminium wiring layer has been formed.

There are shown in Figure 3(a), the substrate 21 (for example, a P-type silicon substrate), a diffusion layer 22 (for example, an n±type diffusion layer), a silicon dioxide (SlO2) film 23 covering the surface of the substrate 21, a phsophorous silicate glass flim 24 formed on the silicon dioxide (SiO2) film 23, and a first aluminium wiring layer 25 formed on the phosporous silicate glass film 24. The first aluminium wiring layer 25 is formed by a process of vacuum evaporation of aluminium and by patterning the aluminium layer. The thickness of the first aluminium wiring layer 25 is about 8000A.

Next, a phosphorous silicate glass (PSG) film 26, which is to lie between the first and a second wiring layers is deposited by means of a chemical vapour deposition method.

This chemical vapour deposition is carried out at a temperature Of 425 C. In this chemical vapour deposition, 6Q of monosilane (SiH4), 1 Q of phosphine (PHB ) and 2Q of oxygen (02) are sent per minute into a reaction furnace, using argon Ar gas as the carrier gas. The growth speed of the phosphorous silicate glass film on the silicon wafer arranged in the reaction funace is 800A/min. Next, a photo-resist layer is formed on the phosphorous silicate glass and the windows for forming the contact holes are formed in the photo-resist layer. Then, the phosphorous silicate glass to be used as the insulating film between first and the second wiring layers is selectively etched using this photo-resist layer as the etching mask. Two examples of liquids which can be used for etching the phosphorous silicate glass are:

Example 1 HF 65 cc content of NH4F 560 cc the liquid H2 0 390 cc or Example 2 HNO3 700 cc content of the liquid NH4HF4 10 g When the liquid of Example 1 is used, the rate of etching of the phosphorous silicate glass is 6000A/min at room temperature, and when the liquid of Example 2 is used, the rate of etching of the phosphorous silicate glass is 120008/mien at room temperature. After forming contact holes by etching, and exposing parts of the first aluminium wiring layer 25 in the contact holes, titanium Ti having a thickness of 100 to 500A is deposited using a vacuum evaporation method or a sputtering method.

Figure 3(b) shows this stage of manufacture, after the titanium Ti layer formation. In Figure 3(b) the phosphosphorous silicate glass film is labelled 26 and and the titanium Ti layer is labelled 27.

Next, as shown in Figure 3(c), aluminium Al is deposited in a layer of a thickness of about l.O,u and this aluminium Al layer, 28 is Figure 3(c), is patterned so that the second aluminium wiring layer is formed as shown at 28 in Figure 3(d). Next, the titanium layer 27 is selectively etched by using the second aluminium wiring layer 28 as the mask, and thereby the titanium layer 27 is removed except for the portion thereof under the second aluminium wiring layer 28. The etching liquid used for etching the titanium is a mixture of 1000 cc of HNO3 to 10 g of NIl4F which etches the titanium Ti layer at an etching rate of 2000/min at room temperature.

Further processing, in which heat treatment is applied to the substrate and in which the aluminium layers 25 and 28 are reacted with the titanium layer 27, is the same as the process illustrated in Figures 2(a) to 2(d).

Actually, as shown in Figure 4, it is prefer able to form polycrystal silicon layers 31 and 32 on the phosphorous silicate glass film 24 and the titanium layer 27 respectively, as parts of the first and second wiring layers respectively. That is to say, beneath the aluminium layer 25 and beneath aluminium layer 28 respective layers of polycrystal silicon are formed, so that the first and second wiring layers are composite layers each having a polycrystal silicon layer beneath an aluminium layer. The polycrystal silicon layer 31 is provided for preventing a short circuit of the PN junction in the substrate under the contact window from occurring between the substrate silicon and the first aluminium wiring layer.

Such a short-circuit could be caused by the formation of an alloy on a contact surface between the substrate and the first aluminium wiring layer. The polycrystal silicon layer 32 is provided for preventing the substrate silicon from penetrating under the first aluminium wiring layer via contact holes to the second aluminium wiring layer 28. For example, if the polycrystal silicon layer 32 is not provided and the contact point between the substrate and the first aluminium wiring layer is located near the contact hole connecting the wiring layers, the PN junction beneath the contact point could be short-circuited. Accordingly, each of the above-mentioned polycrystal silicon layers 31 and 32 should preferably have a thickness of from 100 to 2000A.

Hereinafter are given details of a number of examples of experiments which were carried out in connection with methods embodying the present invention.

EXAMPLE I Three thousand and seventy-nine contact holes having a size of 4 per x 4,u were formed on one chip by utilising a manufacturing process in accordance with the embodiment of the present invention illustrated with reference to Figure 2. That is, three thousand and seventynine connection points connecting a lower wiring layer and an upper wiring layer were provided for one chip. A conventional largescale integration circuit (LSI) often has thousands of contact holes per chip. Each wiring layer was formed with a pattern such that the 3079 contact points were connected in series.

After forming the upper wiring layer, the chip was subjected to heat treatment for 30 minutes at about 4500 C. The relationships between the different sample processes (designated by sample numbers), types of contact constructions at the contact holes and the nondefective factor (IN %) are shown in Table 1. Referring to Table 1, tests were carried out on 34 chips made in accordance with each sample process.

When an electric connection could be obtained on a chip as a result of all of the contact points being successfully connected in series, the chip was deemed to be a good chip, On the other hand, when a non-conductive contact was produced at at least one contact point on a chip, the chip was deemed to be a defective chip.

Referring to Table 1, Al I refers to the lower wiring layer and Al II refers to the upper wiring layer.

EXAMPLE 2 Two thousand eight hundred and fifty-nine contact holes having a size of 5,u x S p were formed on one chip by utilising a manufacturing process in accordance with the embodiment illustrated with reference to Figure 2. Tests were carried out on 24 chips made in accordance with each sample process, while the other conditions were maintained the same as those in Example 1. The results of the tests are shown in Table 2. When Table 2 is compared with Table 1, it will be understood that embodiments of the present invention in accordance with the method of Figure 2 were found to be more effective when the size of the contact holes was smaller.

EXAMPLE 3 Forty chips per sample process were formed in accordance with manufacturing methods in accordance with the embodiment described with reference to Figure 4, and thereafter tested. The results of the tests are shown in Table 3. In this example, the thickness of the polycrystal silicon layers formed beneath the aluminium Al layers was 200A in each sample, and heat treatment was carried out for 30 minutes at a temperature of 480"C after the upper aluminium Al wiring layer was formed.

If electric contacts were obtained at all contact points on a chip, the chip was deemed to be a good chip.

EXAMPLE 4 Contact holes having the size 14u x 14p were formed under the same conditions as those used for forming Samples 13 to 17 in Example 3. Next, the contact resistance of these contact holes was measured. The results of such measurements are shown in Table 4, below. The resistance values shown in Table 4 were measured by connecting ten contact points in series. It was observed from Examples 3 and 4 that the contact resistance decreased suddenly when the thickness of the titanium Ti layer became larger than lOOA.

EXAMPLE 5 The resistance values of contact points having various constructions were measured. Such measurements were carried out by connecting ten contact points in series. The results are shown in Table 5. Samples A, B, C of Table 5 were formed as described below.

Sample A: A Titanium Ti layer having a thickness of about 20-OA was formed over the entire surface of the lower aluminium Al layer, the contact hole was provided in an insulat ing film formed on the titanium Ti layer. A polycrystal silicon layer (thicknes of 200A) and an aluminium Al layer (thickness of 800A) were successively formed on the insulating film and in the contact hole to TABLE 1 Sample number Construction of the contact portion Nondefective factor 1 AlI-AlIl 0 2 Al I - Al II O 3 Al I - #Pt (thickness 250 )# - A1 II 72% 4 Al I - Pt (thickness 250A) - Al II 76% 5 Al I - Pt (thickness SO0A) - Al II 24% 6 Al I - Pt (thickness 500A) - Al II 24% TABLE 2 Sample number Construction of the contact portion Nondefective factor 7 All-Al II 6% 8 Al I - AI II 3% 9 Al I - Pt(250A) - Al II 70% 10 Al I - Pt(250 ) - Al II 88% 11 Al I - Pt(500 ) - Al II 42% 12 AlI-Pt(500A) -AlIl 27% TABLE 3 Sample Contact hole Thickness of Nondefective number size number titanium Ti film factor 13 5,ux5,u 2800 0 0 14 5 x 5 2800 50X 0 15 5 x 5 2800 100A 0 16 5 x 5 2800 150A 100% 17 5 x 5 2800 200A 100% 18 4 x 4 3080 0 0 19 4 x 4 3080 50A 0 20 4 x 4 3080 100A 0 21 4,ux4,u 3080 150A 100% 22 4 x 4 3080 200A 100% TABLE 4 Sample number Resistance value 13 0.36Q 14 0.68 Q 15 0.5211 16 0.3211 17 0.31 # form an upper wiring layer.

Sample B: A titanium layer having a thickness of 200A was formed on an entire surface of the lower aluminium wiring layer. A contact hole was provided in an insulating film formed on the titanium Ti layer. A titanium Ti layer (thickness of 200A), a polycrystal silicon layer (thickness of 200A) and an aluminum layer (thickness of 8000A) were formed successively on the insulating film and in the contact hole to form the upper wiring layer.

Sample C: Formed by means of a process in accord ance with the embodiment shown in Figure 4, the titanium layers and the poly crystal silicon layer were formed with a thickness of 200A.

In each sample the size of each contact hole was lOp x 10 . Fifty chips were provided in accordance with each sample. Referring to Table 5, it can be determined that the employ- ment of a titanium Ti layer formed before the formation of the insulating film and the contact hole on the surface of the lower wiring layer, has no special advantage.

TABLE 5 Sample Resistance value Mean Resistance number value A* 0.65 - 7.55 Q 2.1 # B* 0.63-7.5511 1.7 # C 0.33 - 0.39 # 0.36 Q EXAMPLE 6 A phosphorous silicate glass film having a thickness of 1 pm was formed on the lower aluminium Al wiring layer as an insulating film, and contact holes were formed in the phosphorous silicate glass film. A titanium layer having a thickness of 150A was deposited on the phosphorous silicate glass film. Next, the upper aluminium Al wiring layer having a thickness of 6000A was deposited and annealed for 30 minutes at a temperature of 320 C.

When chips were made in accordance with this example with the size of each contact hole at 10,u x 10 p and when ten contact points were connected in series, the resistance value thereof was found to be 0.55 Q to 0.65 11. Nondefective connections were provided when the size of each contact hole was reduced to 5 p x 5 fez and 2800 contact points using such contact holes were connected in series, and also when the size of each contact hole was reduced to 4 cur x 4 p and 3080 contact points using such contact holes were connected in series.

As is clear from the above-description, embodiments of the present invention can provide for the reliable and reproducible manufacture of contact holes and can afford a considerable improvement by the utilisation of processing involving the formation of a metal layer which is reactive with aluminium in a contact hole.

The above description has referred only to cases in which a multi-wiring-layer structure has comprised only two wiring layers. However, it should be noted that embodiments of the present invention can be employed in the provision of multi-wiring layer-structures comprising more than two wiring layers.

Thus, embodiments of the present invention provide methods of manufacturing a semiconductor device which has a multi-wiringlayer structure and has metal wiring layers composed of aluminium Al as a main component.

In embodiments of the present invention a metal which is reactive with aluminium is inserted into a contact hole located between a lower metal wiring layer and an upper metal wiring layer, the upper metal wiring layer is formed in such a way as to cover the contact hole and heat treatment is applied to the device substrate, and thereby the occurrence of electrically defective connections in contact holes can be reduced or entirely avoided.

WHAT WE CLAIM IS: 1. A method of manufacturing a semiconductor device, wherein a contact hole is provided in an insulating layer formed between a first wiring layer, having aluminium as a main constituent thereof, and a second wiring layer, having aluminium as a main constituent thereof, the first wiring layer being provided beneath the second wiring layer, and wherein there is provided, at least in the said contact hole, a layer of metal reactive with aluminium and of a thickness in the range from lO0A to 1 oOOA, and heating to a temperature above 300)C is effected to cause the said metal to react with the aluminium of the first wiring layer.

2. A method as claimed in Clairn 1, wherein the said metal reactive with aluminium comprises at least one element selected from the group constituted by platinum, gold, copper, titanium, chromium, molybdenum, and tung- sten.

3. A method as claimed in Claim 1 or 2, wherein the first and second wiring layers have thicknesses in the range from 5000A to 15000A.

4. A method as claimed in any preceding claim, wherein the first and second wiring layers are each constituted by an aluminium layer and a polycrystal silicon layer formed beneath the aluminium layer.

5. A method as claimed in Claim 4, wherein in each wiring layer the thickness of the polycrystal silicon layer is in the range from 100A to 2000A.

6. A method as claimed in any preceding claim, comprising th

Claims

**WARNING** start of CLMS field may overlap end of DESC **. aluminium Al wiring layer as an insulating film, and contact holes were formed in the phosphorous silicate glass film. A titanium layer having a thickness of 150A was deposited on the phosphorous silicate glass film. Next, the upper aluminium Al wiring layer having a thickness of 6000A was deposited and annealed for 30 minutes at a temperature of 320 C. When chips were made in accordance with this example with the size of each contact hole at 10,u x 10 p and when ten contact points were connected in series, the resistance value thereof was found to be 0.55 Q to 0.65 11. Nondefective connections were provided when the size of each contact hole was reduced to 5 p x 5 fez and 2800 contact points using such contact holes were connected in series, and also when the size of each contact hole was reduced to 4 cur x 4 p and 3080 contact points using such contact holes were connected in series. As is clear from the above-description, embodiments of the present invention can provide for the reliable and reproducible manufacture of contact holes and can afford a considerable improvement by the utilisation of processing involving the formation of a metal layer which is reactive with aluminium in a contact hole. The above description has referred only to cases in which a multi-wiring-layer structure has comprised only two wiring layers. However, it should be noted that embodiments of the present invention can be employed in the provision of multi-wiring layer-structures comprising more than two wiring layers. Thus, embodiments of the present invention provide methods of manufacturing a semiconductor device which has a multi-wiringlayer structure and has metal wiring layers composed of aluminium Al as a main component. In embodiments of the present invention a metal which is reactive with aluminium is inserted into a contact hole located between a lower metal wiring layer and an upper metal wiring layer, the upper metal wiring layer is formed in such a way as to cover the contact hole and heat treatment is applied to the device substrate, and thereby the occurrence of electrically defective connections in contact holes can be reduced or entirely avoided. WHAT WE CLAIM IS:

1. A method of manufacturing a semiconductor device, wherein a contact hole is provided in an insulating layer formed between a first wiring layer, having aluminium as a main constituent thereof, and a second wiring layer, having aluminium as a main constituent thereof, the first wiring layer being provided beneath the second wiring layer, and wherein there is provided, at least in the said contact hole, a layer of metal reactive with aluminium and of a thickness in the range from lO0A to 1 oOOA, and heating to a temperature above 300)C is effected to cause the said metal to react with the aluminium of the first wiring layer.

6. A method as claimed in any preceding claim, comprising the following steps: forming the first wiring layer, on a first insulating layer formed on a substrate of the device; forming a second insulating layer on the first wiring layer; forming a contact hole in said second insulating layer; forming in the contact hole, on the first wiring layer, a layer of the said metal reactive with aluminium, to a thickness in the range from lOOAto lOO0A; forming, at least in the contact hole, the second wiring layer so as to cover the layer of the said metal reactive with aluminium, and; reacting the aluminium of the first layer with the metal reactive with aluminium, by heating to a temperature above 300 C.

7. A method as claimed in any preceding claim, comprising the following steps:- forming the first wiring layer on a first insulating layer formed on a substrate of the device, forming a second insulating layer on the first wiring layer; forming a resist layer, on the second insulating layer, with at least one window therein for use in forming a contact hole in the second insulating layer; etching the second insulating layer using the resist layer as a mask, thereby to form the contact hole, through which a part of the first wiring layer is exposed; depositing a layer of the said metal reactive with aluminium, to a thickness in the range from 1 OOH to 1 000A, on top of the resist layer and on the exposed part of the first wiring layer; removing the resist layer together that portion of the layer of metal reactive with aluminium that is formed on said resist layer but leaving that part of the layer of reactive metal formed on the first wiring layer in the contact hole; forming the second wiring layer so as to

cover at least the contact hole, and; reacting said first wiring layer with the layer of reactive metal in the contact hole, by heating to a temperature above 3000C.

8. A method as claimed in Claim 6 or 7, wherein said metal reactive with aluminium is platinum.

9. A method as claimed in Claim 8, wherein the said layer of metal reactive with aluminium has a thickness in the range from 250A to sooA.

10. A method as claimed in any one of Claims 1 to 5, comprising the following steps: forming the said insulating layer on the first wiring layer; forming at least one contact hole in the said insulating layer so as to expose therein a part of the said first wiring layer; forming a layer of a metal which is reactive with aluminium, to a thickness in the range from 1 OoA to 1 OOOA, in contact with that part of the said first wiring layer exposed in the contact hole; forming the said second wiring layer on the said layer of metal reactive with aluminium, after forming the said metal layer; etching the said layer of metal reactive with aluminium, using said second wiring layer as a mask; and reactive said first wiring layer with said layer of metal in said contact hole, by heating to a temperature bove 300"C.

11. A method as claimed in Claim 10, wherein said metal reactive with aluminium is titanium, and wherein the formed layer of that metal has a thickness in the range from 100A to 500A.

12. A method as claimed in Claim 11, wherein the thickness of the formed layer of titanium is in the range from 150A to 200A.

13. A method of manufacturing a semiconductor device, substantially as hereinbefore described ith reference to Figure 2 or Figure 3 or Figure 4 of the accompanying drawings.

14. A semiconductor device manufactured by a method as claimed ip any preceding claim.