GB2181894A - Duplicate wiring in a semiconductor device - Google Patents
Duplicate wiring in a semiconductor device Download PDFInfo
- Publication number
- GB2181894A GB2181894A GB08624497A GB8624497A GB2181894A GB 2181894 A GB2181894 A GB 2181894A GB 08624497 A GB08624497 A GB 08624497A GB 8624497 A GB8624497 A GB 8624497A GB 2181894 A GB2181894 A GB 2181894A
- Authority
- GB
- United Kingdom
- Prior art keywords
- semiconductor device
- layer
- insulating layer
- recited
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000005360 phosphosilicate glass Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 9
- 238000002161 passivation Methods 0.000 abstract description 5
- 239000004411 aluminium Substances 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract 2
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The aluminium wiring of a semiconductor device is provided in two layers so that if a break occurs in one layer the other layer provides an alternative conduction path. As shown a first layer 20 of an aluminium wiring pattern is buried in a layer 19 of a phospho-silicate glass. A second layer 26 of the same aluminium wiring pattern is deposited on the glass with regularly spaced holes 24 through the glass coupling the two layers. The duplicate wiring is particularly effective against breaks caused by passivation cracks. <IMAGE>
Description
SPECIFICATION.
Duplicate wiring in a semiconductor device
BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to a semiconductor device and more particularly to aluminum wiring thereon.
Background Art
The prior art to which the present invention is directed includes an arrangement of a phospho-silicate glass (PSG) layer on a semiconductor substrate. Aluminium wiring is formed over the PSG layer.
Conventional aluminum wiring has posed a problem in that cracks may form in the final passivating layer which causes its deformation and may break the aluminum wiring, thus cutting off the path for the conduction of current.
SUMMARY OF THE INVENTION
The present invention is intended to solve the above problem and it is therefore an object of the present invention to provide dependable aluminum wiring in a semiconductor device.
According to the invention, there are two layers of aluminum wiring. At least one of the layers of aluminum wiring is buried in a PSG layer. When a crack causes the top layer of aluminum wiring to break, the buried layer provides a duplicate path for the conduction of current.
BRIEF DESCRIPTION OF THE DRA WINGS
Figure 1 is a sectional view of an embodiment of the present invention.
Figure 2 is a transverse sectional view of
Fig. 1.
DETAILED DESCRIPTION OF THE PREFERRED
EMBODIMENTS
Aluminum wiring is buried in a phospho-silicate glass (PSG) layer when the PSG layer is formed on a substrate. Prior to providing aluminum wiring in a conventional manner on the surface of the PSG layer, a hole is made in the PSG layer covering the buried wiring which is used to couple the previously buried aluminum wire to the surface wiring which is installed in the conventional manner. Then aluminum wiring is provided in the conventional manner on the surface.
Since aluminum wiring is installed in two layers, even if the aluminum wire in the top layer is disconnected because of a passivation crack, the aluminum wire in the buried layer remains whole and is still capable of providing a path for the conduction of current.
An embodiment of the present invention will now be described with reference to Figs. 1 and 2. Figs. 1 and 2 show orthogonal sectional views of a wired semiconductor device.
In a semiconductor substrate 10 of silicon, a source region 12 and a drain region 14 of a transistor component are formed in the conventional manner. Then a gate oxide layer 16 is deposited over the substrate 10. A gate electrode 18, of polysilicon, is deposited over the width of the gate channel and extending slightly further than the gate length between the source 12 and the drain 14. Then a first interlaminar layer 19 of PSG is deposited on top of the gate electrode 18 and of the exposed surface of the substrate 10. This first interlaminar layer 18, since it is PSG, is an insulating layer.
A buried wiring region 20 is deposited on top of the first interlaminar layer 19 of PSG generally along the path of the gate electrode 18 as well as other regions that are used as interconnections between transistors and the like. Then a second interlaminar layer 22 of
PSG is deposited on top of the buried wiring region 20 as well as of the exposed surface of the first interlaminar layer 18.
Then several holes 24 are bored by standard photolithographic techniques through the second interlaminar layer 22 at regular intervals along the path of the buried wiring region 20. A surface wiring region 26 is then deposited in nearly the same pattern as the buried wiring region 20. The surface wiring region 26 covers a portion of the surface of the second interlaminar layer 22 and it also fills the holes 24. Both of the wiring regions 20 and 26 are aluminum. Finally, a passivating layer 28 of silicon dioxide is deposited to cover the entire surface of the semiconductor chip, that is, over the surface wiring region 26 and the second interlaminar layer 22. Of course, through holes are formed at selected locations in the passivating layer 28 to permit contacting to the surface wiring region 26.
Even if the surface metal wiring region 26 is disconnected because of a passivation crack in the passivation layer 28, the buried metal wiring 20 coupled to it is still capable of providing a path for the conduction of current.
Since the buried metal wiring region 20 is buried in the second interlaminar layer 22, it is unaffected by any kind of internal stress.
As set forth above, metal wiring is provided in two layers according to the present invention and therefore the path for the conduction of current is effectively prevented form being cut off by a passivation crack.
Claims (9)
1. A semiconductor device, comprising:
a semiconductor substrate including one or more semiconductive components;
a first insulating layer overlying said substrate;
a first conductive region arranged in a wiring pattern and overlying said insulating layer;
a second insulating layer overlying said first insulating layer and a major portion of said first conductive region;
a second conductive region arranged in said wiring pattern and overlying said second insulating layer; and
a passivating layer overlying said second conductive region and said second insulating layer.
2. A semiconductor device as recited in
Claim 1, wherein said second insulating layer includes through holes at regular intervals along said wiring pattern and wherein said second conductive region fills said holes and contacts said first conductive region.
3. A semiconductor device as recited in
Claim 1, wherein said first and second conductive regions both comprise aluminum.
4. A semiconductor device as recited in
Claim 1, further comprising a gate oxide layer overlying said semiconductor substrate and a gate electrode on said gate oxide layer, said semiconductive components being formed of said semiconductor substrate, said gate oxide layer and said gate electrode.
5. A semiconductor device as recited in
Claim 4, wherein said first insulating layer is disposed between said gate electrode and said first conductive region.
6. A semiconductor device as recited in
Claim 5, wherein said first insulating layer comprises a phospho-silicate glass.
7. A semiconductor device as recited in
Claim 1, wherein said second insulating region comprises a phospho-silicate glass.
8. A semiconductor device as recited in
Claim 6, wherein said second insulating region comprises a phospho-silicate glass.
9. A semiconductor device substantially as hereinbefore described with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60231715A JPS6290950A (en) | 1985-10-16 | 1985-10-16 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8624497D0 GB8624497D0 (en) | 1986-11-19 |
| GB2181894A true GB2181894A (en) | 1987-04-29 |
| GB2181894B GB2181894B (en) | 1989-09-13 |
Family
ID=16927878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8624497A Expired GB2181894B (en) | 1985-10-16 | 1986-10-13 | Duplicate wiring in a semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS6290950A (en) |
| KR (1) | KR900001659B1 (en) |
| DE (1) | DE3635259A1 (en) |
| GB (1) | GB2181894B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0394520A1 (en) * | 1989-04-26 | 1990-10-31 | Richard Nicolaus | Apparatus and method for cutting material wound on reels |
| US4984061A (en) * | 1987-05-15 | 1991-01-08 | Kabushiki Kaisha Toshiba | Semiconductor device in which wiring layer is formed below bonding pad |
| US5463255A (en) * | 1992-03-30 | 1995-10-31 | Nec Corporation | Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion |
| EP0793176A2 (en) * | 1996-03-01 | 1997-09-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line |
| US5835419A (en) * | 1996-03-01 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with clamping circuit for preventing malfunction |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2584986B2 (en) * | 1987-03-10 | 1997-02-26 | 三菱電機株式会社 | Wiring structure of semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1244668A (en) * | 1967-12-06 | 1971-09-02 | Ibm | Improvements relating to semiconductor devices |
| EP0016577A1 (en) * | 1979-03-09 | 1980-10-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with a double interconnection layer |
| GB1596907A (en) * | 1978-05-25 | 1981-09-03 | Fujitsu Ltd | Manufacture of semiconductor devices |
| EP0048610A2 (en) * | 1980-09-22 | 1982-03-31 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacture |
| EP0103362A2 (en) * | 1982-06-30 | 1984-03-21 | Fujitsu Limited | Semiconductor device with power lines |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4617193A (en) * | 1983-06-16 | 1986-10-14 | Digital Equipment Corporation | Planar interconnect for integrated circuits |
-
1985
- 1985-10-16 JP JP60231715A patent/JPS6290950A/en active Pending
-
1986
- 1986-06-19 KR KR1019860004893A patent/KR900001659B1/en not_active IP Right Cessation
- 1986-10-13 GB GB8624497A patent/GB2181894B/en not_active Expired
- 1986-10-16 DE DE19863635259 patent/DE3635259A1/en not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1244668A (en) * | 1967-12-06 | 1971-09-02 | Ibm | Improvements relating to semiconductor devices |
| GB1596907A (en) * | 1978-05-25 | 1981-09-03 | Fujitsu Ltd | Manufacture of semiconductor devices |
| EP0016577A1 (en) * | 1979-03-09 | 1980-10-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with a double interconnection layer |
| EP0048610A2 (en) * | 1980-09-22 | 1982-03-31 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacture |
| EP0103362A2 (en) * | 1982-06-30 | 1984-03-21 | Fujitsu Limited | Semiconductor device with power lines |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984061A (en) * | 1987-05-15 | 1991-01-08 | Kabushiki Kaisha Toshiba | Semiconductor device in which wiring layer is formed below bonding pad |
| EP0394520A1 (en) * | 1989-04-26 | 1990-10-31 | Richard Nicolaus | Apparatus and method for cutting material wound on reels |
| US5463255A (en) * | 1992-03-30 | 1995-10-31 | Nec Corporation | Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion |
| EP0793176A2 (en) * | 1996-03-01 | 1997-09-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line |
| EP0793176A3 (en) * | 1996-03-01 | 1997-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line |
| US5825694A (en) * | 1996-03-01 | 1998-10-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line |
| US5835419A (en) * | 1996-03-01 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with clamping circuit for preventing malfunction |
| US5986915A (en) * | 1996-03-01 | 1999-11-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6290950A (en) | 1987-04-25 |
| DE3635259A1 (en) | 1987-04-16 |
| KR870004502A (en) | 1987-05-09 |
| GB2181894B (en) | 1989-09-13 |
| GB8624497D0 (en) | 1986-11-19 |
| KR900001659B1 (en) | 1990-03-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 746 | Register noted 'licences of right' (sect. 46/1977) |
Effective date: 19951108 |
|
| PE20 | Patent expired after termination of 20 years |
Effective date: 20061012 |