KR100203305B1 - Method of passivation semiconductor device - Google Patents
Method of passivation semiconductor device Download PDFInfo
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- KR100203305B1 KR100203305B1 KR1019960025026A KR19960025026A KR100203305B1 KR 100203305 B1 KR100203305 B1 KR 100203305B1 KR 1019960025026 A KR1019960025026 A KR 1019960025026A KR 19960025026 A KR19960025026 A KR 19960025026A KR 100203305 B1 KR100203305 B1 KR 100203305B1
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- film
- passivation
- semiconductor device
- insulating film
- metal pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
Abstract
본 발명은 패시베이션막에 의한 스트레스를 방지할 수 있는 반도체 소자의 패시베이션 방법이 개시된다. 개시된 본 발명은 트랜지스터 및 그 밖의 소자가 형성된 반도체 소자를 제공하는 단계; 반도체 소자에 전기적연결을 위한 금속 배선 및 패드 금속 패턴을 형성하는 단계; 반도체 기판의 결과물 상부에 절연막을 형성하는 단계; 절연막 상부에 완충용 금속막을 증착하는 단계; 패드 금속 패턴을 오픈시키는 단계; 전체 구조물 상부에 패시베이션막을 형성하는 단계; 및 패시베이션막의 소정 부분을 식각하여 패드 금속 패턴을 오픈시키는 단계를 포함한다.The present invention discloses a passivation method of a semiconductor device capable of preventing stress caused by a passivation film. Disclosed is a semiconductor device comprising: providing a semiconductor device on which transistors and other devices are formed; Forming a metal wire and a pad metal pattern for electrical connection to the semiconductor device; Forming an insulating film on the resultant of the semiconductor substrate; Depositing a buffer metal film on the insulating film; Opening the pad metal pattern; Forming a passivation film on the entire structure; And etching the predetermined portion of the passivation film to open the pad metal pattern.
Description
제1도는 종래의 반도체 소자의 금속 배선 상부에 패시베이션막이 형성된 도면.1 is a view in which a passivation film is formed on a metal wiring of a conventional semiconductor device.
제2a도 내지 제2d도는 본 발명의 반도체 소자의 패시베이션 방법을 공정 순서적으로 나타낸 단면도.2A to 2D are cross-sectional views sequentially showing a passivation method for a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 12 : 금속배선11 semiconductor substrate 12 metal wiring
12A : 패드 금속 패턴 13 : 제1금속간 절연막12A: pad metal pattern 13: first intermetallic insulating film
14 : 평탄화 절연막 15 : 제2금속간 절연막14 planarization insulating film 15 second intermetallic insulating film
16 : 금속막 17 : USG막16 metal film 17 USG film
18 : 질화막18: nitride film
[발명의 기술분야]Technical Field of the Invention
본 발명은 반도체 소자의 패시베이션(passivation) 방법에 관한 것으로, 보다 구체적으로는 패시베이션 공정시, 금속 배선에 인가되는 스트레스를 줄일 수 있는 반도체 소자의 패시베이션 방법에 관한 것이다.The present invention relates to a passivation method of a semiconductor device, and more particularly to a passivation method of a semiconductor device that can reduce the stress applied to the metal wiring during the passivation process.
[종래 기술][Prior art]
일반적으로, 패시베이션 공정은, 반도체 기판에 형성된 소자들을 보호하는 막을 덮는 공정으로, 대부분 금속 배선 상부에 질화막과 같은 수분 흡수 능력을 갖는 막이 증착된다.In general, a passivation process is a process of covering a film protecting elements formed on a semiconductor substrate, and a film having a water absorption capability such as a nitride film is deposited on most of the metal wirings.
여기서, 종래의 금속 배선막 상부에 패시베이션막이 형성된 공정으로, 제1도에 도시된 바와 같이, 모스 트랜지스터 및 그 밖의 소자가 형성된 반도체 기판(1) 상부에 금속 배선이 형성된다. 이 금속 배선은 고집적화 되어 감에 따라, 약 0.4 내지 0.5㎛의 간격으로 금속 배선(2)이 형성된다. 이어서, 전체 구조물 상부에 패시베이션막(3)으로, PE(plasma enhanced) 방식에 의하여 형성된, USG(undoped silicate glass)막과, 동일한 방식에 의하여 형성된 질화막이 형성된다.Here, in the process of forming the passivation film on the conventional metal wiring film, as shown in FIG. 1, the metal wiring is formed on the semiconductor substrate 1 on which the MOS transistor and other elements are formed. As the metal wirings become highly integrated, the metal wirings 2 are formed at intervals of about 0.4 to 0.5 mu m. Subsequently, a nitride film formed by the same method as the undoped silicate glass (USG) film formed by the plasma enhanced (PE) method is formed as the passivation film 3 on the entire structure.
[발명이 이루고자 하는 기술적 과제][Technical problem to be achieved]
그러나, 종래의 패시베이션 방법은, 다음과 같은 문제점이 발생되었다.However, the following problems arise in the conventional passivation method.
첫째로는, 금속 배선의 간격에 의한 문제점으로, 금속 배선 간격이 미세할 경우에는, 패시베이션막이 상부 및 측부 고르게 증착되지 않아, 이후의 팩키지 공정시 금속 배선이 부식되는 문제점이 발생되었으며, 또한 금속 배선의 간격이 넓을 경우에는, 금속 배선 사이에 패시베이션막이 매립되게 되는 문제점이 발생되었다.First, due to the problem of the spacing of the metal wiring, when the spacing of the metal wiring is minute, the passivation film is not evenly deposited on the upper side and the side, which causes the problem of corrosion of the metal wiring during the subsequent package process, and also the metal wiring. When the interval of is wide, a problem arises in that the passivation film is buried between the metal wirings.
둘째로는, 패시베이션막 자체의 문제점으로, 종래의 패시베이션으로 이용되는 막으로, 수분 흡착 특성이 우수한 USG막과 질화막이 이용되는데, 이 막들중 질화막은 하부 금속 배선에 치명적인 스트레스를 인가하므로, 소자의 특성을 열화시키게 되는 문제점이 발생되었다.Secondly, due to the problem of the passivation film itself, a USG film and a nitride film having excellent moisture adsorption characteristics are used as a film used as a conventional passivation. Among these films, since the nitride film applies a critical stress to the lower metal wiring, The problem of deteriorating characteristics has arisen.
따라서, 본 발명은, 상기와 같은 종래의 문제점을 해결하기 위한 것으로, 패시베이션막과, 금속 배선 사이에 평탄화막이 구비된 스트레스 완충용 금속막을 개제하여, 패시베이션막을 고르게 증착함과 더불어, 금속 배선에 가해지는 스트레스를 최소화할 수 있는 반도체 소자의 패시베이션 방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention is to solve the above-mentioned conventional problems, by interposing a passivation film and a stress buffer metal film provided with a planarization film between the metal wiring, and evenly depositing the passivation film and applying it to the metal wiring. It is an object of the present invention to provide a passivation method of a semiconductor device which can minimize stress.
[발명의 구성 및 작용][Configuration and Function of Invention]
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 트랜지스터 및 그 밖의 소자가 형성된 반도체 소자를 제공하는 단계; 상기 반도체 소자에 전기적 연결을 위한 금속 배선 및 패드 금속 패턴을 형성하는 단계; 반도체 기판의 결과물 상부에 절연막을 형성하는 단계; 상기 절연막 상부에 완충용 금속막을 증착하는 단계; 상기 패드 금속 패턴을 오픈시키는 단계; 전체 구조물 상부에 패시베이션막을 형성하는 단계; 및 상기 패시베이션막의 소정 부분을 식각하여 패드 금속 패턴을 오픈시키는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention comprises the steps of providing a semiconductor device formed with a transistor and other devices; Forming a metal wire and a pad metal pattern for electrical connection to the semiconductor device; Forming an insulating film on the resultant of the semiconductor substrate; Depositing a buffer metal film on the insulating film; Opening the pad metal pattern; Forming a passivation film on the entire structure; And opening a pad metal pattern by etching a predetermined portion of the passivation layer.
즉, 본 발명은, 금속 배선과 패시베이션막 사이에 평탄화막 및 스트레스 완충용 금속막을 형성하여, 패시베이션 공정시, 패시베이션막이 고르게 증착되게 하고, 또한 금속 배선에 미치는 스트레스를 최소화할 수 있다.That is, according to the present invention, the planarization film and the stress buffer metal film are formed between the metal wiring and the passivation film so that the passivation film is evenly deposited during the passivation process, and the stress on the metal wiring can be minimized.
[실시예]EXAMPLE
이하, 첨부한 도면에 의하여 본 발명의 바람직한 실시예를 자세히 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2d도는 본 발명의 반도체 소자의 패시베이션 방법을 공정 순차적으로 나타낸 단면도로서, 제2a도에 도시된 바와 같이, 금속 배선을 형성하기 이전의 공정이 진행된 반도체 기판(11) 상부에 금속 배선(12)이 형성되며, 이 금속 배선(12)을 형성하는 공정과 동시에, 패드 금속 패턴(12A)도 형성된다. 이때, 패드 금속 패턴(12A)의 폭은 금속 배선(12)의 폭보다 넓게 형성한다. 그런다음, 반도체 기판의 결과물 상부에 제1금속간 절연막(13)이 증착된다. 이때, 상기 제1금속간 절연막(13)은, 후속으로 진행되는 평탄화 절연막의 증착 공정시, 평탄화 절연막과 금속 배선감의 접촉을 방지하기 위함이다.2A to 2D are cross-sectional views sequentially illustrating a passivation method of a semiconductor device of the present invention. As shown in FIG. 2A, a metal is formed on a semiconductor substrate 11 on which a process before forming metal wiring is performed. The wiring 12 is formed, and at the same time as the process of forming this metal wiring 12, the pad metal pattern 12A is also formed. At this time, the width of the pad metal pattern 12A is formed to be wider than the width of the metal wiring 12. Then, the first intermetallic insulating layer 13 is deposited on the resultant of the semiconductor substrate. In this case, the first intermetallic insulating layer 13 is for preventing contact between the planarizing insulating layer and the metal wiring during the subsequent deposition process of the planarizing insulating layer.
이어서, 제2b도는 제1금속간 절연막(13) 상부에 평탄화 절연막(14)과, 제2금속간 절연막(15)이 형성된 도면으로, 하부의 토폴로지를 없애기 위하여, 평탄화 절연막(14) 바람직하게는 SOG막이 구조물 상부에 도포되고, 이어서, 제2금속간 절연막(15)이 소정 두께로 증착된다. 이때, 제2금속간 절연막(15)은 하부의 금속 배선에 스트레스를 적게 인가되는 막으로, 바람직하게는 실리콘 산화막, TEOS막등이 이용된다.Next, FIG. 2B is a view in which the planarization insulating film 14 and the second intermetallic insulating film 15 are formed on the first intermetallic insulating film 13. In order to eliminate the underlying topology, the planarizing insulating film 14 is preferable. An SOG film is applied over the structure, and then a second intermetallic insulating film 15 is deposited to a predetermined thickness. At this time, the second intermetallic insulating film 15 is a film that is applied with less stress to the lower metal wiring, and preferably, a silicon oxide film, a TEOS film, or the like is used.
그런다음, 제2c도에 도시된 바와 같이, 전체 구조물 상부에 금속막(16)이 증착된다. 이때, 금속막(16)은 이후의 패시베이션 공정시, 인가되는 스트레스를 하부 금속 배선에 이동시키지 않기 위하여 형성되는 스트레스 완충막이다.Then, as shown in FIG. 2C, a metal film 16 is deposited over the entire structure. At this time, the metal film 16 is a stress buffer film formed so as not to transfer the applied stress to the lower metal wiring during the subsequent passivation process.
이어서, 제2d도에 도시된 바와 같이, 완충용 금속막(16) 상부에 하부의 패드 금속 패턴이 노출될 수 있도록 마스크 패턴(도시되지 않음)이 형성되고, 이것의 형태로, 완충용 금속막(16), 제2금속간 절연막(15), 층간 평탄화막(14), 제1금속간 절연막(13)이 순차적으로 식각되어, 패드 금속 패턴(12A)이 오픈된다. 이때, 패시베이션막이 증착되기 이전에 미리 패드 금속 패턴(12A)을 오픈시키는 것은, 완충용 금속막이 반도체 소자에서 배선의 역할을 하는 것을 배제하기 위함이다. 그 후, 결과물 상부에 PE방식에 의하여, USG막(17)과 질화막(18)이 증착되고, 다시 패드 오픈 공정이 실시되어, 패드 금속 패턴의 일부분이 오픈된다. 이때, USG막(17)은 질화막 완충용 금속간의 접촉 특성을 개선하기 위하여, 개재되는 막으로써, USG막(17) 증착 공정을 배제하여도 무방하다. 또한, 상기 패드 금속(12A)막의 폭은 금속 배선 폭(12)보다 크지만 실제적으로 패시베이션막에 의하여 노출되는 면은 적다.Subsequently, as shown in FIG. 2D, a mask pattern (not shown) is formed on the buffer metal film 16 so that the lower pad metal pattern is exposed, and in this form, the buffer metal film. 16, the second intermetallic insulating film 15, the interlayer planarization film 14, and the first intermetallic insulating film 13 are sequentially etched to open the pad metal pattern 12A. In this case, the pad metal pattern 12A is opened in advance before the passivation film is deposited in order to exclude the buffer metal film from acting as a wiring in the semiconductor device. Thereafter, the USG film 17 and the nitride film 18 are deposited by the PE method on the resultant, and the pad opening process is performed again, so that a part of the pad metal pattern is opened. At this time, the USG film 17 is an interposed film in order to improve the contact characteristics between the nitride film buffer metals, and the USG film 17 deposition process may be excluded. Further, the width of the pad metal 12A film is larger than the metal wiring width 12, but the surface of the pad metal 12A is substantially exposed by the passivation film.
[발명의 효과][Effects of the Invention]
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 금속 배선과 패시베이션막 사이에 평탄화막 및 스트레스 완층용 금속막을 형성하여, 패시베이션 공정시, 패시베이션막이 고르게 증착되게 하고, 또한 금속 배선에 미치는 스트레스를 최소화 할 수 있다. 이에 따라, 소자의 특성이 개선된다.As described in detail above, according to the present invention, a planarization film and a stress relief metal film are formed between the metal wiring and the passivation film, so that the passivation film is evenly deposited during the passivation process, and the stress on the metal wiring can be minimized. Can be. Accordingly, the characteristics of the device are improved.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960025026A KR100203305B1 (en) | 1996-06-28 | 1996-06-28 | Method of passivation semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960025026A KR100203305B1 (en) | 1996-06-28 | 1996-06-28 | Method of passivation semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR980005838A KR980005838A (en) | 1998-03-30 |
| KR100203305B1 true KR100203305B1 (en) | 1999-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960025026A KR100203305B1 (en) | 1996-06-28 | 1996-06-28 | Method of passivation semiconductor device |
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| Country | Link |
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| KR (1) | KR100203305B1 (en) |
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1996
- 1996-06-28 KR KR1019960025026A patent/KR100203305B1/en not_active IP Right Cessation
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| KR980005838A (en) | 1998-03-30 |
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