JPH079972B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and an improvement thereof. In particular, the present invention relates to an improvement in a semiconductor device in which a MOSFET made of polycrystalline Si or a crystalline film thereof is further integrated on a MOSFET on a Si substrate.

[Conventional technology]

A partial cross section of the device structure according to the present invention is shown in FIGS. 1 and 2.

101 is a Si substrate, 104 is a source / drain, 103 is a gate, which is a normal MOSFET, and 107 and 108 are polycrystalline Si FETs. 107 is a source / drain and 108 is a conductive region. In this example, the gate 103 is common. An example that is not common is shown in Fig. 2. The gate of the FET made of polycrystalline Si is 209
Is. At this time, the wiring material, which is one element of the integrated circuit, is wired as shown in FIGS. Wiring material is 30
Shown at 1,401. This example is an example in which the drains of the upper and lower FETs are connected, and FIG. 5 is a plan view of the example of FIG.

Each part is indicated by the same number as each part in FIG.

[Problems to be solved by the invention]

The hole 501 for making electrical contact with the wiring material is
Since the wiring member is brought into contact with both of them 104, the size becomes large, and the margin for considering the positional deviation becomes large.
The present invention solves such a problem.

[Means for solving problems]

The present invention relates to a semiconductor device having a first field effect transistor and a second field effect transistor above the first field effect transistor, wherein the source and drain regions of the first field effect transistor are provided on a semiconductor substrate. A first impurity diffusion region, a gate electrode of the first field effect transistor provided above the first impurity diffusion region, and a source and drain region of the second field effect transistor provided above the first impurity diffusion region. A first conductor layer having a second impurity diffusion region, and a first conductor layer provided above the first impurity diffusion region and provided in a conductor layer different from the first conductor layer via an insulating film. 2 The gate electrode of the field effect transistor, the opening portion penetrating the first conductor layer, and the first portion inside the opening portion.
A wiring material is disposed so as to be in electrical contact with the conductor layer on its side surface, and the wiring material connects the second impurity diffusion region and the first impurity diffusion region. And

[Embodiment] An embodiment is shown in FIGS. 6 and 7. Although either of the element structures shown in FIGS. 1 and 2 can be applied, the element structure shown in FIG. 1 will be described for convenience.

The configuration of this embodiment is as follows.

The lower MOSFET is composed of a diffusion layer 602 serving as the source and drain regions provided on the semiconductor substrate and a gate electrode 603 provided on the diffusion layer 602.

The upper MOSFET provided thereabove is a polycrystalline silicon layer including impurity diffusion regions serving as source and drain regions.
604 and a polycrystalline silicon layer 604 have a gate electrode 603 provided in a different layer with an insulating film interposed therebetween. Further holes 701
A diffusion layer 602 of Si substrate penetrating through 604 polycrystalline silicon layers.
The electrical contact between the wiring material 601 and the polycrystalline Si 604 is made on the side surface of the opening of the 604. Also the 6th
As shown in the figure, open the contact holes with polycrystalline silicon.
The contact area between the polycrystalline silicon 604 and the wiring material 601 is increased and the contact resistance is reduced by forming the holes in a slightly oblique manner and embedding the wiring material 601 instead of providing them perpendicularly to the 604. You can also As is clear from FIGS. 6 and 7, it goes without saying that the wiring 601 connects the polycrystalline silicon layer 604 and the diffusion layer 602 of the Si substrate.

〔The invention's effect〕

As can be seen by comparing FIG. 5 and FIG. 7, the opening in FIG. 7 is opened on the 604, and its size may be as small as possible for processing, and its position. There is almost no need to afford the gap. Therefore, a semiconductor device having a higher degree of integration can be provided.

[Brief description of drawings]

 1 and 2 are views showing an element structure related to the present invention. FIG. 3, FIG. 4, and FIG. 5 are views showing a conventional example. 6 and 7 are views showing an embodiment of the present invention.

Claims (1)

[Claims] 1. A semiconductor device having a first field effect transistor and a second field effect transistor above the first field effect transistor, wherein the source and drain regions of the first field effect transistor are provided on a semiconductor substrate. A first impurity diffusion region, a gate electrode of the first field effect transistor provided above the first impurity diffusion region, a source and a drain of the second field effect transistor provided above the first impurity diffusion region A first conductor layer having a second impurity diffusion region serving as a region, the first conductor layer being provided above the first impurity diffusion region, and
The gate electrode of the second field effect transistor provided in a conductor layer different from the conductor layer via an insulating film, an opening penetrating the first conductor layer, and inside the opening, the first electrode A wiring material arranged so as to be in electrical contact with one conductor layer on a side surface, and the wiring material is for wiring the second impurity diffusion region and the first impurity diffusion region. Characteristic semiconductor device.