JPH0527996B2 - - Google Patents
Info
- Publication number
- JPH0527996B2 JPH0527996B2 JP1013185A JP1013185A JPH0527996B2 JP H0527996 B2 JPH0527996 B2 JP H0527996B2 JP 1013185 A JP1013185 A JP 1013185A JP 1013185 A JP1013185 A JP 1013185A JP H0527996 B2 JPH0527996 B2 JP H0527996B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- source
- semiconductor substrate
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、MOS集積回路装置、特にソース電
極と半導体基板とが接続されているトランジスタ
の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS integrated circuit device, particularly to the structure of a transistor in which a source electrode and a semiconductor substrate are connected.
従来、ソース電極と半導体基板とが、接続され
ているMOSトランジスタのソース電極と半導体
基板との接続部を形成する場合、Ｎ形半導体基板
表面上にＰ形ソース領域およびＮ形の不純物領域
を隣接して形成し、これらＰ形ソース領域とＮ形
の不純物領域とを金属層で接続することにより形
成していた。
Conventionally, when a source electrode and a semiconductor substrate form a connection between the source electrode of a MOS transistor and a semiconductor substrate, a P-type source region and an N-type impurity region are placed adjacent to each other on the surface of an N-type semiconductor substrate. The P-type source region and the N-type impurity region are connected by a metal layer.
この一例として、従来のＮ形半導体基板上のＰ
チヤンネル型MOSトランジスタの構造断面図を
第２図に示す。Ｎ形半導体基板１にこの半導体基
板１に電位を与えるＮ形不純物領域７とソース、
ドレイン領域となるＰ形不純物領域２と２′とを
選択拡散し、全表面に存在する絶縁膜６のＰ形領
域２，２′間を除去し、ここに熱酸化による薄い
ゲート絶縁膜を新らたに設け、ドレイン領域とな
る形Ｐ領域２′上およびソース領域となるＰ形領
域２とＮ型領域７とにまたがる領域上の絶縁膜６
を選択的に除去し、その後選択的に金属層を設け
てソース電極３、ドレイン電極４、ゲート電極５
を形成している。Ｎ形領域７とソース領域である
Ｐ形領域２とはソース電極３により接続されて、
ソース領域と半導体基板１とが同電位となつてい
る。 An example of this is P on a conventional N-type semiconductor substrate.
A cross-sectional view of the structure of a channel-type MOS transistor is shown in FIG. An N-type impurity region 7 that applies a potential to the N-type semiconductor substrate 1 and a source;
The P-type impurity regions 2 and 2', which will become the drain region, are selectively diffused, and the area between the P-type regions 2 and 2' of the insulating film 6 existing on the entire surface is removed, and a new thin gate insulating film is formed there by thermal oxidation. An insulating film 6 is provided on the P-type region 2' that becomes the drain region and on the region spanning the P-type region 2 and the N-type region 7 that becomes the source region.
is selectively removed, and then a metal layer is selectively provided to form the source electrode 3, drain electrode 4, and gate electrode 5.
is formed. The N-type region 7 and the P-type region 2, which is a source region, are connected by a source electrode 3.
The source region and semiconductor substrate 1 are at the same potential.
ここで、半導体基板１に電位の与える為に必要
とするＮ形領域７の必要最小幅をＡとすると、必
要な面積はA2である。今かりに、ソース電極３
によりソース領域であるＰ型領域２と半導体基板
１とが接続されているトランジスタが、集積回路
装置の１チツプにつきＮ個あるとすると、集積回
路装置の１チツプに必要な面積は、トランジスタ
の面積の外にＮ・A2で表わされるＮ型領域７の
領域が必要であり、これはトランジスタの個数Ｎ
に比例する。このことは、集積回路装置のチツプ
サイズ縮小を実現される為の一つの障害である。
Here, if the required minimum width of the N-type region 7 required to apply a potential to the semiconductor substrate 1 is A, the required area is A2 . Now, source electrode 3
Assuming that there are N transistors in each chip of an integrated circuit device in which the P-type region 2, which is the source region, and the semiconductor substrate 1 are connected, the area required for one chip of the integrated circuit device is the area of the transistor. In addition to the number of transistors N
is proportional to. This is one of the obstacles to realizing a reduction in the chip size of integrated circuit devices.
本発明の目的は、ソース電極と半導体基板が接
続されているトランジスタの必要占有面積を小さ
くする構造を提供することにある。 An object of the present invention is to provide a structure that reduces the required area occupied by a transistor in which a source electrode and a semiconductor substrate are connected.
本発明によれば、半導体基板上に一導電形の第
１不純物領域を設け、この第１不純物領域上に金
属層を設け、この第１不純物領域、金属層および
半導体基板上に一導電型のエピタキシヤル領域を
設け、このエピタキシヤル領域の表面領域に他の
導電形のソース及びドレイン領域を、ソース領域
が金属層と縦形構造で接続されるように設け、ソ
ース領域およびドレイン領域間のエピタキシヤル
領域上にゲート絶縁膜を介してゲート電極を設け
たMOSトランジスタの構造を得る。
According to the present invention, a first impurity region of one conductivity type is provided on a semiconductor substrate, a metal layer is provided on the first impurity region, and a first impurity region of one conductivity type is provided on the first impurity region, the metal layer, and the semiconductor substrate. An epitaxial region is provided, source and drain regions of other conductivity types are provided in the surface region of the epitaxial region such that the source region is connected to the metal layer in a vertical structure, and an epitaxial region between the source region and the drain region is provided. A MOS transistor structure is obtained in which a gate electrode is provided on the region via a gate insulating film.
次に本発明を図面を用いてより詳細に説明す
る。
Next, the present invention will be explained in more detail using the drawings.
第１図に本発明の一実施例を示す。Ｎ形半導体
基板８に、Ｎ形不純物領域９を有し、さらにＮ形
不純物領域９上に金属層１０を有している。これ
らＮ形不純物領域９、金属層１０および残余のＮ
型半導体基板８上にＮ形エピタキシヤル領域１１
を有し、このＮ形エピタキシヤル領域１１の表面
に、ソース領域、ドレイン領域となるＰ形領域１
２及び１２′を有している。ソース領域となるＰ
型領域１２は少くとも金属層１０に達する深さで
形成されている。ソースおよびドレイン領域とな
る。厚いフイールド酸化膜１３のＰ形領域１２，
１２′間上の部分は一旦除去されて薄いゲート酸
化膜を新らたに熱酸化で形成されている。フイー
ルド酸化膜１３はソース領域であるＰ形領域１２
上およびドレイン領域であるＰ型領域１２′上に
開孔を有し、ここにソース電極１４、ドレイン電
極１５が設けられている。ゲート酸化膜上にはゲ
ート電極１６を有している。 FIG. 1 shows an embodiment of the present invention. An N-type semiconductor substrate 8 has an N-type impurity region 9, and a metal layer 10 is further provided on the N-type impurity region 9. These N type impurity regions 9, metal layer 10 and remaining N
An N-type epitaxial region 11 is formed on a type semiconductor substrate 8.
On the surface of this N-type epitaxial region 11, a P-type region 1 which becomes a source region and a drain region is formed.
2 and 12'. P becomes the source area
The mold region 12 is formed to a depth that reaches at least the metal layer 10. These become source and drain regions. P-type region 12 of thick field oxide film 13,
The portion above the area 12' is once removed and a new thin gate oxide film is formed by thermal oxidation. The field oxide film 13 is a P-type region 12 which is a source region.
There are openings above the P-type region 12' which is the upper and drain region, and a source electrode 14 and a drain electrode 15 are provided therein. A gate electrode 16 is provided on the gate oxide film.
このように、ソース領域であるＰ型領域１２は
金属層１０と接続され、この金属層１０はＮ形不
純物領域９と接続されており、縦形構造で、ソー
ス電極１４はソース領域であるＰ形領域１２、金
属層１０およびＮ形不純物領域９を介して半導体
基板８およびエピタキシヤル領域１１に電気的に
接続されている。このＮ形不純物領域９はソース
領域であるＰ形領域１２の直下に形成されている
ため、半導体基板８およびエピタキシヤル領域１
１に電位を与えるために必要な平面面積はまつた
く必要としない。かかるMOSトランジスタを用
いたMOS集積回路ではトランジスタの構成に必
要なソース領域、ゲート領域およびドレイン領域
の他に付加的なソース電極と半導体基板もしくは
エピタキシヤル領域を接続する領域はまつたく必
要としない。このため、集積回路装置のチツプサ
イズ縮小を可能にする点でその効果は非常に大き
い。 In this way, the P-type region 12, which is a source region, is connected to the metal layer 10, which is connected to the N-type impurity region 9, and has a vertical structure, and the source electrode 14 is connected to the P-type region, which is a source region. It is electrically connected to semiconductor substrate 8 and epitaxial region 11 via region 12 , metal layer 10 and N-type impurity region 9 . Since this N-type impurity region 9 is formed directly under the P-type region 12 which is a source region, the semiconductor substrate 8 and the epitaxial region 1
The planar area required to apply a potential to 1 is not required at all. A MOS integrated circuit using such a MOS transistor does not require any additional region for connecting the source electrode and the semiconductor substrate or epitaxial region in addition to the source region, gate region, and drain region necessary for the structure of the transistor. Therefore, the effect is very large in that it enables the chip size of integrated circuit devices to be reduced.
本発明によれば、必要面積の小さなMOSトラ
ンジスタを得ることができる。
According to the present invention, a MOS transistor with a small required area can be obtained.
第１図は本発明の一実施例によるMOSトラン
ジスタの断面図、第２図は従来のMOSトランジ
スタの断面図である。
１，８……Ｎ形半導体基板、２，２′，１２，
１２′……Ｐ形領域、３，１４……ソース電極、
４，１５……ドレイン電極、５，１６……ゲート
電極、６，１３……絶縁膜、７，９……Ｎ形不純
物領域、１０……金属層、１１……Ｎ形エピタキ
シヤル領域。
FIG. 1 is a sectional view of a MOS transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional MOS transistor. 1, 8...N-type semiconductor substrate, 2, 2', 12,
12'...P-type region, 3,14...source electrode,
4,15...Drain electrode, 5,16...Gate electrode, 6,13...Insulating film, 7,9...N type impurity region, 10...Metal layer, 11...N type epitaxial region.
Claims (1)
有し、該第１不純物領域上に金属層を有し、前記
金属層上、前記第１不純物領域上および前記半導
体基板上に前記一導電形のエピタキシヤル領域を
有し、該エピタキシヤル領域上に他の導電形のソ
ース及びドレイン領域を、前記ソース領域が前記
金属層と接触するように有し、前記ソース及びド
レイン領域間の前記エピタキシヤル領域上にゲー
ト絶縁膜とその上のゲート電極とを有することを
特徴とするMOSトランジスタ。1 A first impurity region of one conductivity type is provided on a semiconductor substrate, a metal layer is provided on the first impurity region, and the one conductivity type is provided on the metal layer, the first impurity region, and the semiconductor substrate. having source and drain regions of other conductivity types on the epitaxial regions such that the source regions are in contact with the metal layer; 1. A MOS transistor comprising a gate insulating film and a gate electrode on the gate insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1013185A JPS61170068A (en) | 1985-01-23 | 1985-01-23 | Mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1013185A JPS61170068A (en) | 1985-01-23 | 1985-01-23 | Mos transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61170068A JPS61170068A (en) | 1986-07-31 |
| JPH0527996B2 true JPH0527996B2 (en) | 1993-04-22 |
Family
ID=11741730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1013185A Granted JPS61170068A (en) | 1985-01-23 | 1985-01-23 | Mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61170068A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5023196A (en) * | 1990-01-29 | 1991-06-11 | Motorola Inc. | Method for forming a MOSFET with substrate source contact |
| WO1991013347A1 (en) * | 1990-02-22 | 1991-09-05 | Nkk Corporation | Magnetic flaw detector for thin steel belt |
| US5512821A (en) * | 1991-06-04 | 1996-04-30 | Nkk Corporation | Method and apparatus for magnetically detecting defects in an object with compensation for magnetic field shift by means of a compensating coil |
-
1985
- 1985-01-23 JP JP1013185A patent/JPS61170068A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61170068A (en) | 1986-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR970003831A (en) | Semiconductor device having another conductive semiconductor region insulated by field oxide and method of manufacturing the same | |
| JP2609753B2 (en) | Semiconductor device | |
| US5192993A (en) | Semiconductor device having improved element isolation area | |
| JP3128364B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH01128568A (en) | Semiconductor device | |
| US3643139A (en) | Integrated circuit having four mosfet devices arranged in a circle surrounding a guard diffusion | |
| JPH0527996B2 (en) | ||
| JPS5951143B2 (en) | MIS type semiconductor device | |
| JP2608976B2 (en) | Semiconductor device | |
| KR960026934A (en) | Bipolar transistor, semiconductor device comprising bipolar transistor and method of manufacturing same | |
| JPH0222868A (en) | Insulated-gate field-effect transistor | |
| JP2978504B2 (en) | MOS transistor | |
| JP2598446B2 (en) | MIS-FET | |
| JPH061816B2 (en) | Method for manufacturing semiconductor device | |
| JPS58116763A (en) | Mos type rom | |
| JP2668713B2 (en) | High voltage semiconductor device | |
| JPS6036110B2 (en) | semiconductor equipment | |
| JP2624373B2 (en) | Semiconductor device | |
| JP2993041B2 (en) | Complementary MOS semiconductor device | |
| JP2968640B2 (en) | Semiconductor device | |
| JPH065751B2 (en) | Insulated gate field effect transistor | |
| JPS6019667B2 (en) | integrated circuit semiconductor device | |
| KR950007163A (en) | Semiconductor device having MOS transistor and manufacturing method thereof | |
| JPH07105493B2 (en) | MIS type transistor | |
| JPH0247873A (en) | Semiconductor integrated circuit device |