JPS61170068A - Mos transistor - Google Patents

Abstract

PURPOSE:To scale down the chip size of an integrated circuit device by reducing the required occupying area of a transistor in which a source electrode and a semiconductor substrate are connected. CONSTITUTION:A P-type region 12 as a source region is connected to a metallic layer 10, the metallic layer 10 is connected to an N-type impurity region 9, vertical type structure is formed, and a source electrode 14 is connected electrically to a semiconductor substrate 8 and an epitaxial region 11 through the P-type region 12 as the source region, the metallic layer 10 and the N-type impurity region 9. The N-type impurity region 9 is shaped just under the P-type region 12 as the source region, thus requiring no plane area necessary for applying potential to the semiconductor substrate 8 and the epitaxial region 11. Accordingly, the chip size of an integrated circuit device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MO8 integrated circuit device, particularly to the structure of a transistor in which a source electrode and a semiconductor substrate are connected.

[Conventional technology]

Conventionally, an MO in which a source electrode and a semiconductor substrate are connected
When forming a connection between the source electrode of an 8-type transistor and a semiconductor substrate, a P-type source region and an N-type impurity region are formed adjacent to each other on the surface of an N-type semiconductor substrate.
An edge is formed by connecting the N-type source region and the N-type impurity region with a metal layer.

As an example of this, a structural cross-sectional view of a P-channel MO8) transistor on a conventional N-type semiconductor substrate is shown in Figure 2.
N-type semiconductor substrate 1 which applies a potential to this semiconductor substrate 1
type impurity region 7 and source.

The P-type impurity regions 2 and 2', which will become the drain region, are selectively diffused, and the insulating film 60 existing on the entire surface is removed between the P-type regions 2 and 2', and a new thin gate insulating film is formed there by thermal oxidation. The insulating film 6 on the P shadow region 2' which becomes the drain region and the region spanning the P shadow region 2 and the N type region 7 which becomes the source region is selectively removed, and then the metal layer is selectively removed. Provide a source electrode 3. Drain '1 pole 4. A gate electrode 5 is formed. Shadow area 7 and source area P
The source electrode 3 is electrically connected to the shadow region 2, so that the source region and the semiconductor substrate 1 are at the same potential.

[Means that the invention seeks to solve]

Here, if the required minimum width tA of the N shadow area 7 required to provide about 1 vct of semiconductor substrate is given, the required area is A
It is. Assuming that there are eight transistors in each chip of an integrated circuit device in which the source electrode 3 is connected to the P-type head region 2, which is the source region, and the semiconductor substrate 1, one chip of the integrated circuit device requires eight transistors. In addition to the area of the transistor, an area of the N-type region 7 represented by I/cN-A2 is required, and the area is proportional to the number N of transistors. This is one of the obstacles to realizing a full reduction in the chip size of integrated circuit devices.

An object of the present invention is to provide a structure that reduces the required area occupied by a transistor in which a source electrode and a semiconductor substrate are connected.

[Means to solve all problems]

According to the present invention, a first impurity region of one conductivity type is provided on a semiconductor substrate, a metal layer is provided on the first impurity region, and the first impurity region and the metal layer are formed on the semiconductor substrate. An epitaxial region of a conductivity type is provided, and source and drain regions of another conductivity type are provided in the surface region of this epitaxial region in a manner in which the source region is connected to the metal layer in a vertical structure, and between the source region and the drain region. MU with a gate electrode provided on the epitaxial region of the MU with a gate insulating film interposed therebetween.
S) Obtain the structure of the transistor.

〔Example〕

Next, the present invention will be explained in detail using the drawings.

! FIG. 41 shows an N-type semiconductor substrate 8 showing an embodiment of the present invention.
It has an N-type impurity region 9t-, and further has a metal layer 10t- on the N-type impurity region 9. These N-type impurity regions 9. After forming the metal layer 10, the remaining N-type semiconductor substrate 8 is covered with N.
The N-type epitaxial region 11 has a P-type epitaxial region 11, and on the surface of the N-type epitaxial region 11, there are P-type shadow regions 12 and 12"i, which become source and drain regions. The P-type head region 12, which becomes a source region, has at least They are formed at different depths than the metal layer 10. They serve as source and drain regions.

The portion of the thick field oxide film 13 between the P shadow regions 12 and 12' is once removed, and a new thin gate oxide film is formed by thermal oxidation. The field oxide film 13 is formed on the P shadow region 12 which is the source region.
An opening is provided on the mold head region 12', and a source electrode 14.
A drain electrode 15 is provided. A gate electrode 16 is provided on the gate oxide film.

In this process, the P-type head region 12, which is the source region, is formed by the metal layer l.
This metal layer lO is connected to the N-type impurity region 9 and has a vertical structure, and the source electrode 14 is connected to the P shadow region 12 . A semiconductor substrate 8 is formed through a metal layer 10 and an N-type impurity region 9 is formed into an epitaxial region 1.
1 is electrically connected to. Since this N-type impurity region 9 is formed directly under the P shadow region 12 which is a source region, it does not require any planar area required for applying a potential to the epitaxial region 11 in the semiconductor substrate 8. In the M (JS integrated circuit device) using an M (78) transistor, the source region necessary for the transistor configuration,
In addition to the gate and drain regions, there is no need for additional regions for connecting the source electrode and the semiconductor substrate or epitaxial region; therefore, it is effective in reducing the chip size of integrated circuit devices. Very large.

〔Effect of the invention〕

By implementing the present invention, a MUS transistor with a small required area can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an M(JS) transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional MUS) transistor. 1.8...N-type semiconductor substrate, 2.2', 12
゜12'...P shadow area, 3.14...
Source electrode, 4.15...Drain electrode, 5.
16...Gate electrode, 6.13...Insulating film, 7,9...N-type impurity region, lO...
...metal layer, 11...N type epitaxial region. $1 1!1 Bud 2I! 1

Claims (1)

[Claims] a first impurity region of one conductivity type on a semiconductor substrate; a metal layer on the first impurity region; and a first impurity region of one conductivity type on the metal layer, the first impurity region, and the semiconductor substrate. having source and drain regions of another conductivity type on the epitaxial region such that the source region is in contact with the metal layer, and having source and drain regions of other conductivity types on the epitaxial region between the source and drain regions. A MOS transistor characterized by having a gate insulating film and a gate electrode thereon.