JPH0364931A - Mos type semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the gate-source capacitance and to obtain an MOS type semiconductor device having high switching rate by a method wherein a metallic electrode layer is formed not entirely on the whole surface of a gate provided on the region encircling respective regions distributed on a semiconductor substrate through gate insulating films but an opening is formed at a part thereof. CONSTITUTION:Gates 6 provided on the proper region of a substrate 1 exposed between channel diffused laters 2 of respective cells and extending outside source diffused layers 3 are provided on the whole surface encircling respective cells, however metallic electrode layers 7 covering the gates 6 through the intermediary of insulating films 8 of PSG, for example, exist not entirely on the whole surface. That is, Al-Si alloy, etc., is applied on the whole surface, the film 7 is partly removed by selective etching process to form opening parts 9. Accordingly, the insulating films 8 existing beneath the openings 9 have no capacitive component thus reducing the gate-source capacitance.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a semiconductor substrate with an MO8 structure on one side for controlling the main current flowing between main electrodes provided on both sides, and is used as a switching power supply. This invention relates to a MOS type semiconductor device used.

[Conventional technology]

In order to control as large a main current as possible with an MO8 structure provided on the surface of a semiconductor substrate of limited area, the semiconductor device is divided into a plurality of parallel cells. Figure 2 (al, (
b) shows a vertical MOSFET as an example;
(al is a plan perspective view, and (b) is a sectional view taken along the line B-B of (al). In each cell, nine layers 2 as a p-channel diffusion layer are formed on the surface of an n-type silicon substrate 1. A deep p+ well diffusion layer 4 is formed in the center of the nine layers 2. A deep p+ well diffusion layer 4 is formed on the surface of the substrate. two n° layer 3
and the exposed part of the n-layer 1, which will become the drain region in the original region of the substrate, from the top of the channel diffusion layer 2 to the top of the similar channel diffusion layer 2 of the adjacent cell via the gate oxide film 5. A polycrystalline silicon gate 6 is provided. The metal electrode 8iIM7 made of, for example, U-St gold alloy, which contacts the n° layer 3 and the p′ layer 4, is common to each cell for parallel connection, as shown by diagonal lines in FIG. 2 ta+. is formed integrally with the gate 6, and a PS
An insulating film 8 made of G or the like is interposed. As schematically shown in FIG. 2, a capacitive component 11 exists in the insulating film 8 between the metal electrode film 7 and the polycrystalline St gate 6. Metal electrode film 7
Since is in contact with the source layer 3, this capacitance component 11 becomes a gate-source capacitance.

[Problem to be solved by the invention]

In order to increase the switching speed of a MOS type semiconductor device as shown in FIG. 2, it is necessary to reduce the gate-drain capacitance or the gate-source capacitance. For this purpose, the following methods have been considered in conventional MOS semiconductor devices.

(11) Reduce the cell size or channel area or thicken the gate oxide film to reduce the gate-drain capacitance.

(2) Increase the thickness of the insulating film between the gate and source to reduce the capacitance between the gate and source.

However, method (1) had a problem in that other characteristics changed. In method (2), other characteristics remain unchanged, but the problem is that it takes time to thicken the insulating film, the etching process takes a long time, and as a result, defects such as side etching are more likely to occur. was there.

An object of the present invention is to solve the above problems, reduce the gate-source capacitance without increasing the thickness of the insulating film interposed between the gate and the metal electrode film in contact with the source layer, and increase the switching speed. It is an object of the present invention to provide a MOS type semiconductor device with high speed.

[Means to solve the problem]

To achieve the above object, the present invention provides a cell region of a second conductivity type that is provided with a ring-shaped source layer of a first conductivity type on a surface layer of a semiconductor substrate of a first conductivity type, with a peripheral edge and a predetermined distance therebetween. A plurality of gates are arranged in a dispersed manner, and a gate is provided on the exposed portion of the original region of the first conductivity type substrate between each cell region, with a gate extending to above a portion outside the source layer of each cell region via a gate insulating film,
In a MOS type semiconductor device in which the metal electrode films in contact with each source layer and the inner part of the source layer of each cell region are interconnected and insulated by the gate and an insulating film, the metal electrode film is in contact with each cell region. It is assumed that an opening is provided above the gate existing on the sandwiched region.

[Effect]

Because the metal electrode film does not cover the entire surface of the gate and has an opening in a portion, the capacitance of the insulating film between the gate metal electrode film is reduced by the area of the opening, and the gate-source capacitance is small. Become.

〔Example〕

As shown in FIG. 3, the chip 20 of the vertical MOSFET, which usually has dimensions of 2 square to 9 square Wa, includes a gate band 21 for connecting the gate to the outside, and a gate band 21 for connecting the metal electrode film to the outside. A source band 22 is provided. 1at and 1(b) show a vertical MOS according to an embodiment of the present invention.
It shows a part away from the source band as shown as part A in Fig. 3 of the FET chip, Tal is a perspective plan view, and 载 is a cross-sectional view of (Ml) taken along the line A-A, which is the same as Fig. 2. The same reference numerals are given to the parts. In this case, the gate oxide film 5 is provided on the original region of the substrate 1 of approximately 20 to 40 #ll exposed between the channel diffusion layers 2 of each cell. , - The gate 6 extending to the top of the channel diffusion layer 2 on the outside of the annular source diffusion layer 3 with sides of 8 to 40 μm is provided over the entire area surrounding each cell, as in the case of FIG. However, unlike the case in FIG. 2, the metal electrode film 7 covering the top with an insulating film 8 made of PSG, for example, does not exist on the entire surface, that is, after coating the entire surface with U-31 alloy, etc. is removed by selective etching to form an opening 9. Therefore, the insulating film 8 existing under this opening 9
Since there is no capacitive component, the gate-source capacitance is reduced accordingly.

Providing the opening 9 in the metal electrode 11K7 reduces the path of current flowing through the source band 22. 1st
As shown in the figure, there is no problem in making the opening large because the current is small in the part away from the source pad, but there is not enough current path in the part close to the source pad 22, indicated by B in FIG. Figure 4(a)
, the area of the opening 9 is reduced as shown in (b).

In addition, in Fig. 4 (al is a plane perspective view, and the mountain)
is a cross-sectional view of ta+ along line CC.

The above embodiments are for n-channel vertical MOSFETs, but p-channel vertical MOSFETs, n- and p-channel wA edge gate bipolar transistors with layers of opposite conductivity type provided on the bottom side of the substrate, etc. MOS
The same method can be applied to type semiconductor devices.

〔Effect of the invention〕

According to the present invention, a metal electrode film is not formed on the entire surface of a gate provided via a gate insulating film on a region surrounding each cell region distributed on a semiconductor substrate, but an opening is formed in a part of the gate. By providing this, the capacitance component generated in the insulating film sandwiched between the gate and the metal electrode film can be reduced by about 20 to 40%, so the gate-source capacitance is reduced and an MO8 type semiconductor device with high switching speed can be obtained. did it.

[Brief explanation of drawings]

Figure 1 t8) and (b) are MOSFEs of one embodiment of the present invention.
T, (a) is a perspective plan view, To) is A- in (a)
A sectional view of the main part along line A, Fig. 2 (1111, (bl
shows a conventional vertical MOSFET, (a) is a perspective plan view, (mountain) is a sectional view of the main part along the BB line of ta+, Fig. 3 is a conceptual plan view of MO5FET chip, 4th V ! J
(a), To) shows a different position from FIG. 1 of a MOSFET according to an embodiment of the present invention, (al is a perspective plan view, Q+)
FIG. 2 is a cross-sectional view of main parts taken along line CC in FIG. 1: N-type silicon substrate, 2: Channel diffusion layer (p layer)
3: Source diffusion layer (n''-layer) 5: Gate oxide film, 6: Gate, 7: Metal electrode film, 8:'$II!1 21st!l

Claims (1)

[Claims] 1) A plurality of cell regions of a second conductivity type each having an annular source layer of the first conductivity type are distributed and arranged on the surface layer of a semiconductor substrate of the first conductivity type, with a ring-shaped source layer of the first conductivity type interposed between the periphery and a predetermined interval, and each cell region On the exposed part of the original region of the first conductivity type substrate between, there is a gate extending to the outer part of the source layer of each cell region via a gate insulating film, and a gate exists between each source layer and the source layer of each cell region. In cases where the metal electrode films that respectively contact the inner parts are connected to each other and are insulated from the gate by an insulating film, the metal electrode film has an opening above the gate located on the region sandwiched between each cell region. A MOS type semiconductor device characterized by having a portion.