JPH0427157A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a wiring pattern adapted for high integration without deteriorating the performance of a MOSFET by alternately disposing contacts and holes in source or drain regions of an insulated gate type field effect transistor (MOSFET). CONSTITUTION:Contacts 6 and holes 7 are alternately disposed on a source region 5. In this case, a current between a drain and a source does not almost alter when the contact 6 is placed on the entire region 5, and the deterioration of the characteristics of a MOSFET is prevented by a reduction in a source resistance. If a first interconnection layer 1 in which a drain region 4 is connected to the contact 6, is formed to cross the region 5 so that the contact 6 and the hole 7 are not placed on entire region 5, the contacts 6 and the holes 7 are alternately disposed on the region 5 to increase the opposed length to the contact on the region 4 as large as possible. Influence to the drain current is reduced to suppress the characteristic deterioration to the minimum limit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a gate array LSI including MOSFETs, and particularly to a high-speed, highly integrated semiconductor device. [Summary of the Invention 1 The present invention provides a gate array LSI including MOS FETs.
In the input/output cell part of the MOSFET, a contact hole (hereinafter referred to as a contact) for connecting the source or drain region of the MOSFET and the first wiring layer (hereinafter referred to as the first wiring layer) and a first wiring layer are provided. layer and the second wiring layer (
The second wiring layer, hereinafter referred to as the second wiring layer, is used as a power supply line for supplying current to the input/output cell section. ) by alternately arranging contact holes (hereinafter referred to as holes) in the source or drain region of the MOSFET to prevent deterioration of MOSFET characteristics and realize a wiring pattern suitable for miniaturization and speeding up. It is something to do. [Prior Art] A conventional semiconductor device is shown, for example, as a planar pattern in FIG. 2(a) at an input/output section of a gate array LSI. In the same figure, an N-channel MOSFET (hereinafter NMO
3) as an example, the drain region 4 is connected to the first wiring layer l through eight contacts 6. Furthermore, the source region 5 is connected to the four contacts 6.
It is connected to the wiring layer cylinder 1 and further has four holes 7.
It is connected to the wiring second layer 2 that supplies source power. 3 is the gate of NMO5. In this way, a contact 6 and a hole 7 are formed in the source region 5.
By arranging both of them, the wiring efficiency can be improved and the pattern can be made smaller, compared to placing the contact 6 over the entire source region and providing a separate wiring region for the hole 7. [Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, as shown in FIG. However, since there is no sink for the train current in the portion where the contact 6 and the hole 7 face each other, the series parasitic resistance Rs of the source region 5 makes it difficult for the current to flow. Therefore,
As the DC characteristics of NMO5 deteriorate, the series parasitic resistance R
There is a problem in that the switching speed is also slow due to the junction capacitance of the source region. Therefore, the present invention solves these problems,
The purpose is to provide a wiring pattern that allows for high integration without deteriorating the performance of MOSFETs. [Means for Solving the Problems] A semiconductor device according to the present invention is characterized in that contacts and holes are alternately arranged in the source or drain region of a MOSFET. [Example] The present invention will be described in detail below with respect to the case where A1 is used as the material of the wiring layer. FIG. 1(a) is a plan pattern diagram showing a semiconductor device according to an embodiment of the present invention. Contacts 6 and holes 7 arranged in the source region 5 are arranged alternately, and as shown in FIG. The reduction in source resistance makes the MOSFE
This can prevent the characteristics of T from deteriorating. FIG. 3 is a plan pattern diagram of a semiconductor device according to another embodiment of the present invention. The first wiring layer l, which is connected to the drain region 4 through a contact 6, crosses the source region 5, and the contact 6 and hole 7 cannot be placed over the entire surface of the source region 5. Therefore, in the source region 5, contacts 6 and holes 7 are placed alternately, and the length of the opposing contact with the contact in the drain region 4 is made as large as possible to minimize the influence on the drain current flow, as shown in FIG. 3(b). By making it small, characteristic deterioration can be minimized. The above has been described using NMO5 as an example, but P channel MO
The same applies to 3FET (PMO3). Also, although A1 is used as the wiring material in this embodiment, the same applies to other metal wiring. [Effect of the invention 1 As described above. According to the present invention, the following effects can be obtained: In a gate array including MOSFETs, MOSFETs
Contacts and holes are arranged alternately in the source or drain region of the device to prevent characteristic deterioration by reducing series parasitic resistance and junction capacitance, while increasing wiring flexibility and making it suitable for high speed and high integration. This has the effect that it is possible to realize a wiring pattern that is

[Brief explanation of drawings]

FIG. 1(a) shows a MOSFET which is an embodiment of the present invention.
FIG. FIG. 1(b) is a diagram showing the flow of current between the source and drain in FIG. 1(a). FIG. 2(a) is a plan pattern diagram of a conventional MOS FET. FIG. 2(b) is a diagram showing the flow of current between the source and drain in FIG. 2(a). FIG. 3(a) shows a MOSFET which is another embodiment of the present invention.
FIG. FIG. 3(b) is a diagram showing the flow of current between the source and drain in FIG. 3(a).・Series parasitic resistance ψ[F] of the first wiring layer, second wiring layer, gate, drain, source, contact, hole, and source region

Claims (3)

[Claims] (1) A first contact hole for electrically connecting the semiconductor substrate and the first wiring layer, and for electrically connecting the first wiring layer and the second wiring layer. A semiconductor device, wherein contact holes are alternately arranged in source regions or drain regions of insulated gate field effect transistors (MOSFETs) formed on the semiconductor substrate. (2) The insulated gate field effect transistor (MOS)
FET) is an insulated gate field effect transistor (MO
2. The semiconductor device according to claim 1, wherein the semiconductor device is included in a gate array LSI composed of SFETs. (3) The insulated gate field effect transistor (MOS)
FET) is an insulated gate field effect transistor (MO
Claim 1 characterized in that the gate array LSI includes a mixture of SFET) and bipolar transistors.
The semiconductor device described.