JPH01235275A - Mos semiconductor device - Google Patents

Abstract

PURPOSE:To make possible an increase in an integration by a method wherein the first-nth contact groups of source and drain regions and first-(n-1)th gate electrodes, each having a crank-shaped bent part and consisting of polySi, are provided, the contact groups are gradually shifted and the crank-shaped bent parts of the kth gate electrodes are positioned between the kth contact groups and the (k+1)th contact groups. CONSTITUTION:A P-MOSFET is formed using 103 and 104 as source and drain regions and using 101 and 102 as gate electrodes. Here, the gate electrodes 101 and 102 are bent between contact holes 105 of the source region 103 and a contact hole 106 of the drain region 104. As the result, the widths of the source and drain regions can be made very narrow excepting places, where the contact holes 105 and 106 are provided, of the regions 103 and 104 and the area of the MOSFET is made very small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a layout of contacts between source and drain regions and a gate electrode made of polysilicon in a semiconductor integrated circuit using a MOSFET.

[Conventional technology 1] The conventional MOS FET, as shown in the example of Fig. 4,
The source region and the drain region were rectangular.6 [Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, the area of the source region and the drain region is relatively large. Requires a large area compared to manufacturing. This poses a problem in that it is difficult to significantly improve the degree of integration of MO3 type semiconductor devices.

Therefore, the present invention is intended to solve the problems of conventional semiconductor devices, and its purpose is to achieve higher integration using MO5! The company provides semiconductor devices.

[Means for Solving the Problems] The MO5 type semiconductor device of the present invention includes: a) a semiconductor integrated circuit using a MOSFET; b) first to nfn of a source region and a drain region;
(2≦n, a natural number); C) first to (n-1) gate electrodes made of polysilicon having crank-shaped bent portions; and d) the contact groups are arranged in stages. and elk is a natural number of (1≦k≦n-1), and the crank-shaped bending of the first gate electrode is between the first contact group and the (k+1)th contact group. It is characterized by the fact that the section is located.

[Example 1] As a first example of the present invention, a P-type MO5FE is shown in FIG.
A plan view of T is shown in FIG. 2, and an equivalent circuit diagram is shown in FIG.

In FIG. 1, 101.
102 is a P-type polysilicon gate electrode, 103
．． A region 104 forms a P-type MO3FET using the gate electrodes 101 and 102 as gate electrodes.

Here, the gate electrodes 101 and 102 are bent between the contact hole 105 of the source region 103 and the contact hole 106 of the drain region 104, and as a result, the widths of the source region and the drain region are 105.
The area other than the area where the 106 contact holes are installed can be made very narrow, and the area of the MOSFET is extremely small.

Also, here, by connecting the contact hole 105 and the aluminum wiring 107 for the source electrode, and connecting the contact hole 106 and the aluminum wiring 108 for the drain electrode, a parallel connection as shown in the equivalent circuit diagram of FIG. MOS FETs can be formed in a small area.

Next, a second embodiment is shown in FIG.

In FIG. 3, a parallel connection circuit of six elements is formed in a small area using the same method as in FIG. 1.

In this way, by installing the number of gate electrodes corresponding to the device area using the method described above, a large number of MOS
FET can be formed.

Further, by changing the aluminum wirings 107 and 108, various circuits can be constructed.

Further, in FIGS. 1 and 3, the circuit using a P-type MO5FET has been described, but the same can be applied to an N-type MO3FET.

In addition, in FIGS. 1 and 3, the number of contact holes in the source fil region and drain region was one, but
this is,? This also applies to the I number.

1. Effects of the invention) As described above, 1. According to the present invention, it is possible to fabricate a large number of parallel-connected MOS FETs in a small area, especially in a small area in the lateral direction, resulting in high integration. It enables high-capacity MOS in a limited area.
This is very effective when you want to create an FET.

Furthermore, by reducing the area of the drain electrode, parasitic capacitance is reduced. This also has the effect of reducing power consumption.

Furthermore, if the parasitic resistance of the drain is smaller than the transistor resistance, there is an effect that the speed can be increased by reducing the parasitic capacitance.

[Brief explanation of the drawing]

FIG. 1 shows a P-type MO3FE showing a first embodiment of the present invention.
It is a top view of T. FIG. 2 is an equivalent circuit diagram of FIG. 1. FIG. 3 shows a P-type MOSFE according to a second embodiment of the present invention.
It is a top view of T. FIG. 4 is a plan view of a conventional P-type MO3FET. 101.102... Gate electrode 103... Source region 104... Drain region 105.106.110... Contact hole 107... Aluminum wiring for source electrode 108... Aluminum wiring for drain electrode 109. ...Aluminum wiring for gate electrodes and above Applicant: Seiko Epson Co., Ltd. Agent Patent Attorney Tsumugi Mogami (and 1 other person) No./Fig. No. 2

Claims (1)

[Claims] a) Insulated gate field effect transistor (hereinafter referred to as MOSF)
(abbreviated as ET), b) the first to nth (n
(2≦n, a natural number); c) first to (n-1) gate electrodes made of polysilicon having crank-shaped bent portions; and d) the contact groups are arranged in stages. and e) where k is a natural number (1≦k≦n-1), there is a k-th contact group between the k-th contact group and the (k+1)-th contact group.
A MOS type semiconductor device, wherein the crank-shaped bent portion of the gate electrode is located.