JPH0656878B2 - Method for manufacturing CMOS semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS semiconductor device in which a capacitor is formed in the CMOS semiconductor device.

<Prior Art> Generally, in a MOS type capacitor (capacitor), its capacitance is set by series connection of an oxide film capacitance and a depletion layer capacitance. The depletion layer capacitance changes depending on the gate voltage value. Therefore, the capacitance value cannot be kept constant. As a result, in a circuit that handles an AC signal, the operation of the transistor becomes unstable. Therefore, it is desired to operate the capacitor in the region where the depletion layer capacitance is not generated.
FIG. 5 is a graph showing the CV characteristic of the MOS capacitor.

Conventionally, a process such as an ion implantation method has been added to form a pseudo channel directly under the gate to eliminate the influence of the depletion layer.

That is, in the case of an IC including a MOS capacitor and a CMOS transistor, it has been conventionally manufactured by the following process.

FIGS. 4A to 4F are cross-sectional views in each step for explaining the method of manufacturing the CMOS semiconductor device having the conventional MOS capacitor.

First, for example, a P-type semiconductor substrate 11 is prepared as shown in FIG. Next, as shown in FIG. 3B, an N-type impurity is introduced into a predetermined region of the semiconductor substrate 11 by, for example, an ion implantation method to form an N well 13.
At this time, other regions are masked by the resist.

Next, as shown in FIG. 6C, the surface of the substrate 11 is selectively oxidized to form a field oxide film 15 on the surface, and the substrate surface is separated into a plurality of transistor formation regions. Also in this case, the mask is used.

Next, as shown in FIG. 3D, N-type impurities are introduced into a predetermined isolation region (MOS capacitor formation region) of the substrate 11 by an ion implantation method. In this case, the other area is covered with the resist. As a result, a predetermined N-type region is formed in the MOS capacitor formation region.

Next, as shown in FIG.
The insulating layer 17 and the gate electrode 19 are deposited and formed on the surface of the substrate by a predetermined mask process, and the insulating layers 27, 29, and The gate electrodes 31 and 33 are formed by using the lithography technique. Further, in the N well region 13, a P type impurity is introduced from the substrate surface by using, for example, an ion implantation method or the like to form a source region 21 and a drain region 2.
3 is formed. A P-channel type FET (field effect transistor) 25 is formed in the region 13.

Further, as shown in FIG.
N-type impurities are introduced at a high concentration in the portion excluding the well region 13. As a result, the N-channel FET 35 and the MOS capacitor 37 are formed on the P-type semiconductor substrate 11.

<Problems to be Solved by the Invention> However, in such a conventional method for manufacturing a semiconductor device, a depletion mask is required for forming a MOS capacitor in addition to the normal MOS transistor forming step. The cost of the mask was high and the unit price of the wafer was high. Therefore, the chip cost is also high.

<Means for Solving the Problem> The present invention provides a step of forming wells of the second conductivity type at a plurality of locations on a semiconductor substrate of the first conductivity type, and a step of forming the second conductivity type on the semiconductor substrate of the first conductivity type. While introducing impurities to form a field effect transistor having a second conductivity type channel,
Forming a capacitor in one of the second conductivity type wells, and introducing an impurity of the first conductivity type into one of the remaining wells of the second conductivity type And a step of forming a field-effect transistor having a channel of 1., and a method of manufacturing a CMOS semiconductor device.

<Operation> In the method of manufacturing the semiconductor device according to the present invention, the MOS transistors of opposite conductivity types are arranged in parallel on the substrate and the capacitor is arranged.

<Example> Hereinafter, a first example of a CMOS semiconductor device according to the present invention will be described with reference to the drawings.

1 (a) to (f) show an M according to the first embodiment of the present invention.
6A to 6C are cross-sectional views in each step for explaining the method of manufacturing the CMOS semiconductor device having the OS capacitor.

First, for example, a P-type semiconductor substrate 111 is prepared as shown in FIG.

Next, as shown in FIG.
Two N wells 113 and 115 are formed at the same time by introducing an N type impurity into the predetermined two regions by ion implantation, for example. At this time, regions other than these are masked by the resist.

Next, as shown in FIG. 1C, the surface of the substrate 111 is selectively oxidized to form a field oxide film 117 on the surface, and the substrate surface is formed into a plurality of transistor formation regions 1.
13 and 119 and the MOS capacitor formation region 115 are separated. Also in this case, the mask is used.

Next, as shown in FIG.
1, 133 and gate electrodes 123, 135, 137 are deposited and formed by a predetermined mask process. Further, in the N well region 113, a mask is used from the substrate surface by, for example, an ion implantation method (other regions 115,
119) to introduce a P-type impurity,
5 and the drain region 127 are formed. A P-channel FET (field effect transistor) 129 is formed in the region 1
13 is formed.

Further, as shown in FIG. 7E, another isolation region of the substrate 111 (MOS capacitor formation region 115 and NFET
In the formation region 119), using a mask (PFET
A high concentration of N-type impurities is introduced into a predetermined portion in a self-aligned manner (covering 129). Thereby, the P-type semiconductor substrate 1
Predetermined areas 119 and 115 on 11 respectively have N
The channel type FET 139 and the MOS type capacitor 141 are formed.

As a result, the P-channel FET 129, the N-channel FET 139 and the MOS are formed on the semiconductor substrate 111.
The type capacitor 141 is formed. The order of the steps shown in (d) and (e) may be reversed.

Next, FIGS. 2 (a) to (e) show the second part of the manufacturing method of the present invention.
An example is shown.

In this embodiment, CMOS and MOS type capacitors are formed on an N type semiconductor substrate 211.

That is, in FIG. 2A, the N-type semiconductor substrate 2
Prepare 11. Next, as shown in FIG. 7B, P-type impurities are introduced into the two regions of the substrate 211 by an ion implantation method using a mask to form P wells 213 and 215.

Next, as shown in FIG.
7 is formed on the surface of the substrate 211 so that the substrate surface is a region 21.
It is separated into 3, 219 and 215.

Next, as shown in FIG.
1, 233 and gate electrodes 223, 235, 237 are deposited and formed. Further, in the P well region 213, an N type impurity is introduced from the substrate surface by an ion implantation method to form a source and a drain. Other areas 215, 21
9 is masked. The N-channel FET (field effect transistor) 225 is formed.

Further, as shown in FIG. 7E, P-type impurities are also introduced into other isolation regions of the substrate 211. As a result, the P-channel FET 227 and the MOS capacitor 229 are formed on the N-screen substrate 211.

FIG. 3 is a sectional view for explaining a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

That is, in this embodiment, M of the first embodiment described above is used.
In the process of forming the OS type capacitor, its gate electrode 3
After forming 01, a predetermined opening 303 is formed in this. After forming the opening, the N well 305 is also ion-implanted through the opening 303.

As a result, when one wide gate electrode 301 is formed, N-type impurities are implanted into the N well 305 at the predetermined position 303. In the figure, 307 is a field oxide film, 309 is aluminum wiring, and 31 is
Reference numeral 1 is an insulating layer.

As described above, in this embodiment, M having a large capacity is used.
The OS type capacitor is divided into small parts. As a result,
Carriers easily move, stable capacitance is obtained, and internal resistance can be reduced.

<Effect> As described above, according to the present invention, a depletion mask for forming a well and a mask for preventing an inversion layer of a capacitor can be used in common, and any depletion mask is unnecessary. , The mask cost can be reduced. Further, since the depletion process is reduced, it is possible to reduce the number of process days by reducing the process. Further, since the depletion process is eliminated, the wafer unit cost and the chip cost can be reduced.
In addition, by the capacitor of this structure, the majority carrier of the substrate,
Since it is used in a state of being stored, it can be used in a state where the capacitance value is MAX, and as a result, a stable capacitance value can be obtained in a circuit handling an AC signal.

[Brief description of drawings]

1 (a) to 1 (e) are sectional views showing respective steps according to the first embodiment of the method for manufacturing a semiconductor device of the present invention, and FIGS. 2 (a) to 2 (e) are semiconductor devices of the present invention. Second manufacturing method
Cross-sectional views showing respective steps according to the embodiment, FIG. 3 is a vertical cross-sectional view of a semiconductor device formed by the method of the present invention, and FIGS. 4 (a) to (f) are related to conventional semiconductor device manufacturing methods. FIG. 5 is a longitudinal sectional view showing the process, and FIG. 5 is a graph showing the CV characteristic of the MOS capacitor. 111 ... P-type semiconductor substrate, 113, 115 ... N-type well, 129 ... P-type FET, 139 ... N-type FET, 141 ... MOS-type capacitor.

Claims (1)

[Claims] 1. A plurality of second conductivity type semiconductor substrates are provided at a plurality of locations on the semiconductor substrate.
The step of forming a conductivity type well and the step of introducing a second conductivity type impurity into the first conductivity type semiconductor substrate to form a field effect transistor having a second conductivity type channel, while the second conductivity Forming a capacitor in one of the wells of the second conductivity type, and introducing an impurity of the first conductivity type into one of the remaining wells of the second conductivity type to form a channel of the first conductivity type. And a step of forming a field-effect transistor having the same.