JPH08102526A - Cmos semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a CMOS semiconductor device incorporating a capacitor element having low inner resistance and good characteristics through a simple fabrication method by implanting impurities of second conductivity type into at least one well of second conductivity type simultaneously with formation of MOS transistor thereby forming a capacitor region. CONSTITUTION: The CMOS semiconductor device comprises wells 113, 115 of second conductivity type formed at a plurality of points on a semiconductor substrate 111 of first conductivity type, and a transistor 139 of second conductivity type formed on the semiconductor substrate 111. The CMOS semiconductor device further comprises a capacitor region formed by introducing impurities of second conductivity type into at least one well 115 simultaneously with formation of the transistor 139, and a capacitor 141 formed between the capacitor region and a gate electrode 137 provided above the capacitor region through an insulation layer 133. The capacitor 141 is provided with an opening at a part of the gate electrode 137 and impurities of second conductivity type are introduced into the capacitor region exposed at the periphery and the opening of the gate electrode 137.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a CMOS semiconductor device having a built-in capacitor.

[0002]

2. Description of the Related Art Generally, in a MOS type capacitor (capacitor), its capacitance is set by connecting an oxide film capacitance and a depletion layer capacitance in series. The depletion layer capacitance changes with the gate voltage value. Therefore, the capacitance value cannot be kept constant. As a result, in a circuit that handles an AC signal, the operation of the transistor becomes unstable. Therefore, it is desired to operate the capacitor in the region where the depletion layer capacitance is not generated.

FIG. 5 is a graph showing the CV characteristic of a MOS capacitor. Conventionally, a process such as an ion implantation method has been added to form a pseudo channel directly under the gate to eliminate the influence of the depletion layer. That is, a MOS capacitor,
In the case of an IC having a CMOS transistor, it has been conventionally manufactured by the following process.

FIGS. 4 (a) to 4 (f) are sectional views showing respective steps for explaining a conventional method for manufacturing a COMS semiconductor device having a MOS type capacitor. First, for example, a P-type semiconductor substrate 11 is prepared as shown in FIG. Next, as shown in FIG. 3B, an N-type impurity is introduced into a predetermined region of the semiconductor substrate 11 by, for example, an ion implantation method to form an N well 13. At this time, other regions are masked by the resist.

Next, as shown in FIG. 1C, the surface of the semiconductor substrate 11 is selectively oxidized to form a field oxide film 15 on the surface, and the substrate surface is formed into a plurality of transistor forming regions. To separate. Also in this case, the mask is used. Next, as shown in FIG.
N-type impurities are introduced into the predetermined isolation region 1 (MOS capacitor forming region) by the ion implantation method. In this case, the other area is covered with the resist. As a result, the MO
A predetermined N-type region is formed in the S capacitor formation region.

Next, as shown in FIG. 2E, the insulating layer 17 and the gate electrode 1 are formed on the surface of the N well region 13.
9 is deposited and formed by a predetermined mask process, and the insulating layer 2 is formed in each of the other isolation regions (MOS capacitor formation region and NFET formation region) of the semiconductor substrate 11.
7, 29 and the gate electrodes 31, 33 are formed by using the lithography technique. Further, in the N well region 13, a P type impurity is introduced from the surface of the substrate by using, for example, an ion implantation method using a mask to form a source region 21 and a drain region 23.
The (field effect transistor) 25 is formed in the region 13.

Further, as shown in FIG. 1F, a high concentration of N-type impurities is introduced into the portion excluding the N well region 13 using a mask. Thereby, the P-type semiconductor substrate 11
The N-channel FET 35 and the MOS capacitor 37 are formed on the top.

[0008]

However, in such a conventional method for manufacturing a semiconductor device, a depletion mask is required for forming a MOS capacitor in addition to the normal MOS transistor forming step. The cost of the mask was high and the unit price of the wafer was high. Therefore, the chip cost is also high.

An object of the present invention is to provide a CMOS semiconductor device having a built-in capacitive element having a small internal resistance and excellent characteristics by a simple manufacturing method.

[0010]

In order to solve the above-mentioned problems, the present invention provides a second conductivity type well formed at a plurality of locations of a first conductivity type semiconductor substrate, and a first conductivity type semiconductor substrate. And a capacitor region formed by introducing impurities of the second conductivity type into the well of the second conductivity type at the same time when the MOS transistor is formed in at least one of the wells of the second conductivity type. A gate electrode provided on the upper part of the capacitor via an insulating layer; and a capacitor having a capacitor formed between the capacitor region and the gate electrode.
In the MOS semiconductor device, an opening is provided in a part of a gate electrode of a capacitor, and a second conductivity type impurity is introduced into the periphery of the gate electrode and a capacitor region exposed in the opening.
A second conductive type impurity region around the gate electrode and the opening is connected by a metal wiring.

[0011]

A first embodiment of a CMOS type semiconductor device according to the present invention will be described with reference to the drawings. 1 (a) to 1 (f) are sectional views in each step for explaining a method of manufacturing a CMOS semiconductor device having a MOS capacitor according to the first embodiment of the present invention.

First, as shown in FIG.
A mold semiconductor substrate 111 is prepared. Next, as shown in FIG. 3B, N-type impurities are introduced into the predetermined two regions of the semiconductor substrate 111 by, for example, an ion implantation method to obtain 2
Two N wells 113 and 115 are formed at the same time. At this time, regions other than these are masked by the resist.

Next, as shown in FIG. 1C, the surface of the semiconductor substrate 111 is selectively oxidized to form a field oxide film 117 on the surface, and the surface of the semiconductor substrate is formed into a plurality of transistor forming regions. 113 and 119 and a MOS capacitor formation region 115 are separated. Also in this case, the mask is used. Next, as shown in FIG. 3D, the insulating layers 121, 131 and 133, and the gate electrodes 123 and 13 are formed.
5, 137 are deposited and formed by a predetermined mask process. Further, in the N well region 113, a P-type impurity is introduced from the surface of the semiconductor substrate using a mask (covering other regions 115 and 119) by, for example, an ion implantation method or the like to form a source region 125 and a drain region 127. Then, a P-channel FET (field effect transistor) 129 is formed in the region 113.

Further, as shown in FIG. 1E, another isolation region (MOS capacitor forming region 1) of the semiconductor substrate 111 is formed.
15 and NFET formation region 119), N type impurities are introduced in a high concentration in a self-aligned manner at a predetermined portion using a mask (covering PFET 129). As a result, N-channel FETs 139 and M are formed in predetermined regions 119 and 115 on the P-type semiconductor substrate 111, respectively.
The OS capacitor 141 is formed.

As a result, the P-channel FET 129 and the N-channel FET 139 are formed on the semiconductor substrate 111.
And the MOS type capacitor 141 is formed. The order of the steps shown in (d) and (e) may be reversed. Next, FIGS. 2 (a) to (f) show the second embodiment of the present invention.
6A to 6C are cross-sectional views in each step for explaining the method for manufacturing the CMOS semiconductor device according to the example. In this embodiment, CMOS and MOS type capacitors are formed on an N type semiconductor substrate 211.

That is, in FIG. 2A, an N type semiconductor substrate 211 is prepared. Next, as shown in FIG. 6B, P-type impurities are introduced into two regions of the semiconductor substrate 211 by an ion implantation method using a mask to form P wells 213 and 215. Next, as shown in FIG. 3C, the field oxide film 217 is formed on the semiconductor substrate 211.
On the surface of the semiconductor substrate to form the semiconductor substrate surface in the regions 213 and 21.
9 and 215 are separated.

Next, as shown in FIG. 3D, the insulating layer 2
21, 231, 233, gate electrodes 223, 235, 2
37 is deposited and formed. Further, this P well region 21
3 from the surface of the semiconductor substrate by ion implantation or the like
A source and a drain are formed by introducing a type impurity to form an N-channel FET (field effect transistor) 225. The other areas 215 and 219 are masked.

Further, as shown in FIG. 3E, P-type impurities are also introduced into other isolation regions of the semiconductor substrate 211. As a result, the P-channel FET 227 and the MOS capacitor 229 are formed on the N-type semiconductor substrate 211. FIG. 3 shows the CO according to the third embodiment of the present invention.
7A to 7C are cross-sectional views for explaining the method for manufacturing the MS semiconductor device. That is, in this embodiment, the first
In the step of forming the MOS type capacitor of the embodiment, after forming the gate electrode 301, a predetermined opening 303 is formed therein. After the opening is formed, the N well 305 is also ion-implanted through the opening 303. As a result, when one wide gate electrode 301 is formed, N-type impurities are also implanted into the N well 305 at the predetermined position 303. In the figure, 307 is a field oxide film, 309 is an aluminum wiring, and 301 is an insulating layer.

The opening 303 may be shaped so as to be surrounded by the gate electrode 301, or may be shaped so as to communicate with a peripheral N-type impurity region by a notch provided in a part of the opening 303. As described above, in this embodiment, the MOS type capacitor having a large capacity is divided into small parts. As a result, carriers easily move, stable capacitance can be obtained, and internal resistance can be reduced.

[0020]

As described above, according to the present invention, the depletion mask for forming the well and the mask for preventing the inversion layer of the capacitor can be used in common, and any depletion mask is unnecessary. Therefore, the mask cost can be reduced. Further, since the depletion process is reduced, it is possible to reduce the process schedule due to the reduction of the process. Further, since the depletion process is eliminated, the unit cost of the wafer and the chip cost can be reduced. Further, since the capacitor of this structure is used in a state where the majority carriers of the semiconductor substrate are accumulated, it can be used in the condition that the capacitance value is MAX and the internal resistance of the capacitor can be reduced. A stable capacitance value can be obtained in a circuit handling.

[Brief description of drawings]

FIG. 1 is a sectional view of a pellet in each manufacturing process of a CMOS semiconductor device according to a first embodiment of the present invention,

FIG. 2 is a sectional view of a pellet in each manufacturing process of a CMOS semiconductor device according to a second embodiment of the present invention,

FIG. 3 is a sectional view of a CMOS semiconductor device of the present invention,

FIG. 4 is a sectional view of a pellet in each manufacturing process of a conventional CMOS semiconductor device,

FIG. 5 is a graph showing CV characteristics of a MOS capacitor.

[Description of Reference Signs] 111: P-type semiconductor substrate 113, 115: N-type well 129: P-type FET 139: N-type FET 141: MOS-type capacitor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display area H01L 27/092 29/94 C

Claims (1)

[Claims] 1. A well of a second conductivity type formed at a plurality of locations on a semiconductor substrate of a first conductivity type, a MOS transistor of a second conductivity type formed on the semiconductor substrate of a first conductivity type, and a second transistor. The M in at least one of the conductivity type wells
A capacitor region formed by introducing an impurity of the second conductivity type at the same time when the OS transistor is formed, and a gate electrode provided above the capacitor region with an insulating layer interposed therebetween.
In a CMOS semiconductor device having a capacitor formed between the capacitor region and the gate electrode, the capacitor has an opening in a part of the gate electrode, and the periphery of the gate electrode. And a second conductivity type impurity is introduced into the capacitor region exposed in the opening, and the periphery of the gate electrode and the second conductivity type impurity region in the opening are connected by metal wiring. CMOS semiconductor device.