JPH04164371A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH04164371A JPH04164371A JP29157390A JP29157390A JPH04164371A JP H04164371 A JPH04164371 A JP H04164371A JP 29157390 A JP29157390 A JP 29157390A JP 29157390 A JP29157390 A JP 29157390A JP H04164371 A JPH04164371 A JP H04164371A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion region
- region
- gate
- gate electrodes
- channel width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 238000005452 bending Methods 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000010354 integration Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits.
LSIの製造技術の進歩により、半導体集積回路の設計
仕様も急激に変化しつつある。高集積化及び動作速度を
含めた性能の向上のため、トランジスタの小型化が進み
、それに伴いMOSトランジスタのゲート長(L)とチ
ャネル幅(W)の減少でゲートアレイの基本セルのサイ
ズが小さくなっている。従来のCMOSゲートアレイの
基本セルは第5図に示すようにいくつかのpMoSトラ
ンジスタ及びn M OS トランジスタから成り、1
対のトランジスタで1つのゲート電極を共有している。With advances in LSI manufacturing technology, design specifications for semiconductor integrated circuits are also rapidly changing. Transistors are becoming smaller due to higher integration and improved performance including operating speed, and as a result, the gate length (L) and channel width (W) of MOS transistors are reduced, resulting in a smaller basic cell size for gate arrays. It has become. The basic cell of a conventional CMOS gate array consists of several pMoS transistors and nMOS transistors, as shown in FIG.
A pair of transistors share one gate electrode.
P形シリコン基板1上にNウェル領域2が形成され、そ
の中にP+拡散領域5が存在し、Nウェル領域2の外に
N+拡散領域6が存在し、その両方の上にゲート電極G
l、G2がある。An N well region 2 is formed on a P type silicon substrate 1, a P+ diffusion region 5 exists within the N well region 2, an N+ diffusion region 6 exists outside the N well region 2, and a gate electrode G is formed on both of them.
There are l and G2.
また、例えば、特開昭58−66343に示されるよう
な高集積度化を計った基本セルも用いられている。第4
図にその例を示す。第4図において、コンタクトホール
9,10.11付近でゲート電極を屈折せしめることで
、セル周辺部でのゲート電極Gl、G2のピッチを小さ
くし、最小のシステム配線ピッチに合わせるようにして
いる。Furthermore, a basic cell with a high degree of integration as shown in, for example, Japanese Unexamined Patent Publication No. 58-66343 is also used. Fourth
An example is shown in the figure. In FIG. 4, by bending the gate electrodes near the contact holes 9, 10, 11, the pitch of the gate electrodes G1, G2 at the cell periphery is made small, so as to match the minimum system wiring pitch.
従来の基本セル、例えば第5図に示すような基本セルで
は、ゲート電極が棒状のため、一定の面積においてチャ
ネル幅Wを増やし動作速度を向上させることができない
。さらに、高集積化による基本セル面積の減少でチャネ
ル幅Wも減少するという問題点があった。In a conventional basic cell, for example, the basic cell shown in FIG. 5, the gate electrode is rod-shaped, so it is not possible to increase the channel width W within a certain area and improve the operating speed. Furthermore, there is a problem in that the channel width W also decreases as the basic cell area decreases due to higher integration.
そのため、第4図に示すように基本セル内でゲート電極
を曲げる事によってチャネル幅Wを増やすものもあるが
、第4図のゲート電極は斜めに曲がっているだけである
のでチャネル幅Wを十分大きくすることができず、その
上P+及びN+拡散領域に対してゲート電極Gl、G2
が斜めに存在することでコンタクトホールを設ける四角
形の面積を確保しにくいという問題点があった。For this reason, as shown in Figure 4, some devices increase the channel width W by bending the gate electrode within the basic cell, but since the gate electrode in Figure 4 is only bent diagonally, the channel width W can be increased sufficiently. Furthermore, the gate electrodes Gl and G2 cannot be made large for the P+ and N+ diffusion regions.
There was a problem in that it was difficult to secure a rectangular area in which to provide a contact hole because the contact hole was present diagonally.
本発明の半導体集積回路は、半導体基板上にゲート絶縁
膜を介して設けられたゲート電極の形状が直角に複数回
曲がっているMOSトランジスタを有している。The semiconductor integrated circuit of the present invention includes a MOS transistor in which the shape of a gate electrode provided on a semiconductor substrate via a gate insulating film is bent multiple times at right angles.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例におけるCMOSゲートアレ
イの基本セルの平面図であり、この基本セルはpMOS
トランジスタとnMOSトランジスタの各2個より構成
されている。FIG. 1 is a plan view of a basic cell of a CMOS gate array in one embodiment of the present invention, and this basic cell is a pMOS
It is composed of two transistors and two nMOS transistors.
P形シリコン基板1において、Nウェル領域2の中にP
+拡散領域5と、ゲート絶縁膜を介して設けられた2本
のゲート電極Gl、G2とを有するpMO5トランジス
タ領域3を構成している。In the P-type silicon substrate 1, P is formed in the N-well region 2.
It constitutes a pMO5 transistor region 3 having a + diffusion region 5 and two gate electrodes Gl and G2 provided via a gate insulating film.
同様に、N1拡散領域6と、ゲート絶縁膜を介して設け
られた2本のゲート電極とでnMOSトランジスタ領域
4を構成している。ゲート電極Gl、G2はP+拡散領
域5及びN+拡散領域6上で直角に曲げることでチャネ
ル幅を増やす事ができ、その結果第4図及び第5図に示
した従来の基本セルに比べて、負荷駆動能力及び動作速
度を向上させることができる。Similarly, the N1 diffusion region 6 and two gate electrodes provided via a gate insulating film constitute the nMOS transistor region 4. By bending the gate electrodes Gl and G2 at right angles on the P+ diffusion region 5 and the N+ diffusion region 6, the channel width can be increased, as compared to the conventional basic cell shown in FIGS. 4 and 5. Load driving ability and operating speed can be improved.
第2図は第1図に電源ライン7、GNDライン8、コン
タクトホール9.10,11,12゜13を加えたもの
であるが、ゲート電極を適当な場所で直角に曲げること
で、コンタクトホール10を配置する場所を確保するこ
とができる。Figure 2 shows Figure 1 with the power supply line 7, GND line 8, and contact holes 9, 10, 11, 12°13 added, but by bending the gate electrode at right angles at appropriate places, the contact holes can be made. 10 can be placed.
第3図はゲート電極Gl、G2を、第1図に比べてより
多く直角に曲げたもの−で、基本セルの負荷駆動能力及
び動作速度をより一層向上させている。In FIG. 3, the gate electrodes Gl and G2 are bent more at right angles than in FIG. 1, thereby further improving the load driving ability and operating speed of the basic cell.
以上説明したように本発明は、ゲート電極を直角に複数
回曲げることで、基本セルサイズを大きくすることなく
、チャネル幅を増加させ、コンタクトホールを配置する
場所を確保でき回路設計の自由度を向上させ有効的な大
規模集積化がなされる効果を有する。As explained above, by bending the gate electrode multiple times at right angles, the present invention increases the channel width without increasing the basic cell size, secures a place for placing the contact hole, and increases the degree of freedom in circuit design. This has the effect of improving and effective large-scale integration.
第1図は本発明の一実施例による半導体チップ上の基本
セルを示す平面図、第2図は、第1図の基本セルにコン
タクトホール、電源ライン、GNDラインを設けたもの
を示す平面図、第3図は一実施例の変形を示す平面図、
第4図及び第5図はそれぞれ従来例の基本セルを示す平
面図である。
1・・・P型シリコン基板、2・・・Nウェル領域、3
・・・pMOSトランジスタ領域、4・・・nMOSト
ランジスタ領域、5・・・P+拡散領域、6・・・N+
拡散領域、7・・・電源ライン、8・・・GNDライン
、9〜13・・・コンタクトホール、Gl、G2・・・
ゲート電極。FIG. 1 is a plan view showing a basic cell on a semiconductor chip according to an embodiment of the present invention, and FIG. 2 is a plan view showing the basic cell of FIG. 1 provided with a contact hole, a power supply line, and a GND line. , FIG. 3 is a plan view showing a modification of one embodiment,
FIGS. 4 and 5 are plan views showing conventional basic cells, respectively. 1...P type silicon substrate, 2...N well region, 3
...pMOS transistor region, 4...nMOS transistor region, 5...P+ diffusion region, 6...N+
Diffusion region, 7... Power supply line, 8... GND line, 9-13... Contact hole, Gl, G2...
gate electrode.
Claims (1)
ト電極の形状が直角に複数回曲がっているMOSトラン
ジスタを有していることを特徴とする半導体集積回路。1. A semiconductor integrated circuit comprising a MOS transistor having a gate electrode provided on a semiconductor substrate with a gate insulating film interposed therebetween, the shape of which is bent multiple times at right angles.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29157390A JPH04164371A (en) | 1990-10-29 | 1990-10-29 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29157390A JPH04164371A (en) | 1990-10-29 | 1990-10-29 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04164371A true JPH04164371A (en) | 1992-06-10 |
Family
ID=17770675
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29157390A Pending JPH04164371A (en) | 1990-10-29 | 1990-10-29 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04164371A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6246080B1 (en) | 1998-05-14 | 2001-06-12 | Nec Corporation | Semiconductor device having bent gate electrode and process for production thereof |
US6842886B2 (en) | 2002-05-31 | 2005-01-11 | Oki Electric Industry Co., Ltd. | Basic cell of gate array semiconductor device, gate array semiconductor device, and layout method for gate array semiconductor device |
KR100498426B1 (en) * | 1998-02-12 | 2006-04-21 | 삼성전자주식회사 | Transistor of sense amlifier in semiconductor memory device |
KR100855843B1 (en) * | 2002-06-29 | 2008-09-01 | 주식회사 하이닉스반도체 | Layout pattern of bit line sense amplifier |
JP2009141379A (en) * | 2009-01-21 | 2009-06-25 | Renesas Technology Corp | Switching element, and antenna switch circuit and high-frequency module using the same |
DE102005046777B4 (en) * | 2005-09-29 | 2013-10-17 | Altis Semiconductor | Semiconductor memory device |
-
1990
- 1990-10-29 JP JP29157390A patent/JPH04164371A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100498426B1 (en) * | 1998-02-12 | 2006-04-21 | 삼성전자주식회사 | Transistor of sense amlifier in semiconductor memory device |
US6246080B1 (en) | 1998-05-14 | 2001-06-12 | Nec Corporation | Semiconductor device having bent gate electrode and process for production thereof |
US6387760B2 (en) | 1998-05-14 | 2002-05-14 | Nec Corporation | Method for making semiconductor device having bent gate electrode |
US6842886B2 (en) | 2002-05-31 | 2005-01-11 | Oki Electric Industry Co., Ltd. | Basic cell of gate array semiconductor device, gate array semiconductor device, and layout method for gate array semiconductor device |
KR100855843B1 (en) * | 2002-06-29 | 2008-09-01 | 주식회사 하이닉스반도체 | Layout pattern of bit line sense amplifier |
DE102005046777B4 (en) * | 2005-09-29 | 2013-10-17 | Altis Semiconductor | Semiconductor memory device |
JP2009141379A (en) * | 2009-01-21 | 2009-06-25 | Renesas Technology Corp | Switching element, and antenna switch circuit and high-frequency module using the same |
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