JPH04164371A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase channel width without increasing basic cell size, ensure a place for arranging a contact hole, and improve the freedom of circuit design, by bending gate electrodes a plurality of times. CONSTITUTION:In an N well region 2 of a P-type silicon substrate 1, a P<+> diffusion region 5, two gate electrodes G1, G2 arranged via a gate insulating film constitute a pMOS transistor region 3. In the same manner, an N<+> diffusion region 6 and two gate electrodes arranged via a gate insulating film constitute an nMOS transistor region 4. By perpendicularly bending the electrodes G1, G2 on the P<+> diffusion region 5 and the N<+> diffusion region 6, channel width can be increased, so that load driving capacity and operating speed can be improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits.

[Conventional technology]

With advances in LSI manufacturing technology, design specifications for semiconductor integrated circuits are also rapidly changing. Transistors are becoming smaller due to higher integration and improved performance including operating speed, and as a result, the gate length (L) and channel width (W) of MOS transistors are reduced, resulting in a smaller basic cell size for gate arrays. It has become. The basic cell of a conventional CMOS gate array consists of several pMoS transistors and nMOS transistors, as shown in FIG.
A pair of transistors share one gate electrode.

An N well region 2 is formed on a P type silicon substrate 1, a P+ diffusion region 5 exists within the N well region 2, an N+ diffusion region 6 exists outside the N well region 2, and a gate electrode G is formed on both of them.
There are l and G2.

Furthermore, a basic cell with a high degree of integration as shown in, for example, Japanese Unexamined Patent Publication No. 58-66343 is also used. Fourth
An example is shown in the figure. In FIG. 4, by bending the gate electrodes near the contact holes 9, 10, 11, the pitch of the gate electrodes G1, G2 at the cell periphery is made small, so as to match the minimum system wiring pitch.

[Problem to be solved by the invention]

In a conventional basic cell, for example, the basic cell shown in FIG. 5, the gate electrode is rod-shaped, so it is not possible to increase the channel width W within a certain area and improve the operating speed. Furthermore, there is a problem in that the channel width W also decreases as the basic cell area decreases due to higher integration.

For this reason, as shown in Figure 4, some devices increase the channel width W by bending the gate electrode within the basic cell, but since the gate electrode in Figure 4 is only bent diagonally, the channel width W can be increased sufficiently. Furthermore, the gate electrodes Gl and G2 cannot be made large for the P+ and N+ diffusion regions.
There was a problem in that it was difficult to secure a rectangular area in which to provide a contact hole because the contact hole was present diagonally.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a MOS transistor in which the shape of a gate electrode provided on a semiconductor substrate via a gate insulating film is bent multiple times at right angles.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a basic cell of a CMOS gate array in one embodiment of the present invention, and this basic cell is a pMOS
It is composed of two transistors and two nMOS transistors.

In the P-type silicon substrate 1, P is formed in the N-well region 2.
It constitutes a pMO5 transistor region 3 having a + diffusion region 5 and two gate electrodes Gl and G2 provided via a gate insulating film.

Similarly, the N1 diffusion region 6 and two gate electrodes provided via a gate insulating film constitute the nMOS transistor region 4. By bending the gate electrodes Gl and G2 at right angles on the P+ diffusion region 5 and the N+ diffusion region 6, the channel width can be increased, as compared to the conventional basic cell shown in FIGS. 4 and 5. Load driving ability and operating speed can be improved.

Figure 2 shows Figure 1 with the power supply line 7, GND line 8, and contact holes 9, 10, 11, 12°13 added, but by bending the gate electrode at right angles at appropriate places, the contact holes can be made. 10 can be placed.

In FIG. 3, the gate electrodes Gl and G2 are bent more at right angles than in FIG. 1, thereby further improving the load driving ability and operating speed of the basic cell.

〔Effect of the invention〕

As explained above, by bending the gate electrode multiple times at right angles, the present invention increases the channel width without increasing the basic cell size, secures a place for placing the contact hole, and increases the degree of freedom in circuit design. This has the effect of improving and effective large-scale integration.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a basic cell on a semiconductor chip according to an embodiment of the present invention, and FIG. 2 is a plan view showing the basic cell of FIG. 1 provided with a contact hole, a power supply line, and a GND line. , FIG. 3 is a plan view showing a modification of one embodiment,
FIGS. 4 and 5 are plan views showing conventional basic cells, respectively. 1...P type silicon substrate, 2...N well region, 3
...pMOS transistor region, 4...nMOS transistor region, 5...P+ diffusion region, 6...N+
Diffusion region, 7... Power supply line, 8... GND line, 9-13... Contact hole, Gl, G2...
gate electrode.

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising a MOS transistor having a gate electrode provided on a semiconductor substrate with a gate insulating film interposed therebetween, the shape of which is bent multiple times at right angles.