JPH0350767A - Bipolar cmos gate array semiconductor device - Google Patents
Bipolar cmos gate array semiconductor deviceInfo
- Publication number
- JPH0350767A JPH0350767A JP18670289A JP18670289A JPH0350767A JP H0350767 A JPH0350767 A JP H0350767A JP 18670289 A JP18670289 A JP 18670289A JP 18670289 A JP18670289 A JP 18670289A JP H0350767 A JPH0350767 A JP H0350767A
- Authority
- JP
- Japan
- Prior art keywords
- type
- mosfets
- bipolar
- gate array
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 230000002708 enhancing effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 12
- 230000000295 complement effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はバイポーラＣＭＯＳゲートアレイ半導体装置に
関し、特に同一基板上にバイポーラトランジスタと相補
型ＭＯＳ Ｆ ＥＴを含む基本内部セルを備えたバイポ
ーラＣＭＯＳゲートアレイ半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar CMOS gate array semiconductor device, and more particularly to a bipolar CMOS gate array having basic internal cells including bipolar transistors and complementary MOS FETs on the same substrate. Related to semiconductor devices.
従来、この種のバイポーラＣＭＯＳゲートアレイ半導体
装置は、内部回路においてバイポーラトランジスタを２
個使ったトーテムポール型の出力段を形成することが多
いために、１つの基本内部セル内に最低２個のバイポー
ラトランジスタを含んでいた。このためバイポーラトラ
ンジスタの使用効率を上げるために、２個１組のバイポ
ーラトランジスタに対して、Ｐ型とＮ型のＭＯＳＦＥＴ
の組を最低でも３組あるいは４組含んでいた。Conventionally, this type of bipolar CMOS gate array semiconductor device has two bipolar transistors in its internal circuit.
In order to often form a totem-pole type output stage using two bipolar transistors, one basic internal cell contained at least two bipolar transistors. Therefore, in order to increase the usage efficiency of bipolar transistors, P-type and N-type MOSFETs are used for each pair of bipolar transistors.
It included at least three or four pairs.
ここで、ＭＯＳＦＥＴの使用効率を上げるために、Ｐ型
、Ｎ型のＭＯＳＦＥＴの組の数を減らすと逆に今度はバ
イポーラトランジスタの未使用となる割合が増え、この
ため現状の方式ではバイポーラ出力段１に対し、ＭＯＳ
ＦＥＴの組の数は３〜４が最適となる。In order to increase MOSFET usage efficiency, if the number of pairs of P-type and N-type MOSFETs is reduced, the proportion of unused bipolar transistors increases, and for this reason, in the current system, the bipolar output stage 1, MOS
The optimum number of FET pairs is 3 to 4.
上述した従来のバイポーラＣＭＯＳゲートアレイ半導体
装置は、基本内部セル内に１．バイポーラトランジスタ
を２個１組とＰ型及びＮ型のＭＯＳＦＥＴを３〜４組と
を備えた構成となっているので、実際の機能回路を形成
した場合、特にひんばんに使用されるインバータや２人
カゲート回路等のブロックを形成する際に、使用しない
ＭＯＳＦＥＴが多くなり、−殻内には素子使用率からみ
ても、ＣＭＯＳゲートアレイに比べると集積度が低くな
るという欠点がある。The conventional bipolar CMOS gate array semiconductor device described above has 1. It has a configuration that includes one set of two bipolar transistors and three to four sets of P-type and N-type MOSFETs, so when forming an actual functional circuit, it can be used especially for frequently used inverters and When forming a block such as a gate circuit, there are many MOSFETs that are not used, and there is a disadvantage that the degree of integration is lower than that of a CMOS gate array, even in terms of element usage rate inside the shell.
本発明の目的は、素子使用率を上げることができ、集積
度を高くすることができるバイポーラＣＭＯＳゲートア
レイ半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a bipolar CMOS gate array semiconductor device that can increase the element usage rate and increase the degree of integration.
本発明のバイポーラＣＭＯＳゲートアレイ半導体装置は
、同一基板上に、それぞれ１つのバイポーラトランジス
タと、複数組のＰ型ＭＯ３ＦＥＴ及びＮ型ＭＯ３ＦＥＴ
とを備えた複数の基本内部セルを有している。The bipolar CMOS gate array semiconductor device of the present invention includes one bipolar transistor and multiple sets of P-type MO3FET and N-type MO3FET on the same substrate.
It has a plurality of basic internal cells.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の基本内部セルの平面レイア
ウト図である。FIG. 1 is a plan layout diagram of a basic internal cell according to an embodiment of the present invention.
この実施例は、１つの基本内部セル内に、１つのバイポ
ーラトランジスタ１２と、２組のＰ型ＭＯＳＦＥＴ（１
３ａ、１３ｂ）及びＮ型ＭＯ３ＦＥＴ （１４ａ、１４
ｂ）と、抵抗１１とを備えた構成となっている。In this embodiment, one bipolar transistor 12 and two sets of P-type MOSFETs (1
3a, 13b) and N-type MO3FET (14a, 14
b) and a resistor 11.
Ｐ型ＭＯＳＦＥＴ１３ａ、１３ｂは、Ｎウェル１上に設
けられたＰ型ソース・ドレイン拡散層３及びゲート配線
層５ａ、５ｂにより形成されている。The P-type MOSFETs 13a and 13b are formed of a P-type source/drain diffusion layer 3 provided on the N well 1 and gate wiring layers 5a and 5b.
また、Ｎ型ＭＯ３ＦＥＴ１．４ａ、１４ｂは、Ｐウェル
２上に設けられたＮ型ソース・ドレイン拡散層４及びゲ
ート配線層５ｃ、５ｄにより形成されている。Further, the N-type MO3FETs 1.4a and 14b are formed of an N-type source/drain diffusion layer 4 provided on the P well 2 and gate wiring layers 5c and 5d.
第２図はこの実施例の等価回路図である。FIG. 2 is an equivalent circuit diagram of this embodiment.
このように本発明の基本内部セル２ｏ内には、１つのバ
イポーラトランジスタ１２と、２組のＰ型ＭＯＳＦＥＴ
１３ａ、１３ｂ及びＮ型ＭＯＳＦＥＴ１４ａ、１４ｂと
、抵抗１１とが設けられている６
第３図は本発明の第２の実施例の基本内部セルの平面レ
イアウト図である。In this way, the basic internal cell 2o of the present invention includes one bipolar transistor 12 and two sets of P-type MOSFETs.
13a, 13b, N-type MOSFETs 14a, 14b, and a resistor 11 are provided.6 FIG. 3 is a plan layout diagram of a basic internal cell according to a second embodiment of the present invention.
この実施例が第１の実施例と相違する点は、バイポーラ
トランジスタ１２ａのコレクタ１２ｃを電源配線層８に
接続した点、及びＰ型Ｍ ＯＳ Ｆ ＥＴ１３ａ、１３
ｂのゲート配線層とＮ型ＭＯＳＦＥＴ１４ａ、１４ｂの
ゲート配線層とをそれぞれ互いに接続した点にある。This embodiment differs from the first embodiment in that the collector 12c of the bipolar transistor 12a is connected to the power supply wiring layer 8, and the P-type MOSFETs 13a, 13
The point is that the gate wiring layer b and the gate wiring layers of the N-type MOSFETs 14a and 14b are connected to each other.
第４図にこの実施例の等価回路図を示す。FIG. 4 shows an equivalent circuit diagram of this embodiment.
この実施例においては、バイポーラトランジスタ１２ａ
のコレクタ１２ｃに対する配線、及びＰ型ＭＯＳＦＥＴ
１３ａ、１３ｂとＮ型ＭＯＳＦＥＴ１４ａ、１４ｂとの
間のゲート間配線が不要になるという利点がある。In this embodiment, bipolar transistor 12a
Wiring for collector 12c and P-type MOSFET
There is an advantage that there is no need for inter-gate wiring between MOSFETs 13a and 13b and N-type MOSFETs 14a and 14b.
第５図（ａ）〜（ｃ）はこの実施例の基本内部セル２Ｏ
Ａを適用して２人力ＮＡＮＤゲートを構成したときの回
路図である。FIGS. 5(a) to 5(c) show the basic internal cell 2O of this embodiment.
FIG. 2 is a circuit diagram when a two-man power NAND gate is constructed by applying A.
この回路は、第５図（ａ）に示されたＭＯＳＦＥＴ部分
と、第５図（ｂ）に示されたバイポーラトランジスタ部
分とを結合し、第５図（Ｃ）に示すような２人力ＮＡＮ
Ｄゲートを構成している。This circuit combines the MOSFET section shown in FIG. 5(a) and the bipolar transistor section shown in FIG. 5(b), and a two-person NAN as shown in FIG.
It constitutes the D gate.
この回路は、出力端に接続された容量性の負荷を充電す
るときのみ、バイポーラトランジスタ１．２ ａを使用
し、放電の際にはＮ型ＭＯＳＦＥＴ１４ａ、１４ｂを使
用するようになっている。This circuit uses a bipolar transistor 1.2a only when charging a capacitive load connected to the output terminal, and uses N-type MOSFETs 14a and 14b when discharging.
第５図（Ｃ）に示された２人力ＮＡＮＤゲートの平面レ
イアウト図を第６図に示す。FIG. 6 shows a plan layout of the two-man powered NAND gate shown in FIG. 5(C).
このように、本発明による基本内部セル２０゜２ＯＡを
使用することにより、簡単な配線でしがも素子使用率の
高い内部回路を形成することができる。As described above, by using the basic internal cell 20°2OA according to the present invention, it is possible to form an internal circuit with simple wiring but with a high element usage rate.
以上説明したように本発明は、１つの基本内部セル内に
複数組のＰ型及びＮ型のＭＯＳ Ｆ ＥＴと１個バイポ
ーラと抵抗とを備えた構成とすることにより、効率的に
ＭＯＳ Ｆ ＥＴとバイポーラトランジスタとを使用す
ることができるので、素子使周率を上げることができ、
従って集積度を高くすることができる効果がある。As explained above, the present invention has a configuration in which one basic internal cell includes a plurality of sets of P-type and N-type MOS FETs, one bipolar transistor, and a resistor. and bipolar transistors can be used, increasing the element usage rate.
Therefore, there is an effect that the degree of integration can be increased.
第１図及び第２図はそれぞれ本発明の第１の実施例の基
本内部セルの平面レイアウト図及び等価回路図、第３図
及び第４図はそれぞれ本発明の第２の実施例の基本内部
セル部の平面レイアウト図及び等価回路図、第５図（ａ
）〜（Ｃ）及び第６図はそれぞれ第３図に示された実施
例の基本内部セルを２人力ＮＡＮＤゲートに適用したと
きの回路図及び平面レイアウト図である。
１・・・Ｎウェル、２・・・Ｐウェル、３・・・Ｐ型ソ
ース・ドレイン拡散層、４・・・Ｎ型ソース・ドレイン
拡ｒ４！ＩＮ、５ ａ 〜５ ｆ ・・・ゲート配線層
、６，６ａ−・Ｎウェル配線層、７・・・Ｐウェル配線
層、８・・・電源配線層、９・・・接地配線層、１０ａ
〜１０ｍ・・・コンタクト、１１・・・抵抗、１２．１
２ａ・・・バイポーラトランジスタ、１３ａ、１３ｂ、
、、Ｐ型ＭＯ３ＦＥＴ、１４ａ、１４ｂ・Ｎ型ＭＯＳＦ
ＥＴ、２０゜ ０Ａ
・・・基本内部セル。1 and 2 are a plan layout diagram and an equivalent circuit diagram of a basic internal cell of a first embodiment of the present invention, respectively, and FIGS. 3 and 4 are a basic internal cell diagram of a second embodiment of the present invention, respectively. Planar layout diagram and equivalent circuit diagram of the cell section, Figure 5 (a
) to (C) and FIG. 6 are a circuit diagram and a plan layout diagram, respectively, when the basic internal cell of the embodiment shown in FIG. 3 is applied to a two-manpower NAND gate. 1...N well, 2...P well, 3...P type source/drain diffusion layer, 4...N type source/drain expansion r4! IN, 5a to 5f...gate wiring layer, 6, 6a--N well wiring layer, 7...P well wiring layer, 8...power supply wiring layer, 9...ground wiring layer, 10a
~10m...Contact, 11...Resistance, 12.1
2a... Bipolar transistor, 13a, 13b,
,, P-type MO3FET, 14a, 14b/N-type MOSF
ET, 20° 0A...Basic internal cell.
Claims (1)
と、複数組のＰ型ＭＯＳＦＥＴ及びＮ型ＭＯＳＦＥＴと
を備えた複数の基本内部セルを有することを特徴とする
バイポーラＣＭＯＳゲートアレイ半導体装置。A bipolar CMOS gate array semiconductor device comprising, on the same substrate, a plurality of basic internal cells each including one bipolar transistor and a plurality of sets of P-type MOSFETs and N-type MOSFETs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18670289A JPH0350767A (en) | 1989-07-18 | 1989-07-18 | Bipolar cmos gate array semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18670289A JPH0350767A (en) | 1989-07-18 | 1989-07-18 | Bipolar cmos gate array semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0350767A true JPH0350767A (en) | 1991-03-05 |
Family
ID=16193139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18670289A Pending JPH0350767A (en) | 1989-07-18 | 1989-07-18 | Bipolar cmos gate array semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0350767A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0493076A (en) * | 1990-08-08 | 1992-03-25 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1989
- 1989-07-18 JP JP18670289A patent/JPH0350767A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0493076A (en) * | 1990-08-08 | 1992-03-25 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
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