JPH03165565A - Master slice semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To lessen a chip in area by a method wherein N channel transistors of basic cells are connected together in parallel, and the drain of the transistor is made to serve as an input protection N+ diode. CONSTITUTION:When an N channel transistor 3 of a basic cell is employed as an output driver, the transistor 3 is used in such a manner that a gate signal is connected to an output driver gate control signal 2. The signal concerned is outputted from an inner logic circuit, and the drain is connected to the output terminal of an integrated circuit through an external connection signal wiring. When the N channel transistor 3 is employed as an input protection P+ diode, a gate signal is connected to VSS- and the gate of the transistor 3 is kept in an OFF state. In this case, the transistor 3 functions as a protective diode 6 in such a manner that if static electricity is applied to a negative side from the input terminal of the integrated circuit, it turns into a reverse current and absorbed, so that an input gate is protected. By this setup, an area required for an input protection pattern can be saved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a gate array device for a master slice semiconductor integrated circuit in which a large number of basic cells are arranged in a two-dimensional matrix. This relates to the fact that the drain portion of the device can be made into an N+ diode for input protection by changing the glass mask for the master slice.

[Conventional technology]

In conventional master slice semiconductor integrated circuits, when an N+ diode for input protection was required, the diode was attached externally, or when the diode was built-in, it existed as a type exclusively for the N+ diode for input protection.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology has a problem in that the diode is externally attached, which increases the number of parts and increases the cost. Further, in the case where a diode is built-in, there is a problem that the pattern area for human power protection of the human output cell becomes large because it exists as a type exclusively for the N+ diode for input protection, and the chip cost increases.

The present invention is intended to solve such problems, and its purpose is to provide a gate array device for a master slice semiconductor integrated circuit in which a large number of basic cells are arranged in a two-dimensional matrix. An object of the present invention is to provide a master slice semiconductor integrated circuit in which the drain portion of a channel transistor can be made into an input protection N+ diode by changing the glass mask for the master slice.

[Means to solve the problem]

In the master slice semiconductor integrated circuit of the present invention, the drain part of the N-channel transistor of the basic cell built in the master slice semiconductor integrated circuit is changed to a glass mask for the master slice, so that the N+
It is characterized by being able to function as a diode.

〔Example〕

The present invention will be described in detail below based on examples.

FIG. 1 is a layout diagram showing an embodiment of the present invention.

When using the basic cell N-channel transistor 3 as an output driver, the gate signal is connected to the output driver gate control signal 2. This signal is an output signal from the internal logic circuit. Further, the drain is connected to the output terminal of the integrated circuit by an external connection signal wiring S.

When used as an N+ diode for human power protection, the gate signal is connected to vSS-, and the gate of the N-channel transistor 3 is turned off.

In this case, a PN junction diode is formed between the N-type impurity diffusion layer of the drain of the N-channel transistor and the P-type well (or P-type substrate) in which it is formed.
At this time, the internal connection signal wiring 4 is connected to the internal logic circuit, and the external connection signal wiring 5 is connected to the input terminal of the integrated circuit.

When used as an N+ diode for human power protection, as shown in Figure 2, even if static electricity is applied to one side from the input terminal of the integrated circuit as a protection diode 6, it will be absorbed as a reverse current and the human power gate will be blocked. Protect.

Furthermore, by connecting the gates of N-channel transistors using a plurality of basic cells and connecting the sources and drains in series to form a parallel connection configuration, the output driver ability can be changed by changing the number of connections.

In the present invention, the connection of the gate signal of each N-channel transistor and the connection of the source signal of multiple P-channel transistors,
Connections between drains and common connections between gates are made by changing the glass mask for the master slice and forming wiring as necessary.

〔Effect of the invention〕

According to the master slice semiconductor integrated circuit having the circuit configuration of the present invention as described above, the drain part of the N-channel transistor of the basic cell can be made into an N+ diode for human power protection by changing the glass mask for the master slice, thereby reducing the chip area. This results in an integrated circuit with excellent cost performance that can be downsized.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing the case where it is used as an N+ diode for input protection. 1 ・ ・ ・ 2nd ・ 3 ・ − 5 ・ i 7 ・ 8 @ Switch output driver Gate control signal N channel transistor internal connection signal wiring External connection signal wiring Input protection N+ diode Internal connection signal wiring External connection signal wiring and above

Claims (1)

[Claims] (1) a) a master slice semiconductor integrated circuit formed by arranging a large number of internal logic gate cells (hereinafter referred to as basic cells) in a two-dimensional matrix, b) an N-channel transistor of the basic cell; and c) the N-channel transistor. A master slice semiconductor integrated circuit, characterized in that a plurality of d) are connected in parallel so that the drain portion of the N-channel transistor can be used as an N+ diode for input protection.