JPH01216568A - Mos type semiconductor device - Google Patents

Mos type semiconductor device

Info

Publication number
JPH01216568A
JPH01216568A JP4270488A JP4270488A JPH01216568A JP H01216568 A JPH01216568 A JP H01216568A JP 4270488 A JP4270488 A JP 4270488A JP 4270488 A JP4270488 A JP 4270488A JP H01216568 A JPH01216568 A JP H01216568A
Authority
JP
Japan
Prior art keywords
type
gate electrode
gate
electrodes
high resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4270488A
Other languages
Japanese (ja)
Inventor
Masayuki Karasawa
唐澤 眞之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4270488A priority Critical patent/JPH01216568A/en
Publication of JPH01216568A publication Critical patent/JPH01216568A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11803Masterslice integrated circuits using field effect technology
    • H01L27/11807CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate an external mounting high resistance element and to reduce the size and cost of a MOS type semiconductor device when an analog circuit is associated in a gate array by realizing the high resistance element with the gate electrode of a basic cell in the array. CONSTITUTION:With P-type polysilicon gate electrodes 101, 102 as gate electrodes P-type MOSFETs 103, 104 are formed, and with N-type polysilicon gate electrodes 105, 106 as gate electrodes N-type MOSFETs 107, 108 are formed. The electrodes 101, 102 are respectively brought into contact with the electrodes 102, 106, thereby forming the basic cell of a gate array. Further, contact holes 109-112 and terminal leads of aluminum 113-116 are respectively formed at the electrodes 101, 102, 105, 106, the terminal leads formed of the aluminums 115, 116 and the holes 111, 112 are connected by aluminum 117, thereby forming a high resistance element by utilizing diode reverse characteristic.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ゲートアレイにおいて、ゲートアレイ内部の
ベーシックセルのゲート電極を利用した高抵抗素子の実
現に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to realizing a high resistance element in a gate array using the gate electrode of a basic cell inside the gate array.

〔従来の技術〕[Conventional technology]

従来のゲートアレイにおいては、高抵抗素子がゲートア
レイ内部に組み込まれたものはなく、高抵抗素子はゲー
トアレイの外部に接続されていた。
In conventional gate arrays, high resistance elements are not incorporated inside the gate array, and the high resistance elements are connected to the outside of the gate array.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

今日、ゲートアレイ内部にディジタル回路だけではなく
、アナログ回路を組み込む傾向が著しく、また、アナロ
グ回路においては高抵抗素子が必要なものとなっている
、しかしながら、従来技術では、高抵抗素子はゲートア
レイの外部に接続されていた為、小型化できないという
問題点を有する。
Nowadays, there is a remarkable tendency to incorporate not only digital circuits but also analog circuits inside gate arrays, and analog circuits require high-resistance elements. However, in conventional technology, high-resistance elements are Since it is connected to the outside of the device, it has the problem that it cannot be miniaturized.

そこで、本発明は以上の如き種々の事情に鑑みなされた
もので、その目的とするところは、ゲートアレイ内部の
ベーシックセルのゲート電・極を利用した高抵抗素子の
実現にある。
SUMMARY OF THE INVENTION The present invention was developed in view of the various circumstances described above, and its purpose is to realize a high-resistance element using the gate electrodes of basic cells inside a gate array.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のMOS型半導体装置は、 ’ a)MOSFETを用いたゲートアレイにおいて、
b)P型ポリシリコンをゲート電極材料とするP型MO
SFETと、N型ポリシリコンをゲート電極材料とする
N型MOSFETとを含み、かつ、前記P型MOSFE
TのゲートtSと、前記N型MOSFETのゲート電極
とが接していることから成るベーシックセルを有し、 C)かつ、少なくとも2つの前記P型MOSFETのゲ
ート電極と前記N型MOSFETのゲート電極とに端子
取り出し口を設け、 d)かつ、少なくとも一方の前記P型MOSFE接続し
た、または、少なくとも一方の前記N型MOSFETの
ゲート電極の端子取り出し口と他方の前記N型MOSF
ETのゲート電極の端子取り出し口とを接続したことを
特徴とする。
The MOS type semiconductor device of the present invention includes: 'a) In a gate array using MOSFETs,
b) P-type MO using P-type polysilicon as the gate electrode material
SFET, and an N-type MOSFET using N-type polysilicon as a gate electrode material, and the P-type MOSFET
C) has a basic cell in which the gate tS of the T and the gate electrode of the N-type MOSFET are in contact with each other; d) and at least one of the P-type MOSFETs is connected to the terminal outlet of the gate electrode of at least one of the N-type MOSFETs and the other of the N-type MOSFETs is provided with a terminal outlet;
It is characterized in that it is connected to the terminal outlet of the gate electrode of the ET.

〔実 施 例〕〔Example〕

本発明の基本的な第1の実施例として第1図に平面図、
第2図に等価回路図を示す。
As a basic first embodiment of the present invention, a plan view is shown in FIG.
Figure 2 shows an equivalent circuit diagram.

第1図において、斜めハツチ部により示される101.
102はP型ポリシリコンゲート電極であり、103.
104は前記101.102をゲート電極としてP型M
OSFETを形成し、クロスハツチ部により示される1
05.106はN型ポリシリコンゲート電極であり、1
07.108は前記105.106をゲート電極として
N型MOSFETを形成する。前記101と105.1
02と106とを接することによりゲートアレイのベー
シックセルを形成する。さらに、前記101.102.
105.106とにそれぞれ109.110.111.
112のコンタクトホールと113.114.115.
116のアルミとにより端子取り出し口を設け、前記1
15と111.112と116とで形成される端子取り
出し口を117のアルミで接続することにより、第2図
の等価回路図に示すように、ダイオード逆方向特性を利
用して高抵抗素子が実現できる。
In FIG. 1, 101.
102 is a P-type polysilicon gate electrode; 103.
104 is a P-type M using the above 101 and 102 as the gate electrode.
1 forming an OSFET and indicated by a crosshatch
05.106 is an N-type polysilicon gate electrode, and 1
07.108 forms an N-type MOSFET using 105.106 as the gate electrode. 101 and 105.1 above
A basic cell of a gate array is formed by connecting cells 02 and 106. Furthermore, the above 101.102.
105.106 and 109.110.111. respectively.
112 contact holes and 113.114.115.
116 aluminum to provide a terminal outlet, and
By connecting the terminal outlet formed by 15, 111, 112 and 116 with aluminum 117, a high resistance element is realized using the diode reverse characteristics, as shown in the equivalent circuit diagram in Figure 2. can.

本発明の基本的な第2の実施例として第3図に平面図、
第4図に等価回路図を示す。
As a basic second embodiment of the present invention, a plan view is shown in FIG.
Figure 4 shows an equivalent circuit diagram.

基本的にベーシックセルの構造は前記第1の実施例と同
じであり、第1図の109と113.110と114と
で形成される端子取り出し口を第3図に示す様に118
のアルミで接続することにより、第4図の等価回路図に
示すように高抵抗素子が実現できる。
Basically, the structure of the basic cell is the same as that of the first embodiment, and the terminal outlet formed by 109 and 113, 110 and 114 in FIG. 1 is replaced by 118 as shown in FIG.
By connecting with aluminum, a high resistance element can be realized as shown in the equivalent circuit diagram of FIG.

以上、基本的な実施例について説明したが、本発明の木
質は、ゲートアレイに前述の様なベーシックセルを適用
することでポリシリコンにより形成されるダイオードの
逆方向特性を利用した高抵抗素子の実現にあり、上記実
施例に限らず第1図中の107のアルミ配線、または第
3図中の108のアルミ配線を変えることにより種々の
高抵抗素子が実現でき、また、ベーシックセルにおける
ゲートtS以外に配線に利用するポリシリコンにおいて
も、P型ポリシリコンとN型ポリシリコンを接したポリ
シリコンを適用することにより同様な事が言える。
Although the basic embodiments have been described above, the wood material of the present invention is a high-resistance element that utilizes the reverse characteristics of a diode formed of polysilicon by applying the above-mentioned basic cell to a gate array. Various high resistance elements can be realized by changing the aluminum wiring 107 in FIG. 1 or the aluminum wiring 108 in FIG. The same thing can be said about polysilicon used for wiring as well, by applying polysilicon in which P-type polysilicon and N-type polysilicon are in contact.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明によればゲートアレイ内部の
ベーシックセルのゲート電極により高抵抗素子が実現で
きる為、ゲートアレイ内部にアナログ回路を組み込む際
、外付けの高抵抗素子が不用となり、製品の小型化、コ
ストの削減が可能となり、また、ベーシックセルのゲー
ト電極を利用した為アルミ配線を容易に行え、アルミ配
線を変えるだけで種々の高抵抗素子が実現でき、また、
チップ面積の増加もないという効果がある。
As described above, according to the present invention, a high resistance element can be realized by the gate electrode of the basic cell inside the gate array, so when incorporating an analog circuit inside the gate array, an external high resistance element is not required. It is possible to downsize and reduce costs, and since the gate electrode of the basic cell is used, aluminum wiring can be easily done, and various high-resistance elements can be realized by simply changing the aluminum wiring.
This has the effect that there is no increase in chip area.

【図面の簡単な説明】 第1図は、本発明の基本的な第1の実施例を示す平面図
、第2図は、本発明の基本的な第1の実施例を示す等価
回路図、第3図は、本発明の基本的な第2の実施例を示
す平面図、第4図は、本発明の基本的な第2の実施例を
示す等価回路図。 101.102・・・P型ポリシリコンゲートを極(斜
めハツチ部) 103.104・・・P型MOSFET105.106
・・・N型ポリシリコンゲート電極(クロスハツチ部) 107.108・・・N型MOSFET109.110
.111.112 ・・・コンタクトホール 113.114.115.116 ・・・アルミ 107・・・・・・・アルミ 108・・・・・・・アルミ 以上 車 11図
[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view showing a basic first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram showing the basic first embodiment of the present invention, FIG. 3 is a plan view showing a second basic embodiment of the invention, and FIG. 4 is an equivalent circuit diagram showing the second basic embodiment of the invention. 101.102...P-type polysilicon gate as pole (diagonal hatch part) 103.104...P-type MOSFET105.106
...N-type polysilicon gate electrode (crosshatch part) 107.108...N-type MOSFET109.110
.. 111.112 ・・・Contact hole 113.114.115.116 ・・・Aluminum 107・・・・・・Aluminum 108・・・・・・Cars made of aluminum or higher Figure 11

Claims (1)

【特許請求の範囲】[Claims] (1)a)絶縁ゲート電界効果トランジスタ(以下MO
SFETと略す)を用いたゲートアレイにおいて、 b)P型ポリシリコンをゲート電極材料とするP型MO
SFETと、N型ポリシリコンをゲート電極材料とする
N型MOSFETとを含み、かつ、前記P型MOSFE
Tのゲート電極と、前記N型MOSFETのゲート電極
とが接していることから成るベーシックセルを有し、 c)かつ、少なくとも2つの前記P型MOSFETのゲ
ート電極と前記N型MOSFETのゲート電極とに端子
取り出し口を設け、 d)かつ、少なくとも一方の前記P型MOSFETのゲ
ート電極の端子取り出し口と他方の前記P型MOSFE
Tのゲート電極の端子取り出し口を接続した、または、
少なくとも一方の前記N型MOSFETのゲート電極の
端子取り出し口と他方の前記N型MOSFETのゲート
電極の端子取り出し口とを接続したことを特徴とするM
OS型半導体装置。
(1) a) Insulated gate field effect transistor (hereinafter MO
b) P-type MO using P-type polysilicon as the gate electrode material
SFET, and an N-type MOSFET using N-type polysilicon as a gate electrode material, and the P-type MOSFET
c) has a basic cell in which the gate electrode of the T-type MOSFET and the gate electrode of the N-type MOSFET are in contact with each other; a terminal outlet for the gate electrode of at least one of the P-type MOSFETs and a terminal outlet for the gate electrode of the other P-type MOSFET;
The terminal outlet of the gate electrode of T is connected, or
A terminal outlet of the gate electrode of at least one of the N-type MOSFETs is connected to a terminal outlet of the gate electrode of the other N-type MOSFET.
OS type semiconductor device.
JP4270488A 1988-02-25 1988-02-25 Mos type semiconductor device Pending JPH01216568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4270488A JPH01216568A (en) 1988-02-25 1988-02-25 Mos type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4270488A JPH01216568A (en) 1988-02-25 1988-02-25 Mos type semiconductor device

Publications (1)

Publication Number Publication Date
JPH01216568A true JPH01216568A (en) 1989-08-30

Family

ID=12643451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4270488A Pending JPH01216568A (en) 1988-02-25 1988-02-25 Mos type semiconductor device

Country Status (1)

Country Link
JP (1) JPH01216568A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245740A (en) * 2005-03-01 2006-09-14 Sanyo Electric Co Ltd Amplifier circuit and electret condenser microphone using same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245740A (en) * 2005-03-01 2006-09-14 Sanyo Electric Co Ltd Amplifier circuit and electret condenser microphone using same

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