JP2006245740A - Amplifier circuit and electret condenser microphone using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit which can achieve a desired resistance value and can be miniaturized, and an electret condenser microphone using the same. <P>SOLUTION: The amplifier circuit or the electret condenser microphone using the same has an impedance conversion element (J-FET) 12, and a high-resistance element 13 connected to the input (a gate electrode) of the impedance conversion element 12 and biasing the input. The high-resistance element 13 is composed by serially connecting a p-channel MOS transistor 131 and an n-channel MOS transistor 132 formed to the same semiconductor substrate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an amplifier circuit and an electret condenser microphone using the same, and more particularly to an amplifier circuit that can be miniaturized and a technique for providing an electret condenser microphone using the amplifier circuit.

  In recent years, small electronic devices such as mobile phones, IC recorders, and PDAs have been increasingly miniaturized. Electret condenser microphones (hereinafter referred to as ECM (Electret Condenser Microphone)) built into these electronic devices are further increased. There is an increasing demand for miniaturization (see, for example, Patent Document 1).

  FIG. 10 shows a circuit example of a general ECM1. In the figure, an electret capacitor 11 has a conductive diaphragm and a fixed electrode facing each other, and a dielectric (electret) is provided on any of these. Either the diaphragm or the fixed electrode is connected to a gate electrode (input) of a junction field effect transistor (hereinafter referred to as J-FET 12) as an impedance conversion element, and the other is grounded. The drain electrode of the J-FET 12 is connected to the drive voltage Vdd via the load resistor RI14, while the source electrode of the J-FET 12 is grounded.

  A high resistance element 13 having the other end grounded is connected to the gate electrode of the J-FET 12. Here, the noise input to the J-FET 12 is reduced, and the filter circuit constituted by the high resistance element 13 and the electret capacitor 11 has a characteristic of passing a low-frequency audio signal (about 100 Hz). Therefore, the resistance value of the high-resistance element 13 is set to a value of several hundred M (mega) to several G (giga) Ω.

When sound is given to the electret capacitor 11 of this circuit, the diaphragm vibrates, and thereby the capacitance of the electret capacitor 11 changes. An audio signal corresponding to the change in capacitance is input to the gate electrode of the J-FET 12, and an AC voltage corresponding to the audio signal is output from the drain electrode of the J-FET 12.
JP 2003-243944 A Japanese Patent Laid-Open No. 11-317996

  By the way, when the high resistance element 13 is constituted by a resistor such as ceramic, for example, the occupied area becomes large, and it is difficult to reduce the size of the ECM 1. Further, when a high resistance is realized with the resistor, an increase in parasitic capacitance becomes a problem.

  On the other hand, in Patent Document 2, a necessary resistance value is obtained by connecting a pair of diodes connected in parallel in the opposite direction. However, since the resistance value of the diode generally varies depending on the process, a desired resistance value is obtained. Difficult to get.

  The present invention has been made in view of such a background, and an object of the present invention is to provide an amplifying circuit which has a good yield and is excellent in mass productivity and can be downsized, and an electret condenser microphone using the amplifying circuit.

  A main invention of the present invention for achieving the above object is an amplifier circuit, comprising: an impedance conversion element; and a high resistance element connected to an input of the impedance conversion element and biasing the input. The high resistance element is formed by connecting a P-channel MOS transistor and an N-channel MOS transistor formed on the same semiconductor substrate in series.

In general, when a P-channel MOS transistor and an N-channel MOS transistor are formed on the same semiconductor substrate, there is little change in resistance value due to variations in threshold voltage _Vth of each MOS transistor. Therefore, in an amplifier circuit used for ECM or the like as in the present invention, a high resistance element that biases the input of an impedance conversion element is connected in series with a P-channel MOS transistor and an N-channel MOS transistor formed on the same semiconductor substrate. With this configuration, it is possible to configure a high-resistance element with little change in resistance value due to variations in threshold voltage _Vth , and to realize an amplifier circuit and an ECM that have a high yield and excellent mass productivity. . In addition, since the high resistance element is configured by the MOS transistor, miniaturization and integration are possible, and a small amplifier circuit and ECM can be realized.

  According to the present invention, it is possible to provide an amplifier circuit that has a good yield and is excellent in mass productivity and can be miniaturized, and an electret condenser microphone using the amplifier circuit.

  Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 shows a circuit configuration of an ECM 1 having an amplifier circuit according to an embodiment of the present invention. In the figure, an electret capacitor 11 has a conductive diaphragm and a fixed electrode facing each other, and a dielectric (electret) is provided on any of these. Either the diaphragm or the fixed electrode is connected to a gate electrode (input) of a junction field effect transistor (hereinafter referred to as J-FET 12) as an impedance conversion element, and the other is grounded. Further, the drain electrode of the J-FET 12 is connected to the drive voltage Vdd via the load resistor RI14, while the source electrode of the J-FET 12 is grounded.

  A high resistance element 13 that biases the gate electrode of the J-FET 12 is connected to the gate electrode of the J-FET 12. Here, the high resistance element 13 is configured by connecting two MOS transistors 131 and 132 formed on the same semiconductor substrate in series. One of the MOS transistors 131 and 132 constituting the high resistance element 13 is a P-channel MOS transistor, and the other is an N-channel MOS transistor. The source electrode of the P channel MOS transistor 131 is connected to the gate electrode of the J-FET 12. The gate electrode of the P channel MOS transistor 131 is connected to the drain electrode of the P channel MOS transistor 131, and the P channel MOS transistor 131 is diode connected. The gate electrode of the N channel MOS transistor 132 is connected to the drain electrode of the N channel MOS transistor 132, and the N channel MOS transistor 132 is diode connected. The gate electrode and drain electrode of the N channel MOS transistor 132 are connected to the gate electrode and drain electrode of the P channel MOS transistor 131. The source electrode of the N channel MOS transistor 132 is grounded.

  FIG. 2 shows a schematic cross-sectional view of a P-type semiconductor substrate 201 on which a P-channel MOS transistor 131 and an N-channel MOS transistor 132 constituting the high resistance element 13 are formed. As shown in the figure, a P-channel MOS transistor 131 includes a first N well 202 formed in a P-type semiconductor substrate 201, and a source electrode (P +) 203 and a drain electrode formed in the first N well 202. (P +) 204 and a gate electrode 205 made of polysilicon (or polycide) formed on both the source electrode (P +) 203 and the drain electrode (P +) 204 through a gate oxide film (not shown). It is configured to include. A body electrode (N +) 206 is formed in the first N well 202.

  On the other hand, the N-channel MOS transistor 132 includes a second N well 211 formed in a region different from the first N well 202, a P well 212 formed in the second N well 211, and a P well 212. The formed drain electrode (N +) 213 and source electrode (N +) 214, and polysilicon (or polycide) formed on the drain electrode (N +) 213 and source electrode (N +) 214 via a gate oxide film. And the gate electrode 215. Note that a power supply electrode (N +) 216 to which a drive voltage Vdd is supplied is formed in the second N well 212. A body electrode (P +) 217 is formed in the P well 212.

  Further, as shown in FIG. 2, the source electrode (P +) 203 and the body electrode (N +) 206 of the P-channel MOS transistor 131 are connected to the gate electrode of the J-FET 12. The gate electrode 205 and the drain electrode (P +) 204 of the P-channel MOS transistor 131 are connected to the drain electrode (N +) 213 and the gate electrode 215 of the N-channel MOS transistor 132. The source electrode (N +) 214 and the body electrode (P +) 217 of the N-channel MOS transistor 132 are grounded. Note that a ground electrode (P +) 218 is formed outside the first N well 202 and the second N well 211 of the P-type semiconductor substrate 201, and the ground electrode (P +) 218 is grounded. Yes.

  As described above, the high resistance element 13 is configured by connecting different types of P-channel MOS transistors 131 and N-channel MOS transistors 132 formed on the same semiconductor substrate in series. Here, the high resistance element 13 having such a configuration has a feature that there is little variation in resistance value. Then, next, the mechanism in which the high resistance element 13 has such a property will be described.

In general, when a MOS transistor is diode-connected, its resistance value has manufacturing variations. Here, the variation in the resistance value is caused by the variation in the threshold voltage _Vth of the MOS transistor. Therefore in order to verify the difference in resistance value due to the difference in the type of variation in the threshold voltage V _th, using the threshold voltage V _th is three different N-channel MOS transistor, and the circuit shown in per Fig. 3 respectively the case _was determined by simulation the _V DS -I _d characteristics. In this simulation, the gate voltage V _GS of the N-channel MOS transistor was fixed at 50 mV, and V _DS was changed from 0 V to 100 mV to obtain the change in the drain current I _d .

The simulation results are shown in FIGS. 4A to 4C. 4A shows a case where the threshold voltage V _th is 386 mV (hereinafter, this case is referred to as “typical” (variable type)), and FIG. 4B shows the threshold voltage V _th FIG. 4C shows a case where the threshold voltage _Vth is set to 491 mV (hereinafter, this case is referred to as “Fast” (small resistance value)). The variation type is “Slow” (high resistance value). Reciprocal of the gradient of the tangent at each point on the V _DS -I _d curve shown in each figure corresponds to the resistance value of the MOS transistor. As described above, since V _GS is 50 mV, the bias condition is the same as when the N-channel MOS transistor is diode-connected when V _DS is 50 mV. In each of FIGS. 4A to 4C, the straight line shown by a dashed line, corresponds to a case V _DS is 50 mV, the inverse of each of these straight lines correspond to the resistance value at the time of the diode connection.

On the other hand, the circuit shown in FIG. 5 was configured, and the difference in resistance value due to the difference in threshold voltage _Vth of one N-channel MOS transistor was obtained by simulation. Note that in this simulation, the drain - voltage _{V DS} between the source was fixed at 50 mV. The gate width of the N channel MOS transistor was set to 1.5 μm and the gate length W was set to 1.5 μm.

The results are shown in Table 1.

As understood from Table 1, when the threshold voltage _Vth is changed from 386 mV to 280 mV, the resistance value which was 1.6 GΩ is extremely reduced to several tens MΩ. That is, it can be understood that the resistance value greatly changes due to variations in the threshold voltage _Vth .

  By the way, generally, when MOS transistors of the same type (P channel and P channel or N channel and N channel) are formed on the same semiconductor substrate, if one variation type is “Fast”, the other is also “Fast”. Thus, if one variation type is “Slow”, the other is also “Slow”, and the probability that the variation types are the same is high. However, when different types of MOS transistors (P channel and N channel) are formed on the same semiconductor substrate, if one variation type is “Fast”, the other variation type is “Slow”. The probability of different increases. For this reason, when two MOS transistors are connected in series, even if one becomes “fast” and the resistance value becomes low, the other becomes “Slow” and the resistance value becomes high. A change in the resistance value of the combined resistor is suppressed. That is, when two MOS transistors are connected in series to form a high resistance element in the circuit shown in FIG. 1, it can be said that it is preferable to employ different types (PMOS and NMOS) of the two MOS transistors.

Table 2 summarizes whether the combination of the threshold voltage variation type of the P-channel MOS transistor and the threshold voltage variation type of the N-channel MOS transistor can be used as a high-resistance element. Is.

Among the combinations shown in Table 2, the combinations marked with “◯” are cases where the resistance value changes little with respect to the variation of the threshold voltage _{Vth and} the resistance value of the high resistance element falls within an appropriate range. . Further, the combinations indicated by “x” marks are cases where the resistance value of the high resistance element changes greatly due to variations in the threshold voltage _Vth . A combination marked with “Δ” is a case where the resistance value of the high resistance element is likely to be high.

In Table 2, “x” is marked for the “Fast-Fast” combination because the resistance value of both the two MOS transistors decreases due to the variation of the threshold value _Vth . In particular, if the resistance variation of each MOS transistor is large, the resistance value of a high resistance element, which is a combined resistance in which these transistors are connected in series, also decreases, and the circuit shown in FIG. There is a high possibility that it will not function as a high-resistance element. In Table 2, the “Slow-Slow” combination is marked with “Δ” because the resistance value of both the P-channel MOS transistor and the N-channel MOS transistor is high, and the variation of each MOS transistor varies. If it is large, the resistance value of the combined resistor becomes high when these are connected in series, and it may not function as a high resistance element for operating the circuit shown in FIG. 1 normally.

For reference, Table 3 shows a summary of the applicability as a high resistance element when two MOS transistors are connected in parallel.

  As shown in Table 3, in the case of parallel connection, when one of them is “Fast”, that is, when both of the resistance values of the two MOS transistors become small, the combined resistance becomes small and high Does not function as a resistance element. On the other hand, in the case of “series” connection, even if only one of them is “Fast”, it functions as a high resistance element. From the above considerations, it is understood that the probability of being used as a high-resistance element is higher in the series connection than in the parallel connection.

As described above, the ECM 1 of this embodiment forms a high-resistance element by connecting different kinds of MOS transistors, that is, a P-channel MOS transistor and an N-channel MOS transistor, formed on the same semiconductor substrate in series. Therefore, there is a feature that there is little change in the resistance value due to variations in the threshold voltage _Vth of each MOS transistor. Therefore, the ECM 1 of the present embodiment has an advantage that the yield is good and the mass productivity is excellent. In addition, since the high resistance element is realized by the MOS transistor, miniaturization and integration are possible, and a small ECM 1 can be configured.

By the way, in the above embodiment, the resistance value of the MOS transistor constituting the high resistance element 13 can be freely set to a desired value by changing the gate width W and the gate length L of the MOS transistor. More specifically, the source-grounded circuit using NMOS transistors, the source - the resistance value R of the NMOS transistor when a voltage is applied to V _B between the drain can be determined from the following equation.

In the above equation, _ID0 is a saturation current, W is a gate width, L is a gate length, _Vth is a threshold voltage, and n is a fitting constant.

Table 4 shows numerical examples of the gate width W and the gate length L when the resistance value of the high resistance element is about 5 G (Ω). The table shows the chip size and occupied area of the chip resistor with a sheet resistance of 200 (MΩ) for reference. As is apparent from this table, when a high resistance element is configured by connecting MOS transistors in series, a high resistance value can be obtained with a very small area compared to the case of using a chip resistor.

FIG. 7 shows the result of simulating the relationship between the applied voltage V _B and the resistance value R by configuring the circuit shown in FIG. 6 using the MOS transistor having the configuration shown in Table 4. As shown in FIG. 7, it can be seen that the resistance value of approximately 3.0~6GΩ is obtained in a wide range of _{V B.}

  By the way, description of the above embodiment is for making an understanding of this invention easy, and does not limit this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  For example, in the above embodiment, as shown in FIG. 1, the P-channel MOS transistor 131 of the two MOS transistors constituting the high-resistance element 13 is arranged near the gate electrode of the J-FET. The N channel MOS transistor 132 may be disposed near the gate electrode of the J-FET.

  In the above embodiment, the high resistance element 13 is constituted by two MOS transistors, but the high resistance element 13 is realized by connecting a plurality of elements composed of combinations of two different types of MOS transistors in series. It may be.

  As shown in FIG. 2, in the above embodiment, the P-well 212 is formed with the second N-well 211 interposed (triple well structure). However, as shown in FIG. It can also be configured without intervening. Further, in this case, as shown in FIG. 9, a circuit configuration in which the first N well 202 of the P-channel MOS transistor 131 is connected to the power source may be employed.

  The J-FET 12 is formed on the same semiconductor substrate as the semiconductor substrate (P-type semiconductor substrate 201 in the above embodiment) on which the P-channel MOS transistor 131 and the N-channel MOS transistor 132 constituting the high resistance element 13 are formed. You may do it.

  The impedance conversion element may be, for example, a bipolar transistor.

It is a figure which shows the circuit structure of ECM1 demonstrated as one Embodiment of the amplifier circuit of this invention. 4 is a schematic cross-sectional view of a semiconductor substrate on which a P-channel MOS transistor 131 and an N-channel MOS transistor 132 constituting the high resistance element 13 are formed according to an embodiment of the present invention. FIG. It is a figure which shows the circuit comprised in the simulation for verifying the difference in resistance value by the difference type of the variation in threshold voltage _Vth . Threshold voltage _{V th} is a diagram showing a _V DS -I _d curve in the case where 386MV. Threshold voltage _{V th} is a diagram showing a _V DS -I _d curve in the case of 280 mV. Threshold voltage _{V th} is a diagram showing a _V DS -I _d curve in the case where 491MV. It is a figure which shows the circuit comprised when simulating the difference in resistance value by the difference in the threshold voltage _Vth of one N channel MOS transistor. It is a diagram showing a circuit configured when the applied voltage V _B to simulate the relationship between the resistance value R. It is a diagram showing the simulation results of the relationship between the applied voltage V _B and the resistance value R. It is a cross-sectional schematic diagram of the semiconductor substrate in which the P channel MOS transistor 131 and the N channel MOS transistor 132 which comprise the high resistance element 13 by other embodiment of this invention are formed. It is a cross-sectional schematic diagram of the semiconductor substrate in which the P channel MOS transistor 131 and the N channel MOS transistor 132 which comprise the high resistance element 13 by other embodiment of this invention are formed. It is a figure which shows an example of general ECM1.

Explanation of symbols

1 ECM
11 Electret capacitor 12 J-FET
DESCRIPTION OF SYMBOLS 13 High resistance element 14 Load resistance 131 P channel MOS transistor 132 N channel MOS transistor 201 P type semiconductor substrate 202 1st N well 203 Source electrode (P +)
204 Drain electrode (P +)
205 Gate electrode 211 Second N well 212 P well 213 Drain electrode (N +)
214 Source electrode (N +)
215 Gate electrode

Claims (8)

An impedance conversion element, and a high resistance element connected to an input of the impedance conversion element and biasing the input,
The high resistance element is formed by connecting in series a P-channel MOS transistor and an N-channel MOS transistor formed on the same semiconductor substrate;
An amplifier circuit characterized by the above. The amplifier circuit according to claim 1,
The P-channel MOS transistor includes a first N well formed in a P-type semiconductor substrate, a source electrode (P +) and a drain electrode (P +) formed in the first N well, and the drain electrode (P +). And a gate electrode formed on the source electrode (P +) through a gate oxide film,
The N-channel MOS transistor includes a second N well formed in a region different from the first N well of the P-type semiconductor substrate, a P well formed in the second N well, A drain electrode (N +) and a source electrode (N +) formed in a P well, and a gate electrode formed on the drain electrode (N +) and the source electrode (N +) through a gate oxide film. An amplifier circuit characterized by The amplifier circuit according to claim 1,
The P-channel MOS transistor includes an N well formed in a P-type semiconductor substrate, a source electrode (P +) and a drain electrode (P +) formed in the N well, the drain electrode (P +), and the source electrode ( P +) and a gate electrode formed through a gate oxide film,
The N-channel MOS transistor is formed on the drain electrode (N +) and the source electrode (N +) formed on the P-type semiconductor substrate, and on the drain electrode (N +) and the source electrode (N +) through a gate oxide film. And an amplifying circuit comprising: a gate electrode that is configured to be a gate electrode; The amplifier circuit according to claim 1,
The amplifier circuit, wherein the impedance conversion element is a field effect transistor or a bipolar transistor. The amplifier circuit according to claim 1,
The amplifier circuit, wherein the impedance conversion element is formed on the same semiconductor substrate as the semiconductor substrate on which the P-channel MOS transistor and the N-channel MOS transistor constituting the high-resistance element are formed. The amplifier circuit according to claim 1,
An amplifying circuit comprising: an electret capacitor connected to the input of the impedance conversion element. An impedance conversion element, a high resistance element connected to the input of the impedance conversion element and biasing the input, and an electret capacitor connected to the input,
The high resistance element is configured by connecting a P-channel MOS transistor and an N-channel MOS transistor formed on the same semiconductor substrate in series.
The P-channel MOS transistor includes a first N well formed in a P-type semiconductor substrate, a source electrode (P +) and a drain electrode (P +) formed in the first N well, and the drain electrode (P +). And a gate electrode formed on the source electrode (P +) through a gate oxide film,
The N-channel MOS transistor includes a second N well formed in a region different from the first N well of the P-type semiconductor substrate, a P well formed in the second N well, A drain electrode (N +) and a source electrode (N +) formed in a P well, and a gate electrode formed on the drain electrode (N +) and the source electrode (N +) through a gate oxide film. An electret condenser microphone characterized by An impedance conversion element, a high resistance element connected to the input of the impedance conversion element and biasing the input, and an electret capacitor connected to the input,
The high resistance element is configured by connecting a P-channel MOS transistor and an N-channel MOS transistor formed on the same semiconductor substrate in series.
The P-channel MOS transistor includes an N well formed in a P-type semiconductor substrate, a source electrode (P +) and a drain electrode (P +) formed in the N well, the drain electrode (P +), and the source electrode ( P +) and a gate electrode formed through a gate oxide film,
The N-channel MOS transistor is formed on the drain electrode (N +) and the source electrode (N +) formed on the P-type semiconductor substrate, and on the drain electrode (N +) and the source electrode (N +) through a gate oxide film. An electret condenser microphone, comprising: a gate electrode that is configured to be formed.