JP2019121937A - Electric charge detection circuit and piezoelectric microphone - Google Patents

Abstract

To provide an electric charge detection circuit capable of detecting a high S/N ratio signal, and reducing output variations to threshold value voltage variations of a field effect transistor.SOLUTION: A first field effect transistor 16 of an electric charge detection circuit includes a gate connected to one terminal of an electric charge generation source 8. A first resistor 14 is connected between a drain of a first field effect transistor 16 and a second node N2 fixed to a second voltage (Vdd). A second field effect transistor 26 includes a gate and a drain connected to the other terminals of the electric charge generation source 8. A second resistor 24 is connected between a drain of the second field effect transistor 26 and the second node N2. Preferably, at least the first field effect transistor 16 operates in a sub-threshold region, and a gate voltage of the first field effect transistor 16 operates between a first voltage (GND) and a second voltage (Vdd).SELECTED DRAWING: Figure 3

Description

  The present invention relates to a charge detection circuit and a piezoelectric microphone including the same.

  In recent years, it is required to detect a minute signal of a sensor at a higher S / N ratio while suppressing power consumption. For example, in a high sensitivity microphone or the like, it is necessary to amplify a minute signal of a sensor that detects sound at a high S / N ratio.

  In general, on the premise that the amplification element in the subsequent stage has low noise and a large dynamic range, the S / N ratio of the amplification circuit is determined based on the performance of the amplification element in the first input stage.

  Conventionally, in such applications, a field effect transistor (FET) is often used in the input first stage, and in particular, a JFET (Junction Field-Effect Transistor) may be used.

FIG. 11 is a circuit diagram of the charge detection circuit described in the paper of the piezoelectric microphone (Non-Patent Document 1). In FIG. 11, one terminal of the charge generating element denoted as Sensor is connected to the ground, and the other terminal is connected to the gate of the JFET. The source of the JFET is connected to ground, and the drain of the JFET is connected to the power supply V _DD through a resistor R _L. An output voltage _Vout is obtained as a potential difference between the source of the JFET and the connection node of the resistor R _L and the ground. This detection circuit is a source-grounded amplification circuit.

Robert John Littrell, High Performance Piezoelectric MEMS Microphones, 2010, Figure 2.4, [Search on December 21, 2017], Internet, <URL, https://deepblue.lib.umich.edu/bitstream/handle/20272/75833/ rlittrel_1.pdf>

  In general, the FET is used to detect a signal using an ON region of Vgs-Vth> 0 (the gate-source voltage Vgs is higher than the threshold voltage Vth). However, in such usage, there is a limit in improving the S / N ratio, and it is desired to further improve the S / N ratio.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a charge detection circuit capable of signal detection with a high S / N ratio.

  The present invention, in summary, is a charge detection circuit for detecting a charge generated in a charge generation source, comprising: a first field effect transistor, a first resistor, a second field effect transistor, and a second resistor And an output node. The first field effect transistor has a gate connected to one terminal of the charge generation source, and a source connected to a first node fixed to a first voltage. The first resistor is connected between the drain of the first field effect transistor and a second node fixed at a second voltage. The second field effect transistor has a gate and a drain connected to the other terminal of the charge generation source, and a source connected to the first node. The second resistor is connected between the drain of the second field effect transistor and the second node. The output node is connected to the drain of the first field effect transistor.

  Preferably, at least the first field effect transistor operates in the subthreshold region, and the gate voltage of the first field effect transistor operates between the first voltage and the second voltage.

  Preferably, the first field effect transistor and the second field effect transistor have the same characteristics.

  Preferably, the charge detection circuit further includes a third resistor connected between the gate of the first field effect transistor and the gate of the second field effect transistor in parallel with the charge generation source.

  More preferably, the resistance value of the third resistor is smaller than the resistance value of the charge generation source and smaller than the gate-source resistance of the first field effect transistor, and the resistance value of the third resistor is smaller than the third resistance. The inverse number of the time constant converted from the resistance of the charge generation source and the capacitance of the charge generation source and the input capacitance of the first field effect transistor is set to be smaller than the detection frequency.

  More preferably, a resistance utilizing a resistance component of a PN junction is used as at least one of the first resistance, the second resistance, and the third resistance.

Preferably, the charge generation source is a piezoelectric body.
In another aspect, the present invention is a piezoelectric microphone provided with any one of the above charge detection circuits and a charge generation source. The charge generation source is a membrane using a piezoelectric thin film, and detects a sound input to the membrane.

  According to the present invention, it is possible to realize a charge detection circuit capable of signal detection with a high S / N ratio and reducing output variation with respect to threshold voltage variation of a field effect transistor.

It is a circuit diagram showing composition of detection circuit A of a study example. It is a circuit diagram showing composition of detection circuit B of a study example. It is a circuit diagram showing composition of detection circuit C of an embodiment. It is a circuit diagram showing composition of detection circuit D of an embodiment. It is a figure which shows the actual structure of a charge generation source. It is a figure which shows the relationship between gate voltage and drain current. It is a figure which shows the relationship between frequency and sensitivity (Vrms). It is the figure which showed the relationship between frequency and noise voltage. It is the figure which compared and showed the sensitivity of each circuit, noise, and S / N ratio. It is a figure which shows the sensitivity calculation result (at 1 kHz) at the time of assuming that the threshold voltage of FET shifts | deviates ± 0.05V. It is a circuit diagram of the charge detection circuit described in the paper (nonpatent literature 1) of a piezoelectric microphone.

  Hereinafter, a study example and an embodiment of the present invention will be described in comparison with reference to the drawings. The same or corresponding portions in the drawings have the same reference characters allotted and description thereof will not be repeated.

  First, before describing the embodiment of the present invention, the configurations of two examination examples will be described. FIG. 1 is a circuit diagram showing a configuration of a detection circuit A of a study example. FIG. 2 is a circuit diagram showing the configuration of the detection circuit B in the study example.

  The detection circuit A shown in FIG. 1 is a detection circuit assuming a JFET (signal detection using a region above the threshold voltage of the FET). The detection circuit A includes a DC voltage source 2, a resistor 4 and a JFET 6. The charge generation source 8 is connected to the gate of the JFET.

  In the following study, various calculations are performed using a circuit simulator LTSpice (Linear Technology). Therefore, charge generation source 8 is simulated by a circuit in which signal source 10 generating a sine wave signal, equivalent resistance 12 having a resistance value of 100 GΩ, and equivalent capacitance 15 having a capacitance value of 2 pF are connected in parallel. ing.

  The detection circuit B shown in FIG. 2 is a circuit in which the resistor 4 is replaced with the resistor 14 and the JFET 6 is replaced with the N-channel type MOSFET 16 in the configuration of the detection circuit A of FIG. This detection circuit B does not perform signal detection using a region where the gate voltage is equal to or higher than the threshold voltage like the detection circuit A, but performs signal detection using a subthreshold region of the MOSFET 16 whose gate voltage is lower than the threshold voltage. It is a detection circuit assumed.

  Next, the configuration of the detection circuit according to the embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a configuration of the detection circuit C of the embodiment. FIG. 4 is a circuit diagram showing a configuration of the detection circuit D according to the embodiment.

  The detection circuit C of FIG. 3 includes a DC voltage source 2, resistors 14 and 24, and N-channel MOSFETs 16 and 26. The resistor 14 and the MOSFET 16 are connected in series between the positive voltage node of the DC voltage source 2 and the ground, and an output voltage signal VoutC is output from these connection node. The resistor 24 and the MOSFET 26 are connected in series between the positive voltage node of the DC voltage source 2 and the ground. The gate of the MOSFET 26 is connected to the drain of the MOSFET 26 and to one terminal of the charge generation source 8. The gate of the MOSFET 16 is connected to the other terminal of the charge generation source 8. In one example, the resistance value of the resistor 14 is 60 kΩ, and the resistance value of the resistor 24 is 120 kΩ.

  The source of the MOSFET 16 is connected to ground. The power supply voltage Vdd of 1.8 V is supplied to the drain of the MOSFET 16 from the direct current voltage source 2 through the 60 kΩ resistor 14. An output terminal is provided at a connection node between the drain of the MOSFET 16 and the resistor 14, and an output voltage signal VoutC is output.

  The source of the MOSFET 26 is connected to ground. A power supply voltage Vdd of 1.8 V is supplied to the drain of the MOSFET 26 from the DC voltage source 2 through a resistor of 120 kΩ. The gate of the MOSFET 26 is connected to the drain.

  The detection circuit D of FIG. 4 is a circuit to which the resistor 32 connected between the gate of the MOSFET 16 and the gate of the MOSFET 26 is added in the configuration of the detection circuit C of FIG. The resistor 32 is connected in parallel to the charge generation source 8. The resistance value of the resistor 32 is 10 GΩ in one example.

  FIG. 5 is a diagram showing the actual structure of the charge generation source. As shown in FIG. 5, the charge generation source 8 has a membrane structure made of a piezoelectric material. Underlying thin film layer 68 is formed to cover the through hole of silicon substrate 70 provided with a through hole at the center, and electrode thin film layers 52, 54, 56 and piezoelectric thin film layers 62, 64 are alternately arranged thereon. It is stacked. The description of the geometrical detailed structure of the membrane is omitted.

  When a sound pressure of 1 Pa is input to this membrane, a sine wave of a current amplitude I = 2πfQ (at f = 20 Hz to 20000 Hz, generated charge amount Q = 5E-14C) is generated from the piezoelectric body. In the circuit diagrams of FIGS. 1 to 4, the capacitance value 2 pF of the equivalent capacitance 15 of the piezoelectric capacitor and the resistance value 100 GΩ of the equivalent resistor 12 corresponding to the leak current of the piezoelectric body are described.

  The performance of the detection circuit of the examination example of the above configuration and the detection circuit of the embodiment simulated by the circuit simulator LTSpice (Linear Technology) will be described below.

  First, the comparison result of the detection circuit A and the detection circuit B in the study example will be described. FIG. 6 is a diagram showing the relationship between gate voltage and drain current. It should be noted that the vertical axis indicating the drain current is in logarithmic scale.

  The configurations of the detection circuit A and the detection circuit B are basically the same, and the characteristics of the FET are different. The FET of the detection circuit A (simulating JFET) is a JFET having an input capacitance of 3 pF and an Ids-Vgs characteristic shown in A of FIG. In the vicinity of Vgs = 0 V where detection is assumed, the gate voltage is in the ON state higher than the threshold voltage Vth. The flicker noise coefficient KF of the JFET model is KF = 4.56E-17, and the flicker noise index AF is 1 (these values are common values as a JFET).

  The FET of the detection circuit B (simulating the FET in the subthreshold region operation) is an N-channel MOSFET having an input capacitance of 13.6 pF and an Ids-Vgs characteristic shown in B of FIG. There is a subthreshold region near Vgs = 0 V assuming detection. The flicker noise coefficient of the MOSFET model, KF = 1E-24, and the flicker noise index AF = 1 (these values are general values for a MOSFET).

  In the charge generation source 8, it is assumed that the capacitance value is 2 pF and a sine wave of current amplitude I = 2πfQ (at f = 20 Hz to 20000 Hz, generated charge amount Q = 5E-14C) is generated. The charge generation source 8 is assumed to have a leak current, and a resistance value 100 GΩ is inserted in parallel with the signal source 10 as an equivalent resistance 12 corresponding to the leak current.

  In the detection circuit A, the resistance value of the fixed resistor 4 is set to 20 kΩ so as to correlate with the current value of the JFET 6 in the vicinity of 0 V. In this case, the current consumption is about 45 μA.

  In the detection circuit B, the resistance value of the fixed resistor 14 is set to 60 kΩ so as to be correlated with the current value in the vicinity of 0 V of the MOSFET 16. In this case, the current consumption is about 16 μA.

  FIG. 7 is a diagram showing the relationship between frequency and sensitivity (Vrms). FIG. 8 is a diagram showing the relationship between frequency and noise voltage. These are the results of calculation using the circuit simulator LTSpice. Note that noise sources other than this circuit are not taken into consideration in the noise calculation this time (in reality, tan δ of the charge generation source and other leakage current etc. are added as noise).

  Assuming that the application product is a microphone, sensitivity S is the voltage at 1 kHz, and noise N is the voltage obtained by integrating the range from 20 Hz to 20000 Hz after the application of the A characteristic filter, including the S / N ratio. In summary, the results (circuit A, circuit B) shown in FIG. 9 are obtained.

  Although the noise of the circuit B is larger than that of the circuit A, the sensitivity increase effect is larger than that of the circuit A, so that the S / N ratio is improved. This is because the detection circuit B detects a signal in the subthreshold region in which the degree of change in the source-drain current Ids is larger than the gate voltage Vgs.

  In addition, in the detection circuit B, the input capacitance of the FET is larger than that of the detection circuit A, and the current consumption is also small. Therefore, although it is generally considered to work disadvantageously in the S / N surface, the subthreshold region is more than that. It can be said that the S / N improvement effect attributable to the high sensitivity by detecting at is superior.

  From the above, comparing the detection circuit A and the detection circuit B, it can be seen that the S / N ratio is improved in the detection circuit B which detects in the subthreshold region of the FET. Therefore, it is also conceivable to use the detection circuit B to improve the S / N ratio.

  However, the problem in the case of detection in the subthreshold region of the FET is that the variation in the threshold voltage Vth is generated due to the manufacturing variation of the FET, and the sensitivity largely fluctuates.

  FIG. 10 is a diagram showing the sensitivity calculation result (at 1 kHz) when it is assumed that the threshold voltage of the FET deviates by ± 0.05V. As shown in A of FIG. 10, in the detection circuit A, the sensitivity fluctuation is relatively small even if the threshold voltage Vth deviates, but as shown in B of FIG. 10, in the detection circuit B, the sensitivity largely fluctuates if the threshold voltage Vth deviates. It becomes difficult to use it in practical use.

  In the present embodiment, such a problem is solved by using the detection circuit C of FIG. 3 and the detection circuit D of FIG.

  The detection circuit C of FIG. 3 has a configuration in which an FET 26 and a fixed resistor 24 are added to the detection circuit B of FIG. 2. In the detection circuit C, both the FET 16 and the FET 26 are N-channel MOSFETs, and the input capacitance is 13.6 pF. The Ids-Vgs characteristic of the FET 16 of the detection circuit C at this time is shown in C of FIG. The FET has a +0.2 V threshold voltage higher than the characteristics of the detection circuit B. The flicker noise coefficient of the MOSFET model is KF = 1E-24, and the flicker noise index is AF = 1 (this value is a general value for a MOSFET).

  Similar to the detection circuits A and B, in the charge generation source 8, it was assumed that a sine wave having a capacitance value of 2 pF and a current amplitude I = 2πfQ (at f = 20 Hz to 20000 Hz, generated charge amount Q = 5E-14C) is generated.

  The fixed resistance 14 was 60 kΩ. As a result, the current consumption of the FET 16 is about 16 μA. On the other hand, the fixed resistance 24 was 120 kΩ. As a result, the consumption current of the FET 26 becomes about 13 μA.

  The results of calculation of the output voltage and the noise voltage using the circuit simulator LTSpice (Linear Technology) are shown in FIG. 7C and FIG. 8C.

  Assuming that the application is a microphone, the sensitivity S is a voltage at 1 kHz, and the noise N is a voltage obtained by integrating the range of 20 Hz to 20000 Hz after the application of the A characteristic filter. The result is shown in the circuit C of FIG. It can be seen that even with the detection circuit C, a high S / N ratio can be obtained as in the detection circuit B.

  Here, the sensitivity calculation result (at 1 kHz) when assuming that the threshold voltage of the FET is shifted by ± 0.05 V due to manufacturing variation or the like is shown in C of FIG. It was found that even if the threshold voltage deviates due to manufacturing variations etc., the sensitivity fluctuation can be made very small. This is because the FET 26 acts to adjust so as to maintain the amount of current of the FET 16 even if the threshold voltage fluctuates.

  In addition, in order for this adjustment to work, it is necessary that the gate voltage of the FET 16 be between the source voltage of the FET 16 and the power supply voltage.

  In the detection circuit D shown in FIG. 4, a resistor 32 connected in parallel to the charge generation source 8 is added to the detection circuit C. The resistor 32 is introduced for the purpose of suppressing the drift of the output voltage with respect to the unstable charge generation due to the unstable leak current of the piezoelectric body or the pyroelectric effect. By making the resistance value of the resistor 32 smaller than the resistance value of the equivalent resistor 12 of the charge generation source 8 and smaller than the gate-source resistance value of the FET 16, the resistor 32 effectively functions. On the other hand, if the resistance value of the resistor 32 is too small, the sensitivity of the low frequency region is lowered, so the resistance value of the resistor 32 is converted from the resistance value of the resistor 32 and the equivalent capacitance 15 of the charge source 8 and the capacitance of the FET 16 Preferably, the reciprocal of the time constant to be set is smaller than the detection frequency.

  The fixed resistors 14 and 24 may be pseudo resistors using a predetermined FET, such as source-drain resistors of FETs, or pseudo resistors using a resistance component of a pn junction.

  Also in the case of the detection circuit D shown in FIG. 4, substantially the same characteristics as the detection circuit C are shown in FIGS. 6, 7 and 10. As shown in FIG. 9, with regard to noise, with respect to the detection circuit D, the noise increased compared to the detection circuit C, and the S / N ratio slightly decreased, but both the sensitivity and the S / N ratio were detected. It is improved over the circuit A and shows desirable characteristics.

  As described above, in the detection circuits C and D according to the present embodiment, detection with a high S / N ratio is possible, and sensitivity variation with respect to threshold voltage variation of the FET can also be reduced. In addition, a compact, low power consumption, and high S / N ratio piezoelectric microphone can be realized.

  Although the problem of the temperature characteristic has not been mentioned up to now, the threshold voltage of the FET is shifted due to the temperature change, so the configuration of the present embodiment is considered to be effective also for reducing the sensitivity variation with respect to the temperature change. .

  Finally, the present embodiment will be summarized again with reference to the drawings. The charge detection circuit C of the present embodiment shown in FIG. 3 outputs the first field effect transistor 16, the first resistor 14, the second field effect transistor 26, the second resistor 24, and the VoutC. And an output node Nout. The first field effect transistor 16 has a gate connected to one terminal of the charge generation source 8 and a source connected to a first node (GND) fixed to a first voltage. The first resistor 14 is connected between the drain of the first field effect transistor 16 and the second node N2 fixed to the second voltage (Vdd). The second field effect transistor 26 has a gate and a drain connected to the other terminal of the charge generation source 8 and a source connected to the first node (GND). The second resistor 24 is connected between the drain of the second field effect transistor 26 and the second node N2. The output node Nout is connected to the drain of the first field effect transistor 16.

  Preferably, at least the first field effect transistor 16 operates in the subthreshold region, and the gate voltage of the first field effect transistor 16 operates between the first voltage (GND) and the second voltage (Vdd). Do.

  With the above configuration, the charge detection circuit can detect a signal with a high S / N ratio, and can greatly reduce the output variation with respect to the threshold voltage variation of the field effect transistor.

  Preferably, the first field effect transistor 16 and the second field effect transistor 26 have the same characteristics. With such a configuration, output voltage variation can be further reduced.

  Preferably, as shown in FIG. 4, in addition to the configuration of the charge detection circuit C, the charge detection circuit D includes the gate of the first field effect transistor 16 and the second field effect transistor in parallel with the charge generation source 8. It further comprises a third resistor 32 connected between it and the gate of 26.

  More preferably, the resistance value of the third resistor 32 is smaller than the resistance value of the equivalent resistor 12 of the charge generation source 8 and smaller than the gate-source resistance of the first field effect transistor 16. The resistance value of the third resistor 32 is such that the reciprocal of the time constant converted from the third capacitor 32 and the equivalent capacitance 15 of the charge generation source 8 and the input capacitance of the first field effect transistor 16 is smaller than the detection frequency It is set to become. For example, in the model described in FIG. 3, the capacitance is 15.6 pF (charge generation source capacitance 2 pF + FET input capacitance 13.6 pF), and the third resistance is 10 GΩ, and 1 ÷ (15.6E-12 × 10E9) = 6.4 Hz, which is set to be smaller than the lower limit 20 Hz of the audio frequency in microphone application.

  With such a configuration, the gate voltage of the first field effect transistor 16 can be stabilized at a predetermined time constant, so that the output voltage can be stabilized.

  More preferably, as at least one of the first resistor 14, the second resistor 24, and the third resistor 32, a resistor using a resistance component of a PN junction is used. The resistance using the resistance component of the P-N junction may be any resistance as long as it includes the respective resistances of the P-type impurity region and the N-type impurity region and the resistance of the P-N junction portion in the semiconductor substrate. For example, a source-drain resistance of a field effect transistor whose gate voltage is controlled to a predetermined potential, a reversely connected zener diode, or the like can be used. Such a resistor can provide a high resistance with a smaller area than a resistor utilizing a wiring layer such as polysilicon. Therefore, the entire charge detection circuit can be miniaturized.

  Preferably, the charge generation source 8 is a piezoelectric body including the piezoelectric thin film layer 62 as shown in FIG.

  In another aspect, the present invention is a piezoelectric microphone provided with a charge detection circuit C or a charge detection circuit D and a charge generation source 8. The charge generation source 8 is a membrane body using the piezoelectric thin film layer 62 as shown in FIG. 5, and is configured to detect a sound input to the membrane body.

As a result, a compact, low power consumption, high S / N ratio piezoelectric microphone can be realized.
It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is indicated not by the above description but by the claims, and is intended to include all the modifications within the meaning and scope equivalent to the claims.

  DESCRIPTION OF SYMBOLS 2 DC voltage source, 4, 14, 24, 32 resistance, 8 charge generation source, 10 signal source, 12 equivalent resistance, 15 equivalent capacity, 16,26 MOSFET, 52,54,56 electrode thin film layer, 62,64 piezoelectric material Thin film layer, 68 base thin film layer, 70 silicon substrate, A, B, C, D charge detection circuit, N2 second node, Nout output node.

Claims (8)

A charge detection circuit for detecting charge generated in a charge generation source, comprising:
A first field effect transistor having a gate connected to one terminal of the charge generation source and a source connected to a first node fixed to a first voltage;
A first resistor connected between the drain of the first field effect transistor and a second node fixed to a second voltage;
A second field effect transistor having a gate and a drain connected to the other terminal of the charge generation source, and a source connected to the first node;
A second resistor connected between the drain of the second field effect transistor and the second node;
A charge detection circuit comprising: an output node connected to a drain of the first field effect transistor.   2. The device according to claim 1, wherein at least the first field effect transistor operates in a subthreshold region, and a gate voltage of the first field effect transistor operates between the first voltage and the second voltage. Charge detection circuit.   The charge detection circuit according to claim 1, wherein the first field effect transistor and the second field effect transistor have the same characteristic.   4. The semiconductor device according to claim 1, further comprising: a third resistor connected between the gate of the first field effect transistor and the gate of the second field effect transistor in parallel with the charge generation source. The charge detection circuit according to claim 1. The resistance value of the third resistor is smaller than the resistance value of the charge generation source, and smaller than the gate-source resistance of the first field effect transistor,
The resistance value of the third resistor is determined such that the reciprocal of the time constant converted from the third resistor, the capacitance of the charge generation source, and the input capacitance of the first field effect transistor is smaller than the detection frequency. The charge detection circuit according to claim 4, wherein the charge detection circuit is set to   6. The charge detection circuit according to claim 4, wherein a resistance utilizing a resistance component of a PN junction is used as at least one of the first resistance, the second resistance, and the third resistance. .   The charge detection circuit according to any one of claims 1 to 6, wherein the charge generation source is a piezoelectric body. A charge detection circuit according to any one of claims 1 to 7;
And the charge generation source,
The charge generation source is a membrane using a piezoelectric thin film, and detects a sound input to the membrane.

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