TW201106126A - Reference voltage circuit and electronic device - Google Patents

Reference voltage circuit and electronic device Download PDF

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TW201106126A
TW201106126A TW099115668A TW99115668A TW201106126A TW 201106126 A TW201106126 A TW 201106126A TW 099115668 A TW099115668 A TW 099115668A TW 99115668 A TW99115668 A TW 99115668A TW 201106126 A TW201106126 A TW 201106126A
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mos transistor
channel depletion
channel
reference voltage
voltage circuit
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TW099115668A
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Chinese (zh)
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TWI474150B (en
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Takashi Imura
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Seiko Instr Inc
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
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  • General Physics & Mathematics (AREA)
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  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

In order to realize a reference voltage circuit that operates with lower current consumption while maintaining an operation at lower voltage without causing deterioration of a power supply rejection ratio, provided is a reference voltage circuit in which a depletion transistor of an ED type reference voltage circuit is constituted of a plurality of depletion transistors connected in series, and in which a gate terminal of a cascode depletion transistor is connected to a connection point between the depletion transistors of the ED type reference voltage circuit.

Description

201106126 六、發明說明： 【發明所屬之技術領域】 本發明是有關半導體裝置，更詳細是有關對於電 壓的變動而言，輸出電壓的變動小，可低電壓動作化 消費電流化的基準電壓電路。 【先前技術】 基於改善類比電路的電源電壓變動除去比之目的 加疊接電路的手法是從以前便被廣泛使用。更使用一 善電源電壓變動除去比，一面可低電壓動作的基準電 路（例如參照專利文獻1 )。在圖4顯示以往的基準電 路的電路圖。 N通道空乏型MOS電晶體301及N通道增強型 電晶體302是構成ED型基準電壓電路310,對ED型 電壓電路310串連有作爲疊接電路動作的n通道空 MOS電晶體3 03。在N通道增強型MOS電晶體302 有控制電流源的N通道增強型MOS電晶體3 04，連 極端子與源極端子的N通道空乏型MOS電晶體305 串連至N通道增強型MOS電晶體304。而且，n通道 型MOS電晶體305的源極端子會被連接至N通道空 MOS電晶體3 03的閘極端子。N通道增強型M〇s電 304及N通道空乏型MOS電晶體3 05是形成對作爲 電路動作的N通道空乏型MOS電晶體3 03供給—定 壓電壓之偏壓電路311。 源電 、低 ，附 面改 壓電 壓電 MOS 基準 乏型 並連 接閘 會被 空乏 乏型 晶體 疊接 的偏 -5- 201106126 在上述的電路中，N通道增強型MOS電晶體302與 3 04及N通道空乏型MOS電晶體303與3 05的特性及跨 導（Transconductance)係數亦爲相等。此情況，因爲各個空 乏型MOS電晶體的源極·後閘極間電壓-汲極電流特性相 等，且汲極電流相等，所以各個空乏型MOS電晶體的源 極電位相等。 在此，N通道空乏型MOS電晶體3 05的源極電位， 可藉以下的方法來比N通道空乏型MOS電晶體303的源 極電位更降低。 1) 對於N通道增強型MOS電晶體3 02的跨導係數， 固定L長，擴大W長等來增大N通道增強型MOS電晶體 3 04的電晶體的跨導係數。 2) 對於N通道空乏型MOS電晶體3 03的跨導係數， 縮小N通道空乏型MOS電晶體3 05的電晶體的跨導係數 3)實施1及2的雙方。 如此一來，圖4的基準電壓電路可低電壓動作。 [先行技術文獻] [專利文獻] [專利文獻1 ]特開2 0 0 7 - 2 6 6 7 1 5號公報 【發明內容】 (發明所欲解決的課題） 然而’因爲上述的蕋準電壓電路是在從N通道空乏型 •6 · 201106126 MOS電晶體3 05到N通道增強型MOS電晶體3 04的路徑 、及從N通道空乏型MOS電晶體3 03到ED型基準電壓 電路3 1 0的路徑之2個的路徑流動電流，所以缺點是消費 電流變多。 本發明是爲了解決以上那樣的課題而設計者，實現一 種不使低電壓動作或電源電壓變動除去比惡化，以更低的 消費電流來動作的基準電壓電路。 (用以解決課題的手段） 爲了解決以往的課題，本發明的基準電壓電路是設置 疊接用空乏電晶體，以複數的空乏電晶體來構成決定基準 電壓的空乏電晶體，作爲將第1空乏電晶體的汲極與第2 空乏電晶體的源極的連接點連接至疊接用空乏電晶體的閘 極端子之構成。 [發明的效果] 本發明的基準電壓電路與以往的電路作比較，可提供 一種不使低電壓動作或電源電壓變動除去比惡化，以更低 的消費電流來動作的基準電壓電路。 【實施方式】 圖1是表示本發明的基準電壓電路的第一實施形態的 電路圖。 本實施形態的基準電壓電路是具備：電源端子1 0 1、 201106126 GND 端子 100、N 通道增強型（enhancement type)MOS 電 晶體1、N通道空乏型（depletion type)MOS電晶體2、N 通道空乏型MOS電晶體3、N通道空乏型MOS電晶體4 及輸出端子102。[Technical Field] The present invention relates to a semiconductor device, and more particularly to a reference voltage circuit in which fluctuations in output voltage are small and voltage-operated current consumption is reduced in response to variations in voltage. [Prior Art] Based on the improvement of the power supply voltage variation of the analog circuit, the method of adding the splicing circuit has been widely used from the past. Further, a reference circuit that can operate at a low voltage while using a power supply voltage variation removal ratio is used (see, for example, Patent Document 1). A circuit diagram of a conventional reference circuit is shown in Fig. 4 . The N-channel depletion MOS transistor 301 and the N-channel enhancement transistor 302 constitute an ED-type reference voltage circuit 310, and an NMOS-type voltage circuit 310 is connected in series with an n-channel empty MOS transistor 303 operating as a splicing circuit. In the N-channel enhancement type MOS transistor 302, there is an N-channel enhancement type MOS transistor 03 with a control current source, and an N-channel depletion MOS transistor 305 connected to the terminal and the source terminal is connected in series to the N-channel enhancement type MOS transistor. 304. Moreover, the source terminal of the n-channel type MOS transistor 305 is connected to the gate terminal of the N-channel empty MOS transistor 303. The N-channel enhancement type M〇s electric 304 and the N-channel depletion type MOS transistor 305 are bias circuits 311 for supplying a constant voltage to the N-channel depletion MOS transistor 03 which operates as a circuit. Source, low, surface-to-face piezoelectric piezoelectric MOS reference is missing and the connection gate will be overlapped by the lack of crystals. -201106126 In the above circuit, N-channel enhancement MOS transistor 302 and 3 04 The characteristics and transconductance coefficients of the N-channel depleted MOS transistors 303 and 305 are also equal. In this case, since the source-back gate voltage-drain current characteristics of the respective vacant MOS transistors are equal and the drain currents are equal, the source potentials of the respective depleted MOS transistors are equal. Here, the source potential of the N-channel depletion MOS transistor 305 can be lowered more than the source potential of the N-channel depletion MOS transistor 303 by the following method. 1) For the transconductance coefficient of the N-channel enhancement type MOS transistor 302, the L length is fixed, the W length is expanded, and the like, and the transconductance coefficient of the transistor of the N-channel enhancement type MOS transistor 309 is increased. 2) For the transconductance coefficient of the N-channel depletion MOS transistor 03, the transconductance coefficient of the transistor of the N-channel depletion MOS transistor 305 is reduced. 3) Both of 1 and 2 are implemented. As such, the reference voltage circuit of FIG. 4 can operate at a low voltage. [PRIOR ART DOCUMENT] [Patent Document 1] [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei 2 0 0 7 - 2 6 6 7 1 5 SUMMARY OF THE INVENTION (Problems to be Solved by the Invention) However, because of the above-mentioned quasi-voltage circuit It is in the path from the N-channel depletion type•6·201106126 MOS transistor 305 to the N-channel enhancement MOS transistor 309, and from the N-channel depletion MOS transistor 03 to the ED-type reference circuit 3 1 0 The path of the two paths flows current, so the disadvantage is that the consumption current increases. In order to solve the above problems, the present invention has been made to realize a reference voltage circuit that operates at a lower consumption current without deteriorating the low voltage operation or the power supply voltage variation. (Means for Solving the Problem) In order to solve the conventional problem, the reference voltage circuit of the present invention is provided with a vacant transistor for splicing, and a plurality of vacant transistors are used to form a vacant transistor that determines a reference voltage, and the first vacant cell is used. The junction of the drain of the transistor and the source of the second vacant transistor is connected to the gate terminal of the vacant transistor for splicing. [Effects of the Invention] The reference voltage circuit of the present invention can provide a reference voltage circuit that operates at a lower consumption current without deteriorating the low voltage operation or the power supply voltage fluctuation removal ratio as compared with the conventional circuit. [Embodiment] Fig. 1 is a circuit diagram showing a first embodiment of a reference voltage circuit according to the present invention. The reference voltage circuit of the present embodiment includes: a power supply terminal 1 0 1 , a 201106126 GND terminal 100, an N-channel enhancement type MOS transistor 1, an N-channel depletion type MOS transistor 2, and an N-channel depletion. The MOS transistor 3, the N-channel depletion MOS transistor 4, and the output terminal 102.

N通道空乏型MOS電晶體2與N通道空乏型MOS電 晶體3是共通連接閘極，且被串連。更與N通道增強型 MOS電晶體1，共通連接閘極，且被串連。亦即，N通道 增強型MOS電晶體1與N通道空乏型MOS電晶體2及N 通道空乏型MOS電晶體3是構成ED型基準電壓電路110 〇 N通道空乏型MOS電晶體4是將閘極連接至N通道 空乏型MOS電晶體2的汲極及N通道空乏型MOS電晶體 3的源極，將源極連接至N通道空乏型MOS電晶體3的 汲極，將汲極連接至電源端子1 〇 1，後閘極是被連接至 GND端子100。亦即，N通道空乏型MOS電晶體4是對 ED型基準電壓電路110具有作爲疊接電路（casc〇de circuit)的 機能。 ED型基準電壓電路110是以N通道空乏型MOS電晶 體2的源極與N通道增強型MOS電晶體1的汲極的連接The N-channel depleted MOS transistor 2 and the N-channel depletion MOS transistor 3 are commonly connected to the gate and are connected in series. Further, the N-channel enhancement type MOS transistor 1 is commonly connected to the gate and is connected in series. That is, the N-channel enhancement type MOS transistor 1 and the N-channel depletion type MOS transistor 2 and the N-channel depletion type MOS transistor 3 constitute an ED-type reference voltage circuit 110. The N-channel depletion type MOS transistor 4 is a gate electrode. The source of the drain of the N-channel depletion MOS transistor 2 and the source of the N-channel depletion MOS transistor 3 is connected to the drain of the N-channel depletion MOS transistor 3, and the drain is connected to the power supply terminal 1 〇1, the back gate is connected to the GND terminal 100. That is, the N-channel depletion MOS transistor 4 has a function as a cascode circuit for the ED type reference voltage circuit 110. The ED type reference voltage circuit 110 is connected to the drain of the N-channel depletion MOS transistor 2 and the drain of the N-channel enhancement type MOS transistor 1.

點作爲輸出端子》又，N通道空乏型MOS電晶體2與N 通道空乏型MOS電晶體3是以1個以上的電晶體所構成 〇 在上述的電路中，N通道空乏型MOS電晶體4的閘 極是被連接至N通道空乏型MOS電晶體3的源極與N通 201106126 道空乏型MOS電晶體2的汲極，所以N通道空乏型MOS 電晶體4的閘極的電位是可比N通道空乏型MOS電晶體 3的汲極-源極間電壓部分，源極的電位低。 在此因爲N通道空乏型MOS電晶體4的閘極電位比 源極電位更低，所以成爲Vgs4<0，與以往的構成同樣， 不用另外準備臨界値低的N通道空乏型MOS電晶體，可 降低最低動作電壓VDD (min)。而且，只在N通道增強型 MOS電晶體1、N通道空乏型MOS電晶體2、N通道空乏 型MOS電晶體3、N通道空乏型MOS電晶體4的路徑流 動電流，所以相較於使用偏壓電路的以往電路，可降低消 費電流。 另外，Ν通道空乏型MOS電晶體2的後閘極（Back Gate)亦可連接至N通道空乏型MOS電晶體2的源極。N 通道空乏型MOS電晶體3的後閘極亦可連接至N通道空 乏型MOS電晶體3的源極或N通道空乏型MOS電晶體2 的源極。 在圖2顯示第二實施形態的基準電壓電路的電路圖。 第二實施形態是具備2個第一實施形態的基準電壓電路， 構成可使相等的基準電壓從2處的輸出端子輸出之基準電 壓電路。 第2實施形態的基準電壓電路是具備：電源端子1 0 1 、GND端子100、N通道增強型MOS電晶體1、N通道增 強型MOS電晶體5、N通道空乏型MOS電晶體2、N通道 空乏型MOS電晶體3、N通道空乏型MOS電晶體4、N通 -9 - 201106126 道空乏型MOS電晶體6、N通道空乏型MOS電晶體7、 通道空乏型MOS電晶體8、輸出端子102及輸出端子1 〇 N通道空乏型MOS電晶體2與N通道空乏型MOS 晶體3是共通連接閘極，且被串連。更與N通道增強 MOS電晶體1，共通連接閘極，且被串連。亦即，N通 增強型MOS電晶體1與N通道空乏型MOS電晶體2及 通道空乏型MOS電晶體3是構成ED型基準電壓電路1 〇 同樣，N通道空乏型MOS電晶體6與N通道空乏 MOS電晶體7是共通連接閘極，且被串連。更與N通 增強型MOS電晶體5，共通連接閘極，且被串連。亦即 N通道增強型MOS電晶體5與N通道空乏型MOS電晶 6及N通道空乏型MOS電晶體7是構成ED型基準電壓 路1 U。 N通道空乏型MOS電晶體4是將閘極連接至N通 空乏型MOS電晶體6的汲極及N通道空乏型MOS電晶 7的源極，將源極連接至N通道空乏型MOS電晶體3 汲極，將汲極連接至電源端子1 〇1，後閘極是被連接 GND端子100。亦即，N通道空乏型MOS電晶體4是 ED型基準電壓電路110具有作爲疊接電路的機能。 N通道空乏型MOS電晶體8是將閘極連接至N通 空乏型MOS電晶體2的汲極及N通道空乏型MOS電晶 3的源極，將源極連接至N通道空乏型MOS電晶體7 N 03 電 型 道 N 10 型 道 體 電 道 體 的 至 對 道 體 的 -10 - 201106126 汲極’將汲極連接至電源端子1 0 1，後閘極是被連接至 GND端子100。亦即’ N通道空乏型MOS電晶體8是對 ED型基準電壓電路U1具有作爲疊接電路的機能。 ED型基準電壓電路11〇是以n通道空乏型MOS電晶 體2的源極與N通道增強型m〇S電晶體1的汲極的連接Point as an output terminal", the N-channel depletion MOS transistor 2 and the N-channel depletion MOS transistor 3 are constituted by one or more transistors, and in the above-described circuit, the N-channel depletion MOS transistor 4 The gate is connected to the source of the N-channel depletion MOS transistor 3 and the drain of the N-pass 201106126-channel depletion MOS transistor 2, so the potential of the gate of the N-channel depletion MOS transistor 4 is comparable to the N-channel The drain-source voltage portion of the depletion MOS transistor 3 has a low potential of the source. Here, since the gate potential of the N-channel depletion MOS transistor 4 is lower than the source potential, Vgs4 < 0, similarly to the conventional configuration, it is not necessary to separately prepare an N-channel depletion MOS transistor having a critically low value. Lower the minimum operating voltage VDD (min). Moreover, the current flows only in the path of the N-channel enhancement type MOS transistor 1, the N-channel depletion MOS transistor 2, the N-channel depletion MOS transistor 3, and the N-channel depletion MOS transistor 4, so that it is compared with the use bias The previous circuit of the voltage circuit can reduce the consumption current. In addition, the back gate of the Ν channel depletion MOS transistor 2 may be connected to the source of the N-channel depletion MOS transistor 2. The rear gate of the N-channel depletion MOS transistor 3 can also be connected to the source of the N-channel depletion MOS transistor 3 or the source of the N-channel depletion MOS transistor 2. Fig. 2 is a circuit diagram showing a reference voltage circuit of the second embodiment. The second embodiment is a reference voltage circuit including two first embodiments, and constitutes a reference voltage circuit that can output equal reference voltages from two output terminals. The reference voltage circuit of the second embodiment includes a power supply terminal 1 0 1 , a GND terminal 100, an N-channel enhancement type MOS transistor 1, an N-channel enhancement type MOS transistor 5, an N-channel depletion type MOS transistor 2, and an N channel. Depleted MOS transistor 3, N-channel depleted MOS transistor 4, N-pass-9 - 201106126 Dao spent MOS transistor 6, N-channel depletion MOS transistor 7, channel depletion MOS transistor 8, output terminal 102 And the output terminal 1 〇 N channel depletion MOS transistor 2 and the N channel depletion MOS crystal 3 are commonly connected to the gate and are connected in series. Further, the N-channel enhancement MOS transistor 1 is commonly connected to the gate and is connected in series. That is, the N-channel MOS transistor 1 and the N-channel depletion MOS transistor 2 and the channel depletion MOS transistor 3 constitute the ED-type reference voltage circuit 1 〇, the N-channel depletion MOS transistor 6 and the N channel The depleted MOS transistor 7 is commonly connected to the gate and is connected in series. Further, the N-channel enhanced MOS transistor 5 is commonly connected to the gate and is connected in series. That is, the N-channel enhancement type MOS transistor 5 and the N-channel depletion type MOS transistor 6 and the N-channel depletion type MOS transistor 7 constitute an ED type reference voltage path 1 U. The N-channel depletion MOS transistor 4 is a source for connecting the gate to the drain of the N-channel depletion MOS transistor 6 and the source of the N-channel depletion MOS transistor 7, and connecting the source to the N-channel depletion MOS transistor 3 Bungee, connect the drain to the power terminal 1 〇1, and the back gate is connected to the GND terminal 100. That is, the N-channel depletion MOS transistor 4 is an ED type reference voltage circuit 110 having a function as a splicing circuit. The N-channel depletion MOS transistor 8 is a source for connecting the gate to the drain of the N-channel depletion MOS transistor 2 and the source of the N-channel depletion MOS transistor 3, and connecting the source to the N-channel depletion MOS transistor 7 N 03 Electrical path N 10 type body body body to the opposite body -10 - 201106126 The drain pole connects the drain to the power terminal 1 0 1, and the rear gate is connected to the GND terminal 100. That is, the 'N-channel depletion type MOS transistor 8 has a function as a splicing circuit for the ED type reference voltage circuit U1. The ED type reference voltage circuit 11 is connected to the drain of the n-channel depletion MOS transistor 2 and the drain of the N-channel enhancement type m〇S transistor 1.

點作爲輸出端子。並且，N通道空乏型MOS電晶體2與N 通道空乏型MOS電晶體3是以1個以上的電晶體所構成 〇 ED型基準電壓電路lu是以n通道空乏型MOS電晶 體ό的源極與N通道增強型m〇S電晶體5的汲極的連接 點作爲輸出端子。並且，Ν通道空乏型MOS電晶體6與Ν 通道空乏型MOS電晶體7是以1個以上的電晶體所構成 〇 在上述的電路中，也因爲Ν通道空乏型MOS電晶體 4的閘極是被連接至Ν通道空乏型MOS電晶體7的源極 及Ν通道空乏型MOS電晶體6的汲極，所以Ν通道空乏 型MOS電晶體4的閘極的電位可比Ν通道空乏型MOS電 晶體7的汲極一源極間電壓部分，源極的電位低。又，由 於Ν通道空乏型MOS電晶體8的閘極是被連接至Ν通道 空乏型MOS電晶體3的源極及Ν通道空乏型MOS電晶體 2的汲極，所以Ν通道空乏型MOS電晶體8的閘極的電 位可比Ν通道空乏型M OS電晶體3的汲極-源極間電壓部 分，源極的電位低。 在此因爲Ν通道空乏型MOS電晶體4的閘極電位比 -11 - 201106126 源極電位更低，所以成爲Vgs4<0，可降低最低動作電壓 VDD(min)。又，有關N通道空乏型MOS電晶體8也是同 樣鬧極電位比源極電位更低，所以成爲Vgs8<0，可降低 最低動作電壓VDD(min)。然後，輸出是可從輸出端子102 及輸出端子103的2處取得同樣的基準電壓。而且，對於 2處的基準電壓的輸出，由於不需要供給偏壓電壓的電路 ，只在2路徑流動電流，因此相較於以往的構成，可降低 消費電流。 另外，N通道空乏型MOS電晶體2的後閘極亦可連 接至N通道空乏型MOS電晶體2的源極。N通道空乏型 MOS電晶體3的後閘極亦可連接至N通道空乏型MOS電 晶體3的源極或N通道空乏型MOS電晶體2的源極。 又，N通道空乏型MOS電晶體6的後閘極亦可連接 至N通道空乏型MOS電晶體6的源極。N通道空乏型 MOS電晶體7的後閘極亦可連接至N通道空乏型MOS電 晶體7的源極或N通道空乏型MOS電晶體6的源極》 在圖3顯示第三實施形態的基準電壓電路的電路圖。 在此，Μ是〇或正的整數，4的倍數，N與P是0或正的 整數。第三實施形態是具備複數個第一實施形態的基準電 壓電路，構成可從複數處的輸出端子輸出相等的基準電壓 之基準電壓電路。 Ν通道空乏型MOS電晶體2與Ν通道空乏型MOS電 晶體3是共通連接閘極，且被串連。更與Ν通道增強型 MOS電晶體1，共通連接閘極，且被串連。亦即，Ν通道 -12- 201106126Point as an output terminal. Further, the N-channel depletion MOS transistor 2 and the N-channel depletion MOS transistor 3 are formed of one or more transistors. The ED-type reference voltage circuit is a source of an n-channel depletion MOS transistor. The connection point of the drain of the N-channel enhancement type m〇S transistor 5 serves as an output terminal. Further, the Ν channel depletion MOS transistor 6 and the 通道 channel depletion MOS transistor 7 are constituted by one or more transistors in the above-described circuit, and also because the gate of the Ν channel depletion MOS transistor 4 is It is connected to the source of the Ν channel depletion MOS transistor 7 and the drain of the Ν channel depletion MOS transistor 6, so the potential of the gate of the Ν channel depletion MOS transistor 4 can be compared with that of the Ν channel depletion MOS transistor 7 The voltage between the drain and the source is low, and the potential of the source is low. Further, since the gate of the erbium channel depletion MOS transistor 8 is connected to the source of the Ν channel depletion MOS transistor 3 and the drain of the Ν channel depletion MOS transistor 2, the Ν channel depletion MOS transistor The potential of the gate of 8 may be lower than the voltage between the drain and the source of the Ν channel depleted M OS transistor 3, and the potential of the source is low. Here, since the gate potential of the Ν channel depletion MOS transistor 4 is lower than the source potential of -11 - 201106126, Vgs4 < 0 can lower the minimum operating voltage VDD (min). Further, the N-channel depletion MOS transistor 8 has the same noise potential lower than the source potential, so that Vgs8 < 0 can lower the minimum operating voltage VDD (min). Then, the output is such that the same reference voltage can be obtained from two places of the output terminal 102 and the output terminal 103. Further, since the output of the reference voltage at two places does not require a circuit for supplying a bias voltage, current flows only in two paths, so that the consumption current can be reduced as compared with the conventional configuration. Further, the rear gate of the N-channel depletion MOS transistor 2 can also be connected to the source of the N-channel depletion MOS transistor 2. The rear gate of the N-channel depletion MOS transistor 3 can also be connected to the source of the N-channel depletion MOS transistor 3 or the source of the N-channel depletion MOS transistor 2. Further, the rear gate of the N-channel depletion MOS transistor 6 may be connected to the source of the N-channel depletion MOS transistor 6. The rear gate of the N-channel depletion MOS transistor 7 may be connected to the source of the N-channel depletion MOS transistor 7 or the source of the N-channel depletion MOS transistor 6". The reference of the third embodiment is shown in FIG. Circuit diagram of the voltage circuit. Here, Μ is a 〇 or positive integer, a multiple of 4, and N and P are 0 or a positive integer. The third embodiment is a reference voltage circuit including a plurality of reference voltage circuits of the first embodiment, and configured to output equal reference voltages from the output terminals of the plurality of terminals. The Ν channel depletion MOS transistor 2 and the Ν channel depletion MOS transistor 3 are commonly connected to the gate and are connected in series. Further, the Ν channel-enhanced MOS transistor 1 is commonly connected to the gate and is connected in series. That is, the channel -12- 201106126

增強型MOS電晶體1與N通道空乏型MOS電晶體2及N 通道空乏型MOS電晶體3是構成ED型基準電壓電路110 〇 同樣，N通道空乏型MOS電晶體6與N通道空乏型 MOS電晶體7是共通連接閘極，且被串連。更與N通道 增強型MOS電晶體5，共通連接閘極，且被串連。亦即， N通道增強型MOS電晶體5與N通道空乏型MOS電晶體 6及N通道空乏型MOS電晶體7是構成ED型基準電壓電 路 1 1 1。 更具備複數個形成同樣構成的基準電壓電路。 N通道空乏型MOS電晶體4是將閘極連接至N通道 空乏型MOS電晶體6的汲極及N通道空乏型MOS電晶體 7的源極，將源極連接至N通道空乏型MOS電晶體3的 汲極，將汲極連接至電源端子1 01，後閘極是被連接至 GND端子100。亦即，N通道空乏型MOS電晶體4是對 ED型基準電壓電路110具有作爲疊接電路的機能。 N通道空乏型MOS電晶體8是將源極連接至N通道 空乏型MOS電晶體7，將汲極連接至電源端子1 0 1，將後 閘極連接至GND端子100。亦即，N通道空乏型MOS電 晶體8是對ED型基準電壓電路111具有作爲疊接電路的 機能。然後，N通道空乏型MOS電晶體8的閘極是被連 接至未圖示之其次的基準電壓電路的N通道空乏型MOS 電晶體1 1的汲極及N通道空乏型MOS電晶體1 0的源極 -13- 201106126 形成同樣的構成之最後的基準電壓電路是將具有作爲 疊接電路機能的N通道空乏型MOS電晶體M + 4的閘極連 接至最初的基準電壓電路的N通道空乏型MOS電晶體2 的汲極及N通道空乏型MOS電晶體3的源極。 ED型基準電壓電路P+110是以N通道空乏型MOS電 晶體M + 2的源極與N通道增強型MOS電晶體M+1的汲極 的連接點作爲輸出端子。又，N通道空乏型MOS電晶體 M + 2與N通道空乏型MOS電晶體M + 3是以1個以上的電 晶體所構成。 在上述的電路中，也是因爲全部的基準電壓電路的疊 接電晶體的閘極電位比源極電位更低，所以成爲 Vgs4<0 ，可降低最低動作電壓 VDD(miη)。然後，可從複數處的 輸出端子Ν + 102(Ν爲正的整數）取得同樣的基準電壓。而 且，對於複數處的基準電壓的輸出，因爲不需要供給偏壓 電壓的電路，所以相較於以往的構成，可降低消費電流。 另外，Ν通道空乏型MOS電晶體Μ + 2的後閘極亦可 連接至Ν通道空乏型MOS電晶體Μ + 2的源極。Ν通道空 乏型MOS電晶體Μ + 3的後閘極亦可連接至Ν通道空乏型 MOS電晶體Μ + 3的源極或Ν通道空乏型MOS電晶體Μ + 2 的源極。 如以上説明，若根據本發明的基準電壓電路’則與以 往的電路作比較，可提供一種不使低電壓動作或電源電壓 變動除去比惡化’以更低的消費電流來動作的基準電壓電 路。 -14- 201106126 【圖式簡單說明】 圖1是表示本發明的基準電壓電路的第一實施形態的 電路圖。 圖2是表示本發明的基準電壓電路的第二實施形態的 電路圖。 圖3是表示本發明的基準電壓電路的第三實施形態的 電路圖。 圖4是表示以往的基準電壓電路的電路圖。 【主要元件符號說明】 1 〇 1 :電源端子 1 0 0 : G N D 端子 102、103、N+102:基準電壓輸出端子 110、111、P+110、310: ED型基準電壓電路 3 1 1 :偏壓電路 -15-The enhanced MOS transistor 1 and the N-channel depletion MOS transistor 2 and the N-channel depletion MOS transistor 3 constitute the ED-type reference voltage circuit 110. Similarly, the N-channel depletion MOS transistor 6 and the N-channel depletion MOS The crystals 7 are commonly connected to the gates and are connected in series. Further, the N-channel enhanced MOS transistor 5 is commonly connected to the gate and is connected in series. That is, the N-channel enhancement type MOS transistor 5 and the N-channel depletion type MOS transistor 6 and the N-channel depletion type MOS transistor 7 constitute an ED type reference voltage circuit 1 1 1 . Further, a plurality of reference voltage circuits having the same configuration are provided. The N-channel depletion MOS transistor 4 is a source connecting the gate to the drain of the N-channel depletion MOS transistor 6 and the source of the N-channel depletion MOS transistor 7, and connects the source to the N-channel depletion MOS transistor. The drain of 3 connects the drain to the power supply terminal 101, and the rear gate is connected to the GND terminal 100. That is, the N-channel depletion MOS transistor 4 has a function as a splicing circuit for the ED type reference voltage circuit 110. The N-channel depletion MOS transistor 8 has a source connected to the N-channel depletion MOS transistor 7, a drain connected to the power supply terminal 1 0 1, and a rear gate connected to the GND terminal 100. That is, the N-channel depletion MOS transistor 8 has a function as a splicing circuit for the ED-type reference voltage circuit 111. Then, the gate of the N-channel depletion MOS transistor 8 is a drain of the N-channel depletion MOS transistor 11 connected to the next reference voltage circuit not shown, and the N-channel depletion MOS transistor 10 Source-13- 201106126 The final reference voltage circuit that forms the same configuration is an N-channel depletion type that connects the gate of the N-channel depletion MOS transistor M + 4 having the function of the splicing circuit to the original reference voltage circuit. The drain of the MOS transistor 2 and the source of the N-channel depletion MOS transistor 3. The ED type reference voltage circuit P+110 is an output terminal of a connection point between a source of the N-channel depletion MOS transistor M + 2 and a drain of the N-channel enhancement type MOS transistor M+1. Further, the N-channel depletion MOS transistor M + 2 and the N-channel depletion MOS transistor M + 3 are composed of one or more transistors. Also in the above circuit, since the gate potential of the stacked transistors of all the reference voltage circuits is lower than the source potential, Vgs4 < 0 can lower the minimum operating voltage VDD (miη). Then, the same reference voltage can be obtained from the output terminal Ν + 102 (Ν is a positive integer) at the complex point. Further, since the output of the reference voltage at the plurality of points does not require a circuit for supplying the bias voltage, the consumption current can be reduced as compared with the conventional configuration. In addition, the back gate of the Ν channel depletion MOS transistor Μ + 2 can also be connected to the source of the Ν channel depletion MOS transistor Μ + 2. The back gate of the Ν channel MOS transistor 3 + 3 can also be connected to the source of the Ν channel depletion MOS transistor Μ + 3 or the source of the Ν channel depletion MOS transistor Μ + 2 . As described above, the reference voltage circuit ' according to the present invention can provide a reference voltage circuit that operates at a lower consumption current without deteriorating the low voltage operation or the power supply voltage fluctuation as compared with the conventional circuit. -14-201106126 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing a first embodiment of a reference voltage circuit of the present invention. Fig. 2 is a circuit diagram showing a second embodiment of the reference voltage circuit of the present invention. Fig. 3 is a circuit diagram showing a third embodiment of the reference voltage circuit of the present invention. 4 is a circuit diagram showing a conventional reference voltage circuit. [Description of main component symbols] 1 〇1: Power supply terminal 1 0 0 : GND Terminals 102, 103, N+102: Reference voltage output terminals 110, 111, P+110, 310: ED type reference voltage circuit 3 1 1 : Partial Pressure circuit-15-

Claims (1)

201106126 七、申請專利範圍： 1. 一種基準電壓電路，係具備： ED型基準電壓電路，其係具有彼此連接閘極的N通 道空乏型MOS電晶體與N通道增強型MOS電晶體；及 疊接電路，其係設於電源端子與前述ED型基準電壓 電路之間， 其特徵爲： 前述N通道空乏型MOS電晶體係由被串連的複數個 N通道空乏型MOS電晶體所構成， 前述疊接電路係由將閘極與前述串連的複數個N通道 空乏型MOS電晶體的連接點的其中任一個連接的N通道 空乏型MOS電晶體所構成。 2 .如申請專利範圍第1項之基準電壓電路，其中，前 述ED型基準電壓電路係具有： 前述N通道增強型MOS電晶體，其係將汲極及閘極 連接至輸出端子，將源極連接至GND端子； 第1 N通道空乏型MOS電晶體，其係將源極及閘極連 接至前述輸出端子；及 第2N通道空乏型MOS電晶體，其係將閘極連接至前 述輸出端子，將源極連接至前述第1N通道空乏型MOS電 晶體的汲極， 前述疊接電路係具有：將汲極連接至前述電源端子， 將閘極與前述第1 N通道空乏型MOS電晶體的汲極和前述 第2N通道空乏型MOS電晶體的源極連接之第3N通道空 -16- 201106126 乏型Μ O S電晶體。 3 .如申請專利範圍第2項之基準電壓電路， 述第1N通道空乏型MOS電晶體與第2N通道空 電晶體的哪個或雙方，係以複數的N通道空乏！ 晶體所構成。 4. 一種基準電壓電路，係具備η個（η爲2 )ED型基準電壓電路及疊接電路的基準電壓電g 型基準電壓電路係具有彼此連接閘極的N通 MOS電晶體與N通道增強型MOS電晶體，該i 設於電源端子與前述ED型基準電壓電路之間， 其特徵爲= 前述N通道空乏型MOS電晶體係由串連的 通道空乏型MOS電晶體所構成， 前述疊接電路係由N通道空乏型MOS電晶 第m(m爲0<m<n的整數）個的疊接電路的N 型MOS電晶體係將閘極與第m+Ι個的ED型g 路的前述被串連的複數的N通道空乏型MOS 接點的其中任一個連接， 第η個的疊接電路的N通道空乏型MOS 1 閘極與第1個的ED型基準電壓電路的前述被_ 的Ν通道空乏型MOS電晶體的連接點的其中仨 〇 5 .如申請專利範圍第4項之基準電壓電路， 其中，前 乏型MOS ! MOS 電 上的整數 卜該ED 道空乏型 接電路係 複數的Ν 體所構成 通道空乏 準電壓電 晶體的連 晶體係將 連的複數 一個連接 其中，前 -17- 201106126 述ED型基準電壓電路係具有： 前述N通道增強型MOS電晶體，其係將汲極及閘極 連接至輸出端子，將源極連接至GND端子； 第1N通道空乏型MOS電晶體，其係將源極及閘極連 接至前述輸出端子；及 第2N通道空乏型MOS電晶體，其係將閘極連接至前 述輸出端子，將源極連接至前述第1N通道空乏型MOS電 晶體的汲極， 前述疊接電路係具有：將汲極連接至前述電源端子， 將閘極與前述第1N通道空乏型MOS電晶體的汲極和前述 第2N通道空乏型M0S電晶體的源極連接之第3N通道空 乏型MOS電晶體》 6. 如申請專利範圍第5項之基準電壓電路，其中，前 述第1N通道空乏型m〇S電晶體與第2N通道空乏型MOS 電晶體的哪個或雙方，係以複數的N通道空乏型MOS電 晶體所構成。 7. —種電子機器，其特徵係具有如申請專利範圍第 1〜6項中的任一項所記載之基準電壓電路。 -18-201106126 VII. Patent application scope: 1. A reference voltage circuit having: an ED type reference voltage circuit, which is an N-channel depleted MOS transistor and an N-channel enhancement type MOS transistor having gates connected to each other; and splicing The circuit is disposed between the power supply terminal and the ED-type reference voltage circuit, and is characterized in that: the N-channel depletion MOS electro-crystal system is composed of a plurality of N-channel depletion MOS transistors connected in series, and the stack The connection circuit is constituted by an N-channel depletion MOS transistor in which a gate is connected to any one of a connection point of a plurality of N-channel depletion MOS transistors connected in series. 2. The reference voltage circuit of claim 1, wherein the ED type reference voltage circuit has: the N-channel enhancement type MOS transistor, wherein the drain and the gate are connected to the output terminal, and the source is Connected to the GND terminal; a first N-channel depletion MOS transistor connecting a source and a gate to the output terminal; and a 2N-channel depletion MOS transistor connecting the gate to the output terminal Connecting the source to the drain of the first NN depletion MOS transistor, the splicing circuit having: connecting the drain to the power terminal, and connecting the gate to the first N-channel depletion MOS transistor The 3N channel of the pole connected to the source of the aforementioned 2N-channel depletion MOS transistor is -16106200126. 3. If the reference voltage circuit of the second application of the patent scope is described, which one or both of the 1N-channel depletion MOS transistor and the 2N-channel crystal cell are used, a plurality of N-channels are depleted! The crystal is composed. 4. A reference voltage circuit comprising: n (η is 2) ED type reference voltage circuits and a reference circuit electric reference g-type reference voltage circuit having N-pass MOS transistors and N-channel enhancements connected to each other The MOS transistor is disposed between the power supply terminal and the ED-type reference voltage circuit, and is characterized in that: the N-channel depletion MOS electro-crystal system is composed of a series of channel depletion MOS transistors, and the splicing The circuit is an N-type MOS electro-crystal system of a N-channel depletion MOS transistor with m (m is an integer of 0 < m < n), and the gate is connected with the m+th ED-type g-path Any one of the plurality of N-channel depletion type MOS contacts connected in series, the n-channel depletion type MOS 1 gate of the nth stacked circuit and the first ED type reference voltage circuit are _ The connection point of the Ν channel depletion MOS transistor is 仨〇5. The reference voltage circuit of the fourth application of the patent scope, wherein the front-deficient MOS! MOS is an integer on the ED channel. The connection of the vacancies of the vacancies The crystal system connects a plurality of connected ones. The ED type reference voltage circuit described in the above -17-201106126 has: the aforementioned N-channel enhanced MOS transistor, which connects the drain and the gate to the output terminal, and connects the source. To the GND terminal; the 1N-channel depletion MOS transistor, which connects the source and the gate to the output terminal; and the 2N-channel depletion MOS transistor, which connects the gate to the output terminal, and the source The pole is connected to the drain of the first NN channel depletion MOS transistor, and the stacking circuit has a drain connected to the power terminal, a gate and a drain of the first N-channel depletion MOS transistor, and the foregoing The 3N-channel depletion MOS transistor in which the source of the 2N-channel depletion type MOS transistor is connected. 6. The reference voltage circuit according to claim 5, wherein the 1N-channel depletion type m〇S transistor and Which one or both of the 2N-channel depletion MOS transistors are formed by a plurality of N-channel depletion MOS transistors. An electronic device characterized by having a reference voltage circuit as described in any one of claims 1 to 6. -18-
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KR101355684B1 (en) 2014-01-27
US8212545B2 (en) 2012-07-03
JP2011029912A (en) 2011-02-10
CN101963819B (en) 2014-06-25
TWI474150B (en) 2015-02-21
JP5306094B2 (en) 2013-10-02
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US20110018520A1 (en) 2011-01-27
CN101963819A (en) 2011-02-02

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