JP4703406B2 - Reference voltage generation circuit and semiconductor integrated device - Google Patents

Description

  The present invention relates to a reference voltage generation circuit and a semiconductor integrated device.

  In recent years, with the spread of mobile devices such as mobile phones, a reference voltage generation circuit having a high power supply voltage fluctuation removal ratio (reference voltage fluctuation ratio with respect to power supply voltage fluctuation) is required to prevent malfunction of logic circuits and the like. Yes.

  Conventionally, as a reference voltage generation circuit used for this requirement, a circuit in which a first depletion type MOS transistor, an enhancement type MOS transistor, and a second depletion type MOS transistor are connected in series is known (for example, Patent Documents). 1).

In the reference voltage generating circuit disclosed in Patent Document 1, the drain of the first depletion type MOS transistor is connected to the source of the second depletion type MOS transistor, and the gate and the source are short-circuited. In the enhancement type MOS transistor, the drain is connected to the source of the first depletion type MOS transistor, the gate and the drain are short-circuited, and the source is connected to the first potential. In the second depletion type MOS transistor, the drain is connected to the second potential, and the gate and the source are short-circuited.
Further, the back gates of the first and second depletion type MOS transistors and the enhancement type MOS transistor are respectively connected to the first potential.

The circuit current is determined by the first depletion type MOS transistor, and the determined current is supplied to the enhancement type MOS transistor whose drain and gate are short-circuited to generate the reference voltage.
In the second depletion type MOS transistor, the power supply voltage fluctuation elimination ratio at a low frequency is improved by fixing the potential of the back gate to the ground potential.

  However, since the reference voltage generating circuit disclosed in Patent Document 1 has the gate and the source of the second depletion type MOS transistor short-circuited, the high frequency fluctuation component superimposed on the power supply voltage is caused by the drain of the second depletion type MOS transistor. -It reaches the output terminal of the reference voltage via the parasitic capacitance between the gates.

As a result, there is a problem that the power supply voltage fluctuation removal ratio decreases as the frequency increases, and a sufficient power supply voltage fluctuation removal ratio cannot be obtained in the high frequency region.
JP-A-11-135732

  The present invention provides a reference voltage generating circuit and a semiconductor integrated device that can obtain a sufficient power supply voltage fluctuation rejection ratio.

A reference voltage generation circuit of one embodiment of the present invention includes a depletion-type first insulated gate field effect transistor having a drain connected to a first potential, a drain connected to a source of the first insulated gate field effect transistor, A depletion type second insulated gate field effect transistor having a gate connected to the source, a drain connected to the source of the second insulated gate field effect transistor, a gate short-circuited to the drain, and a source at the second potential A connected enhancement type third insulated gate field effect transistor, a depletion having a drain connected to the first potential, a gate connected to the gate of the first insulated gate field effect transistor, and a source connected to the gate Type fourth insulated gate field effect transistor and drain connected to the fourth isolation gate Is connected to the source of the gate field effect transistor, a gate connected to the gate of said third insulated gate field effect transistor, and a fifth insulated gate field effect transistor a source of the connected enhancement type to the second potential, the It is characterized by having.

The semiconductor integrated device of one embodiment of the present invention includes at least a depletion-type first insulated gate field effect transistor having a drain connected to a first potential, and a drain connected to a source of the first insulated gate field effect transistor. A depletion type second insulated gate field effect transistor having a gate connected to the source, a drain connected to the source of the second insulated gate field effect transistor, a gate connected to the drain, and a source connected to the second potential An enhancement-type third insulated gate field effect transistor connected to the drain , a drain connected to the first potential, a gate connected to the gate of the first insulated gate field effect transistor, and a source connected to the gate A depletion type fourth insulated gate field effect transistor and a drain An enhancement type fifth insulated gate field effect in which the fourth insulated gate field effect transistor is connected to the source, the gate is connected to the gate of the third insulated gate field effect transistor, and the source is connected to the second potential. The transistors are integrated and formed on the same chip.

  According to the present invention, it is possible to obtain a reference voltage generating circuit and a semiconductor integrated device that can obtain a sufficient power supply voltage fluctuation removal ratio.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a power supply circuit according to Embodiment 1 of the present invention.
As shown in FIG. 1, the reference voltage generating circuit 10 of this embodiment includes a depletion type first insulated gate field effect transistor M1 (hereinafter referred to as MOS transistor M1) connected in series and a depletion type second insulated gate electric field. An effect transistor M2 (hereinafter referred to as MOS transistor M2) and an enhancement type third insulated gate field effect transistor M3 (hereinafter referred to as MOS transistor M3) are connected in series with a first circuit 11 that generates a reference voltage Vref. A depletion type fourth insulated gate field effect transistor M4 (hereinafter referred to as MOS transistor M4) and an enhancement type fifth insulated gate field effect transistor M5 (hereinafter referred to as MOS transistor M5) are provided, and a predetermined gate is provided at the gate G1 of the MOS transistor M1. Give the potential of And it comprises a second circuit (voltage generation means) 12 for generating a voltage.

  The first circuit 11 and the second circuit 12 are connected between the power supply voltage Vdd (first potential) and the reference voltage GND (second potential), respectively. The first potential is set higher than the second potential.

  The conductivity types of the MOS transistors M1 to M3 of the first circuit 11 and the MOS transistors M4 and M5 of the second circuit 12 are all n-type.

Specifically, in the MOS transistor M1 of the first circuit 11, the drain D1 is connected to the power supply voltage Vdd, and the gate G1 is connected to the second circuit 12.
In the MOS transistor M2 of the first circuit 11, the drain D2 is connected to the source S1 of the MOS transistor M1, and the gate G2 and the source S2 are short-circuited.
In the MOS transistor M3 of the first circuit 11, the drain D3 is connected to the source S2 of the MOS transistor M2, the gate G3 and the drain D3 are short-circuited, and the source S3 is connected to the reference voltage GND.

In the MOS transistor M4 of the second circuit 12, the drain D4 is connected to the power supply voltage Vdd, the gate G4 is connected to the gate M1 of the MOS transistor M1, and the gate G4 and the source S4 are short-circuited.
In the MOS transistor M5 of the second circuit 12, the drain D5 is connected to the source S4 of the MOS transistor M4, the gate G5 is connected to the gate G3 of the MOS transistor M3, and the source S5 is connected to the reference voltage GND.

  The MOS transistor M2 of the first circuit 11 supplies the drain current Id2 when the gate-source voltage Vgs2 is 0 V to the MOS transistor M3 because the gate G2 and the source S2 are short-circuited.

  Since the MOS transistor M3 of the first circuit 11 is so-called diode-connected in which the gate G3 and the drain D3 are short-circuited, the MOS transistor M3 always operates in the saturation region, and the reference voltage Vref becomes equal to the gate-source voltage Vgs3.

Here, from the basic equation of the MOS transistor, the drain currents Id2 and Id3 of the MOS transistors M2 and M3 are expressed by the following equations.
Id2 = K2 × (Vgs2-Vth2) ² = K2 × (−Vth2) ² (1)
Id3 = K3 × (Vgs3-Vth3) ² (2)
Here, K represents a proportional constant, and Vth represents the threshold voltage of the MOS transistor.

Since the reference voltage Vref is equal to Vgs3, if equation (2) is modified,
Vref = Vgs3 = Vth3 + √ (Id3 / K3) (3)
From Id2 = Id3,
Vref = Vth3 + √ (K2 × (−Vth2) ² / K3)
= Vth3-Vth2√ (K2 / K3) (4)

Here, if the sizes of the MOS transistor M2 and the MOS transistor M3 are equal, K2 = K3, so the reference voltage Vref is expressed by the following equation.
Vref = Vth3-Vth2 (5)

The MOS transistor M5 of the second circuit 12 forms a current mirror circuit with the MOS transistor M3, and a current equal to the current flowing through the MOS transistor M3 flows.
The MOS transistor M4 of the second circuit 12 is connected in series with the MOS transistor M5, and a current equal to the current flowing through the MOS transistor M5 flows.
The MOS transistor M1 of the first circuit 11 is connected in series with the MOS transistor M3, and a current equal to the current flowing through the MOS transistor M3 flows.
Since a current equal to that of the MOS transistor M1 flows through the MOS transistor M4 of the second circuit 12, the gate-source voltage of the MOS transistor M4 and the gate-source voltage of the MOS transistor M1 are substantially equal.

  As a result, since the gate-source voltage of the MOS transistor M4 of the second circuit 12 is 0V, the gate-source voltage Vgs1 is almost 0V at the gate G1 of the MOS transistor M1 of the first circuit 11. A voltage is given.

  As a result, the predetermined reference voltage Vref is maintained, and the gate G1 and the source S1 of the MOS transistor M1 are not short-circuited, so that the high-frequency fluctuation component superimposed on the power supply voltage Vdd is the capacitance between the gate and drain of the MOS transistor M1. It is possible to suppress appearing at the reference voltage output terminal 13 via Cgd1.

FIG. 2 is a diagram showing the simulation result of the power supply voltage fluctuation removal ratio of the reference voltage generation circuit 10 in comparison with the conventional reference voltage generation circuit. In the figure, the solid line a is the present embodiment, and the broken line b is the conventional example. Is the case.
In FIG. 2, the vertical axis represents the power supply voltage fluctuation removal ratio (logarithm), and indicates that the power supply voltage fluctuation removal ratio is lower as the vertical axis is higher and the power supply voltage fluctuation removal ratio is higher as the lower vertical axis.

  The broken line c shows an example when the second circuit 12 is assumed to be an ideal voltage source having an internal resistance of zero and no frequency characteristics.

As is apparent from FIG. 2, in this embodiment, the power supply voltage fluctuation removal ratio is improved as the frequency increases, and shows a V-shaped frequency characteristic a that deteriorates at a specific frequency as a boundary.
On the other hand, the conventional example shows a monotonically decreasing frequency characteristic b in which the power supply voltage fluctuation rejection ratio deteriorates as the frequency increases.
Moreover, in an ideal voltage source, the power supply voltage fluctuation rejection ratio shows a monotonically increasing frequency characteristic c that increases as the frequency increases.

Specifically, in this embodiment, the power supply voltage fluctuation removal ratio shows a constant value (−66 dB) independent of the frequency in the low frequency region of about 10 to 100 Hz, and the frequency in the frequency region of about 100 to 10 kHz. In particular, the maximum value (−98 dB) is shown at the frequency d (8 kHz).
Although the power supply voltage fluctuation rejection ratio starts to deteriorate when the frequency exceeds d, it remains lower than a constant value (−66 dB) in the low frequency region up to about 20 kHz, and depends on the frequency in the frequency region of about 1 MHz or more. A constant value (−28 dB) is shown.

  On the other hand, in the conventional example, the power supply voltage fluctuation removal ratio shows a constant value (−66 dB) regardless of the frequency in the frequency region of about 10 to 1 kHz, and in the frequency region of about 1 kHz to 1 MHz. It worsens with the frequency range of about 1 MHz or more, and shows a constant value (−28 dB) regardless of the frequency.

  Further, in an ideal voltage source, the power supply voltage fluctuation removal ratio shows a constant value (−66 dB) regardless of the frequency in the frequency region of about 10 to 1 kHz, and in the frequency region of 1 kHz or more, similarly to this embodiment. The higher the frequency, the better.

  Thus, it is recognized that the reference voltage generation circuit 10 can obtain a higher power supply voltage fluctuation removal ratio than the conventional example in a wide frequency range from 100 Hz to 1 MHz.

FIG. 3 is a diagram showing a main part of an AC equivalent circuit of the reference voltage generation circuit 10 in which a MOS transistor is approximated by a drain-source small signal resistance and a drain-gate capacitance.
As shown in FIG. 3, in the low frequency region where the frequency of the high frequency fluctuation component superimposed on the power supply voltage Vdd is 10 kHz or less, the drain / gate capacitance Cdg1 of the MOS transistor M1 and the drain / gate capacitance Cdg3 of the MOS transistor M3 Since the impedance is high, the fluctuation component is sufficiently attenuated at the gate G1 terminal of the MOS transistor M1, and the constant voltage characteristic of the voltage of the gate G1 is maintained. As a result, the power supply voltage fluctuation removal ratio is improved as compared with the conventional example.

  Since the impedance of the drain / gate capacitances Cds1 and Cds4 decreases from the time when the frequency of the fluctuation component exceeds 10 kHz, the influence of the fluctuation component begins to appear at the gate G1 of the MOS transistor M1, and the constant voltage characteristic of the gate G1 is destroyed. As a result, the power supply voltage fluctuation removal ratio gradually deteriorates, and finally shows almost the same frequency characteristics as the conventional example.

FIG. 4 is a circuit diagram showing a configuration of a regulator using the reference voltage generation circuit 10.
As shown in FIG. 4, the regulator 20 includes a reference voltage generation circuit 10, a voltage dividing circuit 21 that divides the output voltage Vout by resistors R1 and R2 and outputs a feedback voltage Ver, and a reference voltage Vref and a feedback voltage Ver. And a differential amplifier 22 that performs feedback control so as to be equal.

  The reference voltage Vref is input from the reference voltage generating circuit 10 to the positive input terminal of the differential amplifier 22, and the feedback voltage Ver = Vout × R2 / (R1 + R2) is input from the voltage dividing circuit 21 to the negative input terminal.

  Since the differential amplifier 22 performs feedback control so that the reference voltage Vref and the feedback voltage Ver are equal, a constant output voltage Vout = Vref × (R1 + R2) / R2 is supplied to the load 23.

  For example, when the power supply voltage Vdd = 5V, the reference voltage Vref = 1.1V, and the voltage division ratio R2 / R1 = 1/3, the output voltage Vout = 3.3V is obtained.

FIG. 5 is a diagram showing a semiconductor integrated device having the regulator 20.
As shown in FIG. 5, the semiconductor integrated device 30 is formed by monolithically integrating a regulator 20 having a reference voltage generation circuit 10 on a semiconductor chip 31.

  Furthermore, the output voltage Vout of the regulator 20 is supplied, and an internal circuit 32 for executing predetermined information processing and the like, and an interface circuit 33 for inputting / outputting information and processing results to / from the internal circuit 32 are provided.

  Bonding pads 34a to 34d for connecting the interface circuit 33 and an external circuit (not shown) are formed.

  For example, the MOS transistors M1 to M5 of the reference voltage generation circuit 10 form a p-type well region in an n-type silicon substrate, and form an n-type drain region, an n-type source region, and a gate region in the p-type well region, respectively. Is formed.

  The depletion type MOS transistors M1, M2, and M4 are formed, for example, by implanting a very small amount of n-type impurity into the channel portion of the gate region.

The gate length and gate width of the MOS transistors M1 and M4 constituting the mirror circuit are preferably set to be equal to each other so that the mirror ratio is 1.
Similarly, the gate lengths and gate widths of the MOS transistors M3 and M5 constituting the mirror circuit are preferably set to be equal to each other so that the mirror ratio is 1.

  As described above, the reference voltage generation circuit 10 of this embodiment is configured such that the second circuit 12 causes the gate of the MOS transistor M1 to be connected to the gate of the MOS transistor M1 without short-circuiting the gate G1 and the source S1 of the first circuit 11. Since the voltage is applied so that the drain voltage Vgs1 is substantially 0 V, the reference voltage Vref is maintained, and the high frequency fluctuation component superimposed on the power supply voltage Vdd causes the gate-drain capacitance Cdg1 of the MOS transistor M1 to And appearing at the reference voltage output terminal 13 can be suppressed.

  As a result, the power supply voltage fluctuation removal ratio in the high frequency region is improved, and the frequency characteristics of the power supply voltage fluctuation removal ratio can be improved. Therefore, it is possible to provide a reference voltage generation circuit and a semiconductor integrated device that can obtain a sufficient power supply voltage fluctuation removal ratio.

  Further, since the potential relationship between the first circuit 11 and the second circuit 12 is uniquely determined, it is not affected by fluctuations in the power supply voltage Vdd itself and is suitable for the CMOS manufacturing process.

  FIG. 6 is a circuit diagram showing a configuration of a reference voltage generating circuit according to Embodiment 2 of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.

The present embodiment is different from the first embodiment in that the second circuit is constituted by a series circuit of a depletion type MOS transistor and a resistor.
That is, as shown in FIG. 6, the reference voltage generation circuit 40 of this embodiment includes a second circuit 42 having a MOS transistor M4 and a resistor R3 connected in series.
The resistor R3 of the second circuit 42 is connected between the source S4 of the transistor M4 and the reference voltage GND.

  The resistor R3 is set so that the gate-source voltage Vgs1 of the MOS transistor M1 is approximately 0V. Specifically, for example, the resistor R3 is set so that the voltage drop due to the drain current of the MOS transistor M4 becomes the sum of the reference voltage Vref and the drain-source voltage Vds2 of the MOS transistor M2.

  As a result, it is possible to maintain the reference voltage Vref and suppress high-frequency fluctuation components superimposed on the power supply voltage Vdd from appearing at the reference voltage output terminal 13 via the gate-drain capacitance Cgd1 of the MOS transistor M1. .

FIG. 7 is a diagram showing the simulation result of the power supply voltage fluctuation removal ratio of the reference voltage generation circuit 40 in comparison with the conventional reference voltage generation circuit. In FIG. Is the case.
A broken line c shows an example when the second circuit 42 is assumed to be an ideal voltage source having zero internal resistance and no frequency characteristics.

  As is apparent from FIG. 7, according to the present embodiment, the power supply voltage fluctuation rejection ratio shows the same V-shaped frequency characteristic as in FIG. 2, and in a wide frequency range from 100 Hz to 1 MHz, the power supply voltage is higher than that of the conventional example. It is possible to obtain a voltage fluctuation rejection ratio.

  According to the simulation, it is possible to change the frequency d at which the maximum power supply voltage fluctuation removal ratio is obtained by changing the resistance R3. For example, if the resistance R3 is reduced, the frequency d at which the maximum power supply voltage fluctuation removal ratio is obtained increases, so that the solid line a can be made closer to the broken line c.

  As described above, in the reference voltage generating circuit 40 of the present embodiment, the second circuit 42 is a series circuit of the MOS transistor M4 and the resistor R3. Therefore, the frequency characteristic of the power supply voltage fluctuation removal ratio is adjusted by the resistor R3. There is an advantage that becomes easier.

  FIG. 8 is a circuit diagram showing a configuration of a reference voltage generating circuit according to Embodiment 3 of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.

The present embodiment is different from the first embodiment in that the second circuit is constituted by a series circuit of resistors. That is, as shown in FIG. 8, the reference voltage generation circuit 50 of this embodiment includes a second circuit 52 having a resistor R4 (first resistor) and a resistor R3 (second resistor) connected in series.
One end of the resistor R4 is connected to the power supply voltage Vdd, and a connection point a between the resistors R4 and R3 is connected to the gate G1 of the MOS transistor M1 of the first circuit 11.

  The resistors R4 and R3 are set so that the gate-source voltage Vgs1 of the MOS transistor M1 is approximately 0V. Specifically, for example, it is preferable to set the resistor R3 and the resistor R4 so that the voltage Va at the connection point a becomes the sum of the reference voltage Vref and the drain-source voltage Vds2 of the MOS transistor M2.

  As a result, it is possible to maintain the reference voltage Vref and suppress high-frequency fluctuation components superimposed on the power supply voltage Vdd from appearing at the reference voltage output terminal 13 via the gate-drain capacitance Cgd1 of the MOS transistor M1. .

  As described above, in the reference voltage generation circuit 50 of the present embodiment, the second circuit 52 is a voltage dividing circuit using resistors connected in series, so that there is an advantage that the circuit configuration is simplified.

  FIG. 9 is a circuit diagram showing a configuration of a reference voltage generating circuit according to Embodiment 4 of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.

The present embodiment is different from the first embodiment in that the first and second circuits are composed of p-type MOS transistors.
That is, as shown in FIG. 9, the reference voltage generating circuit 60 includes a depletion type sixth insulated gate field effect transistor M6 (hereinafter referred to as MOS transistor M6) and a depletion type seventh insulated gate field effect transistor connected in series. A depletion type connected in series with a first circuit 61 having M7 (hereinafter referred to as MOS transistor M7) and an enhancement type eighth insulated gate field effect transistor M8 (hereinafter referred to as MOS transistor M8) and generating a reference voltage Vref. Nth insulated gate field effect transistor M9 (hereinafter referred to as MOS transistor M9) and an enhancement type tenth insulated gate field effect transistor M10 (hereinafter referred to as MOS transistor M10). Apply potential It is provided with a second circuit 62 for generating that voltage.

The first circuit 61 and the second circuit 62 are connected between the power supply voltage Vdd (first potential) and the reference voltage GND (second potential), respectively.
Here, the conductivity types of the MOS transistors M6 to M8 of the first circuit 61 and the MOS transistors M9 and M10 of the second circuit 62 are all p-type.

Specifically, in the MOS transistor M6 of the first circuit 61, the source S6 is connected to the power supply voltage Vdd, and the gate G6 and the drain D6 are short-circuited.
In the MOS transistor M7 of the first circuit 61, the source S7 is connected to the drain D6 of the MOS transistor M6, and the gate G7 and the source S7 are short-circuited.
In the MOS transistor M8 of the first circuit 61, the source S8 is connected to the drain D7 of the MOS transistor M7, the gate G8 is connected to the second circuit 62, and the drain D8 is connected to the reference voltage GND.

In the MOS transistor M9 of the second circuit 12, the source S9 is connected to the power supply voltage Vdd, and the gate G9 is connected to the gate G6 of the MOS transistor M6.
In the MOS transistor M10 of the second circuit 12, the source S10 is connected to the drain D9 of the MOS transistor M9, the gate G10 is connected to the gate G8 of the MOS transistor M8, the gate G10 and the source S10 are short-circuited, and the drain D10 is the reference voltage. Connected to GND.

  The reference voltage Vref is expressed by a difference between the threshold voltage Vth6 of the enhancement type MOS transistor M6 and the threshold voltage Vth7 of the depletion type MOS transistor M7 as measured from the power supply voltage Vdd.

  As a result, it is possible to obtain a high power supply voltage fluctuation removal ratio with respect to the high frequency fluctuation components that are superimposed on the power supply voltage and enter from the reference voltage GND side.

  As described above, in the reference voltage generating circuit 60 of the present embodiment, the first and second circuits are configured by p-type MOS transistors, and thus there is an advantage that the reference voltage Vref can be obtained with reference to the power supply voltage Vdd. .

  FIG. 10 is a circuit diagram showing a configuration of a reference voltage generating circuit according to Embodiment 5 of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.

The present embodiment is different from the first embodiment in that the second circuit is arranged outside.
That is, as shown in FIG. 10, the reference voltage generation circuit 70 is connected to the external voltage source Vex of the second circuit 72 in which the gate G1 of the MOS transistor M1 of the first circuit 11 is arranged outside via the external power supply connection terminal 73. Connected.

  The external voltage source Vex of the second circuit 72 is adjusted so that the gate-source voltage Vgs1 of the MOS transistor M1 becomes approximately 0V.

  As a result, it is possible to maintain the reference voltage Vref and suppress high-frequency fluctuation components superimposed on the power supply voltage Vdd from appearing at the reference voltage output terminal 13 via the gate-drain capacitance Cgd1 of the MOS transistor M1. .

  The external power source Vex is not particularly limited as long as the internal resistance is small and the frequency dependency is small. For example, a dry battery can be used.

  As described above, in the reference voltage generation circuit 70 of this embodiment, since the second circuit is arranged outside, there is an advantage that the degree of freedom in designing the second circuit is increased.

1 is a circuit diagram showing a configuration of a reference voltage generation circuit according to Embodiment 1 of the present invention. The figure which shows the simulation result of the power supply voltage fluctuation removal ratio of the reference voltage generation circuit which concerns on Example 1 of this invention compared with the conventional reference voltage generation circuit. The figure which shows the alternating current equivalent circuit of the reference voltage generation circuit which concerns on Example 1 of this invention. 1 is a circuit diagram showing a configuration of a regulator according to Embodiment 1 of the present invention. 1 is a diagram showing a semiconductor integrated device according to Embodiment 1 of the present invention. FIG. 5 is a circuit diagram showing a configuration of a reference voltage generation circuit according to Embodiment 2 of the present invention. The figure which shows the simulation result of the power supply voltage fluctuation removal ratio of the reference voltage generation circuit which concerns on Example 2 of this invention compared with the conventional reference voltage generation circuit. FIG. 6 is a circuit diagram showing a configuration of a reference voltage generation circuit according to Embodiment 3 of the present invention. FIG. 6 is a circuit diagram showing a configuration of a reference voltage generation circuit according to Embodiment 4 of the present invention. FIG. 9 is a circuit diagram showing a configuration of a reference voltage generation circuit according to Embodiment 5 of the present invention.

Explanation of symbols

10, 40, 50, 60, 70 Reference voltage generation circuit 11, 61 First circuit 12, 42, 52, 62, 72 Second circuit 13 Reference voltage output terminal 20 Regulator 21 Voltage dividing circuit 22 Differential amplifier 30 Semiconductor integrated device 31 Semiconductor chips 34a to 34d Bonding pads 73 External power supply connection terminals M1, M2, M4 n-depletion type MOS transistors M3, M5 n-enhancement type MOS transistors M6, M7, M8 p-depletion type MOS transistor M9, M10 p-enhancement type MOS transistors R1, R2, R3, R4 Resistor Vref Reference voltage Vex External voltage source

Claims (3)

A depletion-type first insulated gate field effect transistor having a drain connected to a first potential;
A depletion type second insulated gate field effect transistor having a drain connected to a source of the first insulated gate field effect transistor and a gate connected to the source;
An enhancement type third insulated gate field effect transistor having a drain connected to a source of the second insulated gate field effect transistor, a gate connected to the drain in a short circuit , and a source connected to a second potential;
A depletion type fourth insulated gate field effect transistor having a drain connected to the first potential, a gate connected to the gate of the first insulated gate field effect transistor, and a source connected to the gate;
An enhancement type fifth insulated gate having a drain connected to the source of the fourth insulated gate field effect transistor, a gate connected to the gate of the third insulated gate field effect transistor, and a source connected to the second potential A field effect transistor;
A reference voltage generating circuit comprising: The first insulated gate field effect transistor, the second insulated gate field effect transistor, the third insulated gate field effect transistor, the fourth insulated gate field effect transistor, and the fifth insulated gate field effect transistor 2. The reference voltage generating circuit according to claim 1, wherein the reference voltage generating circuits are of the same conductivity type. at least,
A depletion-type first insulated gate field effect transistor having a drain connected to a first potential;
A depletion type second insulated gate field effect transistor having a drain connected to a source of the first insulated gate field effect transistor and a gate connected to the source;
An enhancement type third insulated gate field effect transistor having a drain connected to a source of the second insulated gate field effect transistor, a gate connected to the drain in a short circuit , and a source connected to a second potential;
A depletion type fourth insulated gate field effect transistor having a drain connected to the first potential, a gate connected to the gate of the first insulated gate field effect transistor, and a source connected to the gate;
An enhancement type fifth insulated gate having a drain connected to the source of the fourth insulated gate field effect transistor, a gate connected to the gate of the third insulated gate field effect transistor, and a source connected to the second potential A field effect transistor;
Are integrated and formed on the same chip.

Images