JP2003233429A - Power supply circuit and bias circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the dependency of standard voltage on source voltage. <P>SOLUTION: A third depletion-mode transistor (M3) is provided between a first transistor (M1) and a high potential side power supply (VDD), and the backgate of the third transistor is connected to the ground (GND) or a series connection node of the first and the second transistors. In this circuit, the third transistor functions as a constant voltage source, and allows terminal voltage of the first transistor to stabilize. This reduces the dependency of standard voltage on source voltage. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit technique, a power supply circuit for obtaining a predetermined reference voltage, and a bias circuit for obtaining a predetermined bias current.

[0002]

2. Description of the Related Art A depletion type first n-channel MOS transistor and an enhancement type second n-channel MOS transistor.
A reference voltage circuit in which an n-channel MOS transistor is connected in series and a reference voltage is obtained from the series connection node is known. The gate of the first n-channel type MOS transistor and the gate of the second n-channel type MOS transistor are coupled to the series connection node. Further, the source of the first n-channel type MOS transistor is coupled to the high potential side power source, and the source of the second n-channel type MOS transistor is coupled to the low potential side power source (ground). In this case, the reference voltage is the difference between the threshold value of the first transistor and the threshold value of the second transistor.

An example of a document describing a reference voltage circuit is "Integrated Circuit Engineering (2) page 180" issued by Corona Co. in June 1993.

[0004]

Ideally, the reference voltage is not affected by fluctuations in the high-potential-side power supply voltage. However, in the reference voltage circuit in which the depletion type first n-channel MOS transistor and the enhancement type second n-channel MOS transistor are connected in series as described above and the reference voltage is obtained from the series connection node, , M applied there
Due to the influence of the correction coefficient (value determined by the early voltage) of the OS transistor, the reference voltage fluctuates with respect to the fluctuation of the high-potential-side power supply voltage, and as a circuit applied to, for example, a three-terminal regulator, The inventors of the present application have found that the line regulation characteristic is not sufficient. Further, in a semiconductor integrated circuit, particularly in a constant current output type operational amplifier 40 and the like, the line regulation characteristic of the output current is important. In order to improve the line regulation characteristic of the output current in the constant current output type operational amplifier 40, it is important to reduce the power supply voltage dependency of the bias circuit included in the operational amplifier.

An object of the present invention is to provide a technique for reducing the power supply voltage dependency of the reference voltage.

Another object of the present invention is to provide a technique for reducing the power supply voltage dependency of the bias circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, when the power supply circuit is configured to include the depletion type first transistor and the enhancement type second transistor connected in series to the depletion type first transistor, the depletion is provided between the first transistor and the high potential side power source. A third transistor of the type
The back gate of the transistor is connected to the ground or a series connection node of the first transistor and the second transistor.

According to the above means, the third transistor acts as a constant voltage source and stabilizes the terminal voltage of the first transistor. This achieves a reduction in the power supply voltage dependency of the reference voltage.

At this time, the potential of the series connection node of the first transistor and the third transistor is equal to that of the first transistor.
It can be set to be higher than the sum of the potential of the serial connection node of the transistor and the second transistor and the threshold value of the first transistor. Further, the gate size ratio of the third transistor can be set to be larger than the gate size ratio of the first transistor. Further, in order to further stabilize the reference voltage, a plurality of the third transistors may be connected in series.

A back gate of the second transistor includes a first transistor having a gate and a source coupled to the ground, and a second transistor having a gate and a source coupled to the drain of the first transistor. Is coupled to the ground to form a bias circuit.

According to the above means, the second transistor acts as a constant voltage source and stabilizes the terminal voltage of the first transistor. At this time, the bias current flowing therethrough can be stabilized by causing the second transistor to function as a constant current source. This achieves a reduction in the power supply voltage dependency of the bias circuit.

[0014]

FIG. 15 shows a configuration example of a constant voltage circuit which is an example of a power supply circuit according to the present invention. Figure 1
Although not particularly limited, the constant voltage circuit shown by 5 includes a three-terminal regulator 10 for lowering the voltage. The three-terminal regulator 10 is a high-potential-side power source (VD
D) terminal, ground (GND) terminal, output (OU)
T) terminal. The high-potential power supply VDD is supplied to the high-potential power supply (VDD) terminal, and the reduced voltage is output from the output (OUT) terminal. Grand (G
The (ND) terminal is coupled to the ground GND. The capacitor 11 is coupled to the high-potential power supply (VDD) terminal, and the capacitor 12 is coupled to the output (OUT) terminal. The output voltage from the output (OUT) terminal is the high potential side power supply VDD
Is reduced, the voltage is divided by the series connection circuit of the resistors 13 and 14, and the divided output Vout is supplied to a circuit (not shown).

FIG. 16 shows a configuration example of a constant current circuit which is an example of the power supply circuit according to the present invention. The constant current circuit shown in FIG. 16 is also not particularly limited, but includes the three-terminal regulator 10 like the constant voltage circuit. Np driven by the output voltage of the three-terminal regulator 10
An n-type bipolar transistor 15 is provided. npn
The collector of the bipolar transistor 15 is connected to the high potential power source VD via the pnp bipolar transistor 16.
Connected to D. npn bipolar transistor 15
Source is coupled to ground GND through resistor 18. A pnp type bipolar transistor 17 current-mirror coupled to the bipolar transistor 16 is provided, and a constant current output Iout is obtained via the bipolar transistor 17.

FIG. 1 shows a configuration example of the three-terminal regulator 10.

The three-terminal regulator 10 shown in FIG.
Is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

N-channel type MOS transistors M5, M
6 are differentially coupled by coupling their sources to the ground GND via the n-channel MOS transistor M4. In addition, the n-channel MOS transistor M
The drains of M5 and M6 are coupled to the high potential side power supply VDD via the corresponding p-channel MOS transistors M7 and M8. The p-channel MOS transistor M7 is current-mirror coupled to the p-channel MOS transistor M8. The reference voltage V formed by the reference voltage circuit 20 is applied to the gate of the n-channel MOS transistor M5 and the gate of the n-channel MOS transistor M4.
REFF is supplied. The reference voltage VREFF is set to 1.6V, although not particularly limited. A differential output is obtained from the drain of the n-channel MOS transistor M5, which is a p-channel MOS transistor M in the subsequent stage.
9 is transmitted to the gate. The source of the p-channel type MOS transistor M9 is coupled to the high potential side power supply VDD. The output (OUT) terminal of the three-terminal regulator 10 is drawn from the drain of the p-channel type MOS transistor M9. The output voltage from the output terminal is detected by being divided by the resistors R1 and R2 connected in series, and the detection result is supplied to the gate of the p-channel MOS transistor M6. Although not particularly limited, the resistance R1 is 51.5 kΩ and the resistance R2 is 48.5 kΩ.
It is said that A capacitor C for phase compensation is provided at the source and gate of the p-channel MOS transistor M9.

Here, the n-channel type MOS transistor M4 and the p-channel type MOS transistor M7,
M8 and M9 are enhancement type, and n
The channel type MOS transistors M5 and M6 are of depletion type. The gate size ratio (ratio of the gate width W to the gate length L) W / L of the n-channel MOS transistor M4 is not particularly limited, but is 16/80.

The reference voltage circuit 20 is constructed as follows.

N-channel type MOS transistors M1 and M
2 are connected in series, and an n-channel type MOS transistor M3 is connected in series thereto. The drain of the n-channel MOS transistor M3 is coupled to the high potential power supply VDD, and the source of the n-channel MOS transistor M2 is coupled to the ground GND. The gate of n-channel MOS transistor M1 is coupled to the source, and the gate of n-channel MOS transistor M2 is coupled to the drain. The gate of the n-channel MOS transistor M3 is coupled to the source. The n-channel MOS transistors M1 and M3 are of depletion type, and the n-channel MOS transistor M2 is of enhancement type. n-channel type MOS transistor M1 or M
2 has a gate size ratio W / L of 16/80, and the n-channel MOS transistor M3 has a gate size ratio W / L of 10
It is set to 0/5. n-channel type MOS transistor M1
From the node connected in series with the reference voltage circuit 20
Output voltage VREF is obtained. The voltage of the n-channel type MOS transistor M3 is VS ₃ , and the n-channel type MO transistor M3 is
When the threshold value of the S transistor M1 is VT ₁ , the gate size ratio of the MOS transistor is determined so that the voltage VS ₃ becomes higher than VREF + VT ₁ . Although the back gates of the n-channel type MOS transistors M1 and M2 are coupled to the sources,
The back gate of the OS transistor M3 is ground GND
Is bound to. As a result, the dependency of the reference voltage VREF on the high-potential-side power supply VDD can be reduced. By reducing the dependency of the reference voltage VREF on the high-potential-side power supply VDD, the output voltage (VDD-OUT) characteristic of the three-terminal regulator 10 that forms an output voltage based on the reference voltage VREF with respect to the high-potential-side power supply. Is fixed at 3.3 V within a predetermined range of the high-potential-side power supply VDD, as shown in FIG.

Next, the reason why the dependency of the output voltage VREF of the reference voltage circuit 20 on the high-potential power supply VDD is reduced will be described in detail.

First, a basic circuit for generating a reference voltage will be described.

As shown in FIG. 3, the depletion device
Type n-channel MOS transistor M1
Instrument type n-channel MOS transistor M
2 is connected in series to the reference voltage circuit,
Threshold VT of register M1 ₁And a MOS transistor
M2 threshold VT_TwoIs defined as the reference voltage VREF
(See FIG. 4). In the following description, -VT₁= VT
_Two= 0.8, K = 0.75, 2φF = 0.65, VB =
-1.2V, β0₁= Β0_Two= 77.5 μA / V^TwoTosa
Be done. Where VT₁Is the threshold of the MOS transistor M1
Value, VT_TwoIs the threshold of the MOS transistor M2, K
Is a constant determined by the gate oxide film thickness, 2φF is an impurity of the substrate
VB is MO, a constant determined by the concentration and the intrinsic carrier concentration
Back gate voltage of S transistor, β0₁Is MOST
A constant determined by the structure of the gate of the transistor M1,
β0_TwoIs due to the structure of the gate of the MOS transistor M2
It is a constant that is determined.

The drain current ID ₁ of the n-channel MOS transistor M1 is expressed by the equation 1, and the reference voltage VRE
F is shown by equation 2.

[0026]

[Equation 1]

[0027]

[Equation 2]

Here, substituting equation 1 into equation 2 and applying each value
Then, as shown in Equation 3, the reference voltage VREF is
It is set to 1.6V. Furthermore, (β0₁・ W₁/ L₁) /
(Β0 _Two・ W_Two/ L_Two) = 1, and inside the route of number 1
By setting it to "1", the temperature characteristic can be made zero.
Wear.

[0029]

[Equation 3]

However, as is apparent from the drain-source current (IDS) characteristics of the MOS transistor shown in FIG. 5, there is an influence of the correction coefficient λ of the n-channel type MOS transistor M1. Therefore, as shown in FIG. , The reference voltage VREF is slightly changed with respect to the change of the high-potential-side power supply VDD. High-potential-side power supply VD of reference voltage VREF
In order to reduce the D dependence, as shown in FIG.
Channel type MOS transistor M1 and high potential side power supply VD
Enhancement-type n-channel MO with D
Providing the S-transistor M0 is conceivable, but in reality, a sufficient effect cannot be obtained.

Here, the drain-source voltage VDS
Drain current ID in consideration of fluctuation₁Is according to
Applying this equation 4 to the equation 2, (β0₁・ W₁
/ L ₁) / (Β0_Two・ W_Two/ L_Two) = 1, the standard
The voltage VREF is as shown in Equation 5.

[0032]

[Equation 4]

[0033]

[Equation 5]

Next, when Equation 5 is differentiated by the drain-source voltage VDS ₁ of the n-channel MOS transistor M1, Equation 6 is obtained. Also, λ1 ・ VDS1
Since «1 is set and λ1 · VDS1 = 0 is set and Equation 6 is rearranged, Equation 7 is obtained.

[0035]

[Equation 6]

[0036]

[Equation 7]

In Equation 7, λ (1/50 V), VT ₁ = −0.
Substituting 8V, the line regulation is 8mV /
From the result of V or more, n-channel type MOS transistor M1
It is obvious that the VREF line regulation is deteriorated due to the influence of the correction coefficient λ of.

Therefore, as shown in FIG. 1, a depletion type n-channel MOS transistor M3 is provided, and the back gate of this MOS transistor M3 is coupled to the ground GND to form the reference voltage circuit 20.

FIG. 8 shows the reference voltage circuit 20 shown in FIG.
Only typically shown.

Depletion type n-channel MOS
The transistor M3 is provided between the n-channel MOS transistor M1 and the high potential side power supply VDD
The back gate of transistor M3 is coupled to ground GND. In addition, the gate size ratio (W ₃ / L of the MOS transistor M3 is set so that VS ₃ > VREF + VT ₁ holds.
₃ ) is set. As a result, the MOS transistor M
3 has a sufficient capacity to pass the drain current ID ₁ determined by the MOS transistor M1,
The threshold value (VT ₃ ) is forcedly raised, and feedback is applied to suppress the current of the MOS transistor M ₃ . As a result, a potential difference (VS ₃ ) is generated between the source of the MOS transistor M3 and the ground (back gate). As a result, as shown in FIG. 9, the MOS transistor M3
The device itself becomes a kind of constant voltage source that operates by the bias current (ID ₁ ), and even if the high potential side power supply VDD fluctuates, the MO
The drain voltage (= VS ₃ ) of the S-transistor M1 is kept substantially constant as shown in FIG. Therefore, the line regulation of the reference voltage VREF can be significantly improved.

Here, the line regulation characteristic of the reference voltage VREF will be further considered.

In order to simplify the mathematical expression, in the following description, the dependence of λ on the gate length (L) and the drain current (I
A slight change in D ₁ ) shall be ignored.

First, the source voltage VS ₃ of the MOS transistor M3 is obtained. The general formula is ID ₁ = (1/2) ·
From the modification of (β0 ₃ · W ₃ / L ₃ ) · (−VT ₃ ) ² ,
The number 8 can be obtained.

[0044]

[Equation 8]

Since the back gate of the MOS transistor M3 is connected to the ground GND, the threshold value (VT ₃ ) is affected by the substrate bias effect. At this time, the threshold value VT ₃ is represented by the equation 9, and when it is transformed with respect to the back gate voltage (VB ₃ ),
As shown in.

[0046]

[Equation 9]

[0047]

[Equation 10]

From the above, the source voltage VS ₃ of the MOS transistor M3 becomes as shown by the equation 11 by substituting the equation 8 into the equation 10.

[0049]

[Equation 11]

In this equation 11, VT0_Three= -0.8, K =
0.75, 2φF = 0.65, β0 _Three= 77.5 μA /
V^Two, W_Three/ L_Three= 100/5, ID₁= Substitute 5 μA
Then VS_Three= 2.5V is obtained.

Next, the fluctuation amount of the source voltage VS ₃ with respect to the high potential side power source Vdd is obtained. The threshold value VT _{3 in} consideration of the influence of the drain-source voltage VDS is
Is transformed into Equation 12. Then, by substituting the equation 12 into the equation 10, the equation 13 is obtained, and by differentiating the equation 13 with VDS ₃ , the equation 14 is obtained.

[0052]

[Equation 12]

[0053]

[Equation 13]

[0054]

[Equation 14]

Since λ · VDS ₁ << ₁ , λ ·
When VDS ₁ = 0 is set and Equation 14 is rearranged, Equation 15 is obtained.

[0056]

[Equation 15]

In this equation 15, VT0_Three= -0.8, K =
0.75, 2φF = 0.65, β0 _Three= 77.5 μA /
V^Two, W_Three/ L_Three= 60/15, λ = 1 / 50V, ID
₁= 5μA is substituted for VS_ThreeΔV
S_Three/ΔVDD=6.55mV/V can be obtained
It

From the above, the VREF line regulation when the MOS transistor M ₃ is provided is given by the equation 16 from the product of the equation 7 and the equation 15. That is, VRE when the MOS transistor M3 does not exist
The F line regulation is 8.00 mV / V (see FIG. 6), while the VREF line regulation when the MOS transistor M3 is provided is 52.
Since it is 4 μV / V, it is clear that the VREF line regulation is remarkably improved by providing the MOS transistor M3 (see FIG. 11).

[0059]

[Equation 16]

The output voltage OUT from the output terminal of the three-terminal regulator 10 shown in FIG.
If T2 = -VT1 = 0.8V, the output voltage OUT
Is 3.3V. This output voltage OUT = 3.3V
Is generated in the reference voltage circuit 20 based on the reference voltage VREF having a good VREF line regulation, so that the high-potential-side power supply Vdd dependency is reduced and stabilized.

[0061]

[Equation 17]

According to the above example, the following operational effects can be obtained.

(1) In the reference voltage circuit 20, MO
A depletion type MOS transistor M3 is provided between the S transistor M1 and the high-potential power supply VDD, and the back gate of this MOS transistor M3 is connected to the ground G.
By connecting to the ND, the MOS transistor M
3 acts as a constant voltage source and can stabilize the terminal voltage of the MOS transistor M1, so that the reference voltage V
The power supply voltage dependency of REF can be reduced.

(2) Due to the effect of (1) above, the power supply voltage dependency of the output voltage OUT in the three-terminal regulator 10 operated based on the reference voltage VREF can be reduced.

FIG. 12 shows another configuration example of the three-terminal regulator 10. The three-terminal regulator 10 shown in FIG. 12 is greatly different from that shown in FIG. 1 in that an n-channel MOS transistor M10 is provided.
That is, a depletion type n-channel MOS
A depletion type n-channel MOS transistor M is provided between the transistor M3 and the high-potential-side power supply Vdd.
10 is provided, and the back gate of the MOS transistor M10 is connected to the ground GND. The gate of MOS transistor M10 is coupled to the source. Although not particularly limited, the MOS transistor M10 has the same gate size ratio as the MOS transistor M3.
As described above, the MOS transistor M3 functions as a kind of constant voltage source.
Similarly, the MOS transistor M10 vertically stacked in 3 also functions as a kind of constant voltage source to stabilize the source voltage of the MOS transistor M10 (which is equal to the drain voltage of M3). The configuration shown in FIG.
VREF line regulation can be improved. Therefore, the voltage output from the output terminal OUT is further stabilized. In order to further improve the VREF line regulation, it is effective to further add a MOS transistor corresponding to the MOS transistor M10.

FIG. 13 shows another configuration example of the three-terminal regulator 10.

Three-terminal regulator 10 shown in FIG.
However, the main difference from that shown in FIG. 1 is that the back gates of the MOS transistors M5 and M6 are connected to the ground GND.
It is a point fixed to. Even in this case, the same effect as that of the circuit shown in FIG. 1 can be obtained.

FIG. 14 shows a constant current output type operational amplifier to which the bias circuit according to the present invention is applied.

The constant current output type operational amplifier 40 shown in FIG. 14 has a bias circuit 30.
It is designed to operate based on the bias current supplied by 0. The sources of the p-channel type MOS transistors M25 and M26 are p-channel type M
It is differentially coupled by being commonly connected to the high-potential side power supply Vdd via the OS transistor M24. The bias circuit 30 is coupled to the high-potential-side power supply Vdd via the p-channel MOS transistor M23, so that the MO
A predetermined current flows through the S transistor M23. Since the p-channel MOS transistor M24 is mirror-coupled to the MOS transistor M23, the MOS transistor M24 functions as a constant current source for the differential pair (M25, M26). n-channel type MOS transistor M2
7, M28 are differentially coupled MOS transistors M2
5, M26 load, which is mirror-coupled. MO
A differential output is obtained from the drain of the S-transistor M26, which is the n-channel MOS transistor M3 in the subsequent stage.
1 is transmitted to the gate. An n-channel MOS transistor M32 is connected in parallel to the n-channel MOS transistor M31, and p-channel MOS transistors M29 and M30 are coupled thereto. The MOS transistors M29 and M30 are mirror-coupled to the MOS transistor M23 and function as a constant current source. An n-channel MOS transistor M33 is mirror-coupled to the MOS transistor M32. The MOS transistor M33 has a p-channel MOS
A transistor M34 is connected in series, and a p-channel type MOS transistor M35 is connected to this MOS transistor M34.
Are mirror-coupled. N in the MOS transistor M35
Channel type MOS transistor M36 is connected in series,
The output current OUT is obtained from the series connection node of the MOS transistors. By connecting the drain of the MOS transistor M26 to the gate of the MOS transistor M36, the differential output of the differential pair (M25, M26) is transmitted. Further, a capacitor C for phase compensation is connected between the gate and drain of the MOS transistor M36.

An inverting input terminal IN (-) is drawn from the gate of the MOS transistor M25, and a non-inverting input terminal IN is drawn from the gate of the MOS transistor M26.
(+) Is pulled out. The output voltage OUT is obtained according to the potential difference between the signals input between the inverting input terminal IN (−) and the non-inverting input terminal IN (+). The MOS transistors M23 to M36 are of enhancement type.

Here, in the bias circuit 30, the n-channel type MOS transistors M100 and M300 are connected in series, and basically, the reference voltage circuit 2 shown in FIG.
0 is equivalent to the MOS transistor M2 omitted. The gate of the MOS transistor M100,
The source and back gate are coupled to ground GND. In the MOS transistor M300, the gate is coupled to the source and the back gate is ground GN.
It is connected to D. MOS transistors M100, M
300 is a depletion type. The gate size ratio of the MOS transistor M300 is set to be much larger than the gate size ratio of the MOS transistor M100. This relationship is the same as the relationship between the MOS transistors M3 and M1 in the reference voltage circuit 20 shown in FIG. This is the MOS transistor M1
The function of the 00 as a constant current source is the MOS transistor M
This is to avoid being restricted by 300. M
The OS transistor M300 functions as a kind of constant voltage source similarly to the MOS transistor M3 in the reference voltage circuit 20 shown in FIG.
The drain voltage of is stabilized against fluctuations in the high-potential-side power supply VDD. Since the drain voltage of the MOS transistor M100 is stabilized, the current flowing through the MOS transistors M23 and M300 is stabilized. The bias current flowing through the MOS transistors M23 and M300 is determined by the MOS transistor M100 that functions as a constant current source.

In this way, in the bias circuit 3, the MO
An S-transistor M300 is provided, and the back gate of the MOS transistor 300 is coupled to the ground GND, so that the drain voltage of the MOS transistor M100 can be stabilized, whereby M
Since the line regulation of the bias current flowing through the OS transistors M23 and M300 can be improved, the line regulation of the output current OUT can be improved.

Although the invention made by the present inventor has been specifically described above, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

For example, in the above example, the back gate of the MOS transistor M3 is coupled to the ground GND, but the back gate of the MOS transistor M3 is connected to the MOS transistor M1.
Even if the voltage is fixed to the reference voltage VREF level by being coupled to the node connected in series with M2 and M2, the same effect as in the case of the above example can be obtained.

In the above description, the invention made by the present inventor was mainly applied to a three-terminal regulator or an operational amplifier, which is the field of application of the background, but the present invention is not limited thereto. It can be widely applied to various electronic circuits.

The present invention can be applied on the condition that at least a transistor is included.

[0077]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a depletion type third transistor is provided between the first transistor and the high potential side power source, and the back gate of the third transistor is grounded, or the first transistor and the second transistor are connected in series. By connecting to the node, the third transistor acts as a constant voltage source and can stabilize the terminal voltage of the first transistor, so that the dependency of the reference voltage on the power supply voltage can be reduced.

The back gate of the second transistor includes a first transistor whose gate and source are coupled to the ground, and a second transistor whose gate and source are coupled to the drain of the first transistor. When a bias circuit is configured by coupling the above to the ground, the second transistor acts as a constant voltage source, and the terminal voltage of the first transistor can be stabilized. By functioning as a constant current source, the bias current flowing therethrough can be stabilized, and the power supply voltage dependency of the bias circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a configuration example of a three-terminal regulator which is an example of a power supply circuit according to the present invention.

FIG. 2 is a characteristic diagram of an output voltage of the three-terminal regulator with respect to a high potential side power source.

FIG. 3 is a circuit diagram of a basic configuration of a reference voltage circuit.

FIG. 4 is a characteristic diagram for explaining an operation principle of reference voltage generation in the reference voltage circuit.

FIG. 5 is a characteristic diagram of drain-source current with respect to drain-source voltage of a MOS transistor.

6 is a characteristic diagram of line regulation in the reference voltage circuit shown in FIG.

FIG. 7 is a circuit diagram of a configuration example when the reference voltage circuit shown in FIG. 3 is improved.

FIG. 8 is a circuit diagram showing a configuration example of a reference voltage circuit applied to the power supply circuit according to the present invention.

FIG. 9 is a characteristic diagram of a source voltage with respect to a drain current in the reference voltage circuit.

FIG. 10 is a characteristic diagram of a reference voltage and a source voltage with respect to a drain voltage in the reference voltage circuit.

FIG. 11 is a characteristic diagram of line regulation in the reference voltage circuit.

FIG. 12 is a circuit diagram of another configuration example of the three-terminal regulator.

FIG. 13 is a circuit diagram of another configuration example of the three-terminal regulator.

FIG. 14 is a circuit diagram of a configuration example of a constant current output type operational amplifier to which the bias circuit according to the present invention is applied.

FIG. 15 is a circuit diagram of a configuration example of a constant voltage circuit to which the three-terminal regulator is applied.

FIG. 16 is a circuit diagram of a configuration example of a constant current circuit to which the three-terminal regulator is applied.

[Explanation of symbols]

10 3 terminal regulator 20 Reference voltage circuit 30 bias circuit 40 Constant current output type operational amplifier M1, M2, M3 n-channel MOS transistor

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Claims (5)

[Claims] 1. A depletion type first transistor and an enhancement type second transistor connected in series to the depletion type first transistor are provided, and a difference in threshold value between the first transistor and the second transistor is obtained as a reference voltage. A depletion-type third transistor is provided between the first transistor and the high-potential-side power supply, and the back gate of the third transistor is grounded or the first transistor
A power supply circuit comprising a transistor and a second transistor connected to a series connection node. 2. The potential of the serial connection node between the first transistor and the third transistor is the potential of the serial connection node between the first transistor and the second transistor and the threshold value of the first transistor. The power supply circuit according to claim 1, wherein the power supply circuit is set to be higher than the added value. 3. The power supply circuit according to claim 1, wherein the gate size ratio of the third transistor is set larger than the gate size ratio of the first transistor. 4. The power supply circuit according to claim 1, wherein a plurality of the third transistors are connected in series. 5. A bias circuit for obtaining a predetermined bias current, comprising: a first transistor having a gate and a source coupled to ground; and a first transistor having a gate and a source coupled to the drain of the first transistor. A bias circuit including two transistors, the back gate of the second transistor being coupled to the ground.