JP3531129B2 - Power supply circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a power supply circuit and a low-loss DC power supply circuit, for example, a three-terminal type. The present invention relates to a technology effective for use in a regulator IC (semiconductor integrated circuit device). FIG. 4 shows a schematic configuration of a conventional power supply circuit. The power supply circuit shown in FIG. 1 includes a reference voltage generation circuit 1, a differential amplifier circuit 20 forming an error amplifier, a p-channel MOS
Buffer circuit 3 including transistor M5 and resistor R
1 and R2, the output voltage V
feedback voltage Vf (Vf = V
o × R1 / (R1 + R2)) and the reference voltage Vr, the output voltage Vo is reduced by a negative feedback loop such that the difference becomes zero.
At a constant voltage (Vr = Vo × R1 / (R1 + R2)). When this power supply circuit is a three-terminal regulator IC, an unstabilized power supply voltage Vcc is used as an external terminal.
, An output terminal P2 for extracting a stabilized output voltage Vo, and a common terminal P3 for connecting a reference potential to a common reference potential (GND).
Is provided. However, in the power supply circuit shown in FIG. 4, the reference voltage Vr, which is a control reference for the output voltage Vo, is generated by the reference voltage generation circuit 1, and this reference voltage generation circuit 1 This has prevented the number from being reduced. If the reference voltage generating circuit 1 is a simple circuit with a small number of elements, it is susceptible to fluctuations in the power supply voltage Vcc, making it impossible to obtain a stable reference voltage Vr. Stability also worsens. In other words, in this type of power supply circuit, an increase in the number of elements is inevitable in order to obtain a certain level of stabilization accuracy against fluctuations in the power supply voltage Vcc and the like. Therefore, the present inventors have studied a power supply circuit as shown in FIG. 5 in order to solve the above-mentioned problem. The power supply circuit shown in FIG. 5 has two n-channel MOS transistors M1 and M2 source-coupled via a constant current circuit 21 and two p-channel MOS transistors M3 and M4 forming a current mirror circuit 22.
And the other MOS transistor M5 is of the enhancement type and the other MOS transistor M2 is of the depletion type, so that the differential amplifier circuit 20 has a constant input offset voltage. Vio, and this voltage offset Vio is used instead of the reference voltage (Vr).
That is, the stabilization control of o is performed. That is, in this power supply circuit, a fixed input offset voltage Vi is used instead of providing a reference voltage generation circuit.
is used as an error amplifier, and a feedback voltage Vf (Vf = Vo × R1 / (R1 + R2)) obtained by dividing the output voltage Vo by the resistors R1 and R2 becomes the input offset voltage Vio. The output voltage Vo is kept at a constant voltage (Vio = Vo × R1) by a negative feedback loop.
/ (R1 + R2)). Thus, the reference voltage generating circuit can be omitted, so that the number of circuit elements can be reduced. Further, the input offset voltage Vio corresponding to the reference voltage
Is formed by the difference between the threshold voltages of the enhancement type MOS transistor M1 and the depletion type MOS transistor M2.
Is relatively stable against fluctuations in As a result, in a power supply circuit such as a three-terminal regulator, the number of elements can be reduced while maintaining a certain operation accuracy. As a known technique relating to this type of power supply circuit, there is, for example, US Pat. No. 4,188,588. However, it has been clarified by the present inventors that the above-described technology has the following problems. That is, in the power supply circuit shown in FIG. 5, the two n-channel MOS transistors M1 and M2, which are source-coupled via the constant current circuit 21, are dc separated by a pn reverse junction. A slight leakage current Ir flows between the substrate (Vcc potential) and the source electrode. This leak current Ir is superimposed on the source current of MOS transistors M1 and M2. At this time, if the constant current value of the constant current circuit 21 for controlling the common source current of the MOS transistors M1 and M2 is sufficiently larger than the leak current Ir, no particular problem occurs. However, if the constant current value of the constant current circuit 21 is reduced as much as possible in order to minimize the power consumption of the circuit, the existence of the leak current Ir cannot be ignored and the constant current The current value It overflows with only the leak current Ir. This leak current Ir is also affected by temperature and the like. As a result, it has been found that the operation of the differential amplifier circuit 20 becomes unstable, and the operation of the entire power supply circuit becomes unstable accordingly. It is an object of the present invention to provide a technique capable of reducing the number of circuit elements and significantly reducing power consumption in a power supply circuit or the like while ensuring constant operation accuracy. The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Means for Solving the Problems Of the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, an enhancement type MOS transistor having a drain connected to the current input terminal of the current mirror circuit and a source connected to the reference potential, a drain connected to the current output terminal of the current mirror circuit, and a source connected to the reference potential Depletion type M connected to
An error amplifier having a constant input offset voltage is constituted by the OS transistor, and a negative feedback loop of the output voltage is formed using the error amplifier. According to the above-mentioned means, the leak current flowing between the semiconductor substrate and the source electrode is immediately bypassed from the source electrode to the reference potential. Therefore, by minimizing the current value that is constantly consumed in the circuit,
Even if the leak current becomes relatively conspicuous, the influence of the leak current on the circuit operation can be avoided. As a result, in a power supply circuit or the like, the object of reducing the number of circuit elements and significantly reducing power consumption while securing a certain operation accuracy is achieved. Preferred embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. FIG. 1 shows an embodiment of a power supply circuit to which the technology of the present invention is applied. The error amplifier 2 having a constant input offset voltage Vio, a p-channel M
The buffer circuit 3 performs inversion amplification by the OS transistor M5, and the voltage feedback circuit 4 includes the resistors R1 and R2. As an external terminal for forming a three-terminal regulator IC, an input terminal P1 for inputting an unstabilized power supply voltage Vcc, an output terminal P2 for extracting a stabilized output voltage Vo, and a reference potential To a common reference potential (GND). The error amplifier 2 comprises n-channel MOS transistors M1 and M2 and p-channel MOS transistors M3 and M4. P channel MOS transistors M3, M
4 forms a current mirror circuit 22. This current mirror circuit 22 is connected to the power supply potential (Vcc) side,
The current from the power supply potential (Vcc) side is controlled. That is, the current flowing to the current input terminal controls the current flowing to the current output terminal. In this case, the drain of the p-channel MOS transistor M3 whose drain and gate are commonly connected forms a current input terminal, and the drain of the p-channel MOS transistor M4 whose gate is connected to the common connection point forms a current output terminal. . N-channel MOS transistors M1, M
In No. 2, one (M1) is an enhancement type and the other (M2) is a depletion type. Enhancement type MOS transistor M
Reference numeral 1 indicates that the drain is connected to the current input terminal of the current mirror circuit 22, the source is connected to the reference potential, and the feedback voltage Vf is input to the gate. Depletion type MOS transistor M2
Has a drain connected to the current output terminal of the current mirror circuit 22, and a source and a gate connected to a reference potential. That is, the gate is at the reference potential (GND)
Biased. The buffer circuit 3 is formed of a grounded source circuit of a p-channel MOS transistor. The buffer circuit 3 inverts and amplifies a voltage appearing at the drain side of the depletion type MOS transistor M2, that is, at the current output terminal side of the current mirror circuit 22, and outputs it. Vo is its output voltage. The voltage feedback circuit 4 forms a voltage dividing circuit by the resistors R1 and R2, divides the output voltage Vo and feeds back the voltage to the gate of the enhancement type MOS transistor M1. The above-described current mirror circuit 22, enhancement type MOS transistor M1, depletion type MOS transistor M2, buffer circuit 3, and voltage feedback circuit 4 are integrated on the same semiconductor substrate. Next, the operation will be described. In FIG. 1, MOS transistors M1-M1
The error amplifier 2 composed of M4 has an input offset voltage Vio as shown in equation (1) due to the difference in threshold value between the n-channel enhancement type MOS transistor M1 and the n-channel depletion type MOS transistor M2. ## EQU1 ## The stabilization control of the output voltage Vo is performed by using the voltage offset Vio obtained as described above in place of the reference voltage. That is, the output voltage Vo is changed to the resistances R1 and R1.
2, the feedback voltage Vf (Vf = Vo × R1 / (R1
+ R2)) is stably controlled to a constant voltage (Vio = Vo × R1 / (R1 + R2)) by a negative feedback loop in which the input offset voltage Vio becomes the input offset voltage Vio. As a result, the reference voltage generating circuit can be omitted, so that the number of circuit elements can be reduced. Further, the input offset voltage Vio corresponding to the reference voltage
Is formed by the difference between the threshold voltages of the enhancement type MOS transistor M1 and the depletion type MOS transistor M, and is therefore relatively stable against fluctuations in the power supply voltage Vcc. Specifically, the threshold value Vth1 of M1 and Mth
2 have substantially the same temperature coefficient. Thus, the temperature dependence of the input offset voltage Vio can be extremely reduced. Further, since the drain-source voltage of M1 and the drain-source voltage of M2 are substantially the same, the input offset voltage Vio
Are susceptible to the effect of varying the channel lengths of M1 and M2.
As a result, the number of elements can be reduced while securing a certain operation accuracy. It should be noted that the leak current Ir flowing between the semiconductor substrate and the source electrodes of M1 and M2 formed on the semiconductor substrate is reduced by the leakage current Ir of M1 and M2.
Is immediately bypassed from the source electrode to the reference potential and does not directly affect the operation of the error amplifier 2. Therefore, by minimizing the current value constantly consumed in the circuit as much as possible, even if the leak current becomes relatively noticeable, it is possible to avoid the influence of the leak current Ir on the circuit operation. Can be. Since the constant current circuit 21 is not used for the circuit shown in FIG.
, The number of elements can be further reduced. As described above, in addition to securing control accuracy and reducing the number of circuit elements, it is possible to significantly reduce power consumption. FIG. 2 shows an embodiment in which the above-described circuit of the present invention is applied to a DC amplifier circuit. In the power supply circuit shown in FIG. 1, the gate of the depletion type MOS transistor M2 is connected to the reference potential to apply a fixed bias, but as shown in FIG.
If the gate of M2 is connected to the input voltage source 11 via the terminal P4, the voltage Vai from the input voltage source 11 is amplified and appears at the output terminal P2. in this case,
The input voltage Vai is amplified by applying a bias corresponding to the input offset voltage Vio. FIG. 3 shows an embodiment in which the above-described circuit of the present invention is applied to a voltage detection circuit. The circuit shown in FIG. 3 is a circuit in which the input side of the feedback circuit 4 is separated from the output terminal P2 and connected to the detection terminal P5. The detected voltage Vci supplied to this terminal P5 is equal to the input offset. Whether or not the detection threshold given by the voltage Vio has been exceeded is output by turning on / off the MOS transistor M5 of the buffer circuit 3. Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, the feedback circuit 4 outputs the output voltage Vo
May be directly fed back without passing through the resistors R1 and R2. In the above description, mainly the case where the invention made by the present inventor is applied to a power supply circuit such as a three-terminal regulator IC, a DC amplifier circuit, and a voltage detection circuit, which are the background fields of application, has been described. However, the present invention is not limited to this, and can be applied to, for example, an amplifier circuit for small signals including AC or high frequency. The effects of the typical inventions disclosed in the present application will be briefly described as follows. That is, in a power supply circuit or the like, an effect is obtained that the number of circuit elements can be reduced and power consumption can be significantly reduced while securing a certain operation accuracy.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of a power supply circuit to which the technology of the present invention is applied. FIG. 2 is a circuit diagram showing an embodiment of a DC amplifier circuit to which the technology of the present invention is applied. FIG. 3 is a circuit diagram showing an embodiment of a voltage detection circuit to which the technique of the present invention is applied. FIG. 4 is a block diagram showing a schematic configuration of a conventional power supply circuit. FIG. 5 is a power supply studied prior to the present invention. Circuit diagram [Description of reference symbols] 11 Input signal source 2 Error amplifier 22 Current mirror circuit M1 N-channel enhancement type MOS transistor M2 N-channel depletion type MOS transistor M3, M4, M5 P-channel MOS transistor 3 Buffer circuit 4 Feedback circuit R1 , R2 Resistance P1 to P5 Terminal Vio Input offset voltage Vo Output voltage Vcc Power supply voltage GND Reference potential

Continuation of the front page (56) References JP-A-2-96817 (JP, A) JP-A-2-297615 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G05F 3 / twenty four

Claims (1)

(57) [Claim 1] An error having a constant input offset voltage
Including an amplifier and a first p-channel MOS transistor
A buffer circuit comprising: a first and a second resistor;
A voltage feedback circuit including first and second resistors.
And a power supply circuit for extracting the output voltage from the buffer circuit.
A road, the error amplifier, the second and third p-channel M
A current mirror circuit including an OS transistor ; a drain connected to the current input terminal of the current mirror circuit; a source connected to the reference potential;
An enhancement-type MOS transistor in which the output voltage is fed back is divided by the first and second resistance above a drain connected to the current output terminal of said current mirror circuit, a source and a gate connected to a reference potential It comprises a depletion type MOS transistor, the buffer circuit, the depletion type MOS voltage appearing on the drain side the first transistor p tea
Inverts and amplifies with a channel MOS transistor and outputs
And it is connected to the current input terminal side of the current mirror circuit
Enhancement type MOS transistor
Depletion connected to the current output terminal side of the current mirror circuit
All MOS transistors are n-channel M
An OS transistor, and the buffer circuit is a p-channel MOS transistor.
A resistor voltage dividing circuit formed by a common source circuit and including the first and second resistors.
Indicates that the above output voltage is an enhancement type MOS transistor.
Forming a voltage feedback circuit for feeding back to the gates of the current mirror, the current mirror circuit, and the enhancement type MO.
S transistor, depletion type MOS transistor
And the buffer circuit are integrated on the same semiconductor substrate.
As an external terminal for forming a three-terminal regulator IC,
Input terminal for inputting unregulated power supply voltage and stabilization
Output terminal for extracting the output voltage, and a reference potential
And a common terminal for connecting to a common reference potential, wherein the current mirror circuit is connected to a power supply potential side,
By controlling the current from the power supply potential side to the current input terminal
The flowing current controls the current flowing to the current output terminal.
And the drain and gate are connected in common.
The drain of the second p-channel MOS transistor is
The current input terminal is formed, and a gate is connected to the common connection point.
Drain of the connected third p-channel MOS transistor
And the error amplifier is connected to the n-channel enhancement element.
MOS transistor and the above n-channel depressurization
Due to the difference in threshold from the MOS transistor
The n-channel enhancement type MOS transistor having a predetermined input offset voltage;
Threshold and the above n-channel depletion type MO
The threshold value of the S transistor has substantially the same temperature coefficient
This makes the input offset voltage dependent on temperature.
Power supply circuit characterized by the absence .