JP2005116634A - Semiconductor device including plurality of reference voltage generating circuits and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which enables the remarkable reduction of time required for a wafer test process 1 to realize the cost reduction of semiconductor device and includes a plurality of reference voltage generating circuits, and also to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device including a plurality of constant voltage circuits within a chip has a monitor reference voltage generating circuit in the same structure and in the equal characteristic as the reference voltage generating circuit used in the constant voltage circuit. The monitor reference voltage generating circuit has exclusive pads (T1) to (T3) for contact of a test probe in order to measure the current consumption (I) and reference voltage (Vref) of only the monitor reference voltage generating circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wafer test of a semiconductor device. More particularly, the present invention relates to a semiconductor device for simplifying a wafer test process and a method of manufacturing the same in a semiconductor device including a plurality of reference voltage generation circuits on one chip and a circuit affected by the characteristics of the reference voltage generation circuit. It is.

  FIG. 5 shows an example of a schematic process for manufacturing a conventional semiconductor device. A wafer test 1 is performed when a circuit is formed on the wafer. In a semiconductor device, the characteristics of a built-in circuit are different due to process variations or differences in position on the wafer in a process until a circuit is formed on a wafer. Therefore, in this step, test probes are sequentially applied to pads formed on a large number of chips formed on the wafer to test the operation and characteristics of each chip. If the characteristic is not within the predetermined range, the trimming amount of the predetermined part of the circuit is determined, and trimming is performed by laser trimming in the next process so that the characteristic falls within the predetermined range. The wafer that has been trimmed is inspected for each chip again in wafer test 2, only non-defective chips are assembled, and finally a shipping inspection is performed.

  Conventionally, the wafer test 1 process in which a plurality of constant voltage circuits as shown in FIG. 1 are included in one chip includes the power supply (Vdd), the negative power supply (Vss) and the output voltage of each constant voltage circuit. A probe is applied to the output pad from which (Vout) is output, and the current consumption and output voltage (Vout) of the constant voltage circuit are measured. If the current consumption is not within the specified range, a bias current of the error amplification circuit is generated. Trimming of the Nch MOSFETs (M7) and (M9) is performed so as to be within a predetermined current consumption. If the output voltage (Vout) is not within the predetermined range, trimming of one or both of the output voltage detection resistors (R1) and (R2) is performed, and the output voltage (Vout) is within the predetermined voltage range. I was trying to fit.

  In addition, a switching element such as a MOS transistor is arranged in series with the fuse element in the feedback circuit of the reference voltage generation circuit, and the switching element is controlled by a test mode signal so that the fuse is not actually cut. However, there has been a trimming method and circuit that allows the reference voltage to be adjusted in the same state as when the fuse is blown by changing the feedback rate, and can greatly reduce the trimming process of the semiconductor device having the internal reference voltage generation circuit. (For example, refer to Patent Document 1).

Furthermore, there has been a method for manufacturing a semiconductor device capable of realizing a product having a large operation margin with respect to an input level by always adjusting an input threshold value of an input buffer of the product to an optimum value even when process variations occur ( For example, see Patent Document 2.)
JP-A-7-144101 JP-A-8-316327

Recently, many types of power supplies have been required because the functions of the devices have become abundant and the characteristics of the power supplies required for each function are different. Therefore, a so-called system power source has been used in which many constant voltage circuits are housed in one chip and the constant voltage circuits are totally controlled.
However, when there are many constant voltage circuits in one chip, 20 or more constant voltage circuits are accommodated. Therefore, as described in the prior art, all constant voltage circuits included in one chip in the wafer test 1 process. If the current consumption and output voltage are measured by applying a probe to each constant voltage circuit, a large amount of time is required for the test, which causes an increase in cost.

  Furthermore, the error amplifier circuit has a problem that the bias current is greatly varied and the consumption current of the semiconductor device exceeds the standard. In addition, since the amount of phase compensation of the error amplifier circuit changes depending on the value of the bias current, the conventional method of converting the bias current from the current consumption of the entire constant voltage circuit cannot grasp the accurate bias current and trimming. There was a problem that the deviation of the bias current later became large and optimal phase compensation might not be performed.

  The present invention has been made in order to solve the above-described problems. A plurality of reference voltage generation circuits that can significantly reduce the time of the wafer test 1 process and contribute to cost reduction of a semiconductor device are provided. It is an object to obtain a semiconductor device including the same and a manufacturing method thereof.

  According to the present invention, a plurality of reference voltage generation circuits are provided on one chip of a semiconductor device formed in large numbers on a wafer, and the output voltage and / or current consumption of the reference voltage generation circuit is used in the circuits in the chip. In the semiconductor device, the monitor reference voltage generation circuit having the same circuit configuration and the same characteristics as the reference voltage generation circuit is formed on the chip, so that the characteristics of the reference voltage generation circuit can be measured.

The monitor reference voltage generating circuit is
A depletion type Nch MOSFET,
Enhancement type NchMOSFET,
With
The source of the depletion type NchMOSFET is connected to the drain of the enhancement type NchMOSFET, and the gates of both FETs are connected to the connection point.
Since the voltage between the source and drain of the enhancement type NchMOSFET is used as a reference voltage output, the consumption current of the monitor reference voltage generation circuit and the drain current of the enhancement type NchMOSFET can be made the same, and the drain of the depletion type NchMOSFET Since the enhancement-type Nch MOSFET source and the probe contact pad are provided on the reference voltage output, the monitor reference voltage generation circuit alone can be measured.

  Further, in order to reduce the number of measurement pads, the source of the enhancement type NchMOSFET is connected to the negative power supply (Vss) of the semiconductor device, and the pad provided on the source of the enhancement type NchMOSFET is omitted.

On the other hand, the semiconductor device performs a circuit inspection in the chip in one wafer test process, and in the next process, at least the output of the reference voltage generation circuit and / or the current consumption due to the manufacturing variation of the circuit. In a method for manufacturing a semiconductor device including a laser trimming process for correcting characteristics,
In the wafer test 1 step, the output voltage and / or current consumption of the monitor reference voltage generation circuit is measured,
Based on the measurement result, in the next laser trimming process, the circuit is trimmed on the same chip as the monitor reference voltage generating circuit, so that the time required for one wafer test process can be shortened. .

Further, a plurality of constant voltage circuits each including at least a reference voltage generation circuit, an error amplification circuit, and an output voltage detection resistor are built on one chip, and the output voltages of the plurality of constant voltage circuits are adjusted. In the semiconductor device in which the output voltage detection resistor is trimmed so that the output voltage of the constant voltage circuit falls within a predetermined voltage range.
Since the monitor reference voltage generation circuit having the same circuit configuration and the same characteristics as the reference voltage generation circuit is created on the chip, the characteristics of the reference voltage generation circuit can be measured.

  Further, the output voltage of the monitor reference voltage generation circuit is measured in one wafer test process, and based on the measurement result, in the next laser trimming process, the plurality of monitor reference voltage generation circuits on the same chip as the monitor reference voltage generation circuit Since the output voltage detection resistors included in the constant voltage circuit are trimmed, the time required for one wafer test process can be shortened.

In addition, a plurality of constant voltage circuits each including a reference voltage generation circuit, an error amplification circuit, and an output voltage detection resistor are provided on one chip, and the bias current of the error amplification circuit included in the plurality of constant voltage circuits is adjusted. In the semiconductor device in which trimming is performed so that the bias current of the error amplifier circuit falls within a predetermined current range,
The bias current of the error amplifier circuit is proportional to the current consumption of the reference voltage generation circuit,
Since the monitor reference voltage generation circuit having the same circuit configuration and the same characteristics as the reference voltage generation circuit is created on the chip, the characteristics of the reference voltage generation circuit can be measured.

Further, the current consumption of the monitor reference voltage generation circuit is measured in one wafer test process, and in the next laser trimming process performed based on the measurement result,
Trimming of the bias current of the error amplification circuit included in the plurality of constant voltage circuits on the same chip as the monitor reference voltage generation circuit is performed, so that the time required for one wafer test process can be shortened. It was.

The monitor reference voltage generating circuit is
A depletion type Nch MOSFET,
Enhancement type NchMOSFET,
With
The source of the depletion type NchMOSFET is connected to the drain of the enhancement type NchMOSFET, and the gates of both FETs are connected to the connection point.
Using the voltage between the source and drain of the enhancement type Nch MOSFET as a reference voltage output,
Since the drain of the depletion type Nch MOSFET, the source of the enhancement type Nch MOSFET, and the probe contact pad are provided on the reference voltage output, the monitor reference voltage generation circuit alone can be measured.

  Further, in order to reduce the number of measurement pads, the source of the enhancement type NchMOSFET is connected to the negative power supply (Vss), and the pad provided on the source of the enhancement type NchMOSFET is omitted.

  Further, since the monitor resistor having one end connected to an arbitrary pad of the monitor reference voltage generating circuit and the other end connected to an independent pad is provided, the monitor resistor can be created only by adding one pad.

  In addition, the resistance value of the monitor resistor is measured in one wafer test process, and in the next laser trimming process based on the measurement result, the plurality of constant voltage circuits on the same chip as the monitor reference voltage generating circuit are measured. Trimming of a fixed resistor that requires the absolute value of the included resistance value is performed, so that the time required for one wafer test process can be shortened.

  The bias current generation circuit of the error amplifying circuit includes an enhancement type NchMOSFET constituting a reference voltage and a plurality of NchMOSFETs constituting a current mirror circuit, and a trimming fuse is provided at the drain or source of the plurality of NchMOSFETs. Since it is connected, trimming of the bias current is possible with a simple circuit configuration.

  According to the present invention, a monitor reference voltage generating circuit is provided in each chip, and by simply measuring the characteristics of the monitor reference voltage generating circuit, the circuit characteristics that are influenced by the characteristics of the reference voltage generating circuit are predicted, Since the trimming amount is determined, the time required for the wafer test 1 can be greatly reduced, and the cost of the semiconductor device can be reduced.

  Further, when the present invention is applied to a semiconductor device equipped with a plurality of constant voltage circuits, a monitor reference is used in place of the current consumption and output voltage measured for each constant voltage circuit, which is conventionally performed in the wafer test 1. By measuring only the current consumption and output voltage of the voltage generation circuit, the bias current and output voltage of the constant voltage circuit included in the chip can be predicted, and the next process laser trimming is performed based on the prediction result. The time required for the wafer test 1 can be greatly reduced, and the cost of the semiconductor device can be reduced.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 shows an example of a constant voltage circuit used in the present invention.
The constant voltage circuit of FIG. 1 includes a reference voltage generation circuit, an error amplification circuit, output voltage detection resistors (R1) and (R2), and a current detection resistor (R3).

The reference voltage generation circuit is composed of a depletion type Nch MOSFET (M1) and an enhancement type Nch MOSFET (M2) (hereinafter, enhancement notation is not performed). Since the drain of the depletion type Nch MOSFET (M1) is connected to the power supply (Vdd), the gate and the source are further connected, and the gate is set to 0 bias, the drain current of the depletion type Nch MOSFET (M1) becomes a constant current.
The source of the depletion type Nch MOSFET (M1) is connected to the drain of the Nch MOSFET (M2). The source of the Nch MOSFET (M2) is connected to the negative power supply (Vss), and the gate is connected to the drain.

  As a result, since the drain current of the Nch MOSFET (M2) becomes equal to the drain current of the depletion type Nch MOSFET (M1), the gate voltage of the Nch MOSFET (M2) is set to a voltage determined by the drain current of the depletion type Nch MOSFET (M1). Is done. This voltage becomes the reference voltage (Vref) output from the reference voltage generation circuit.

The error amplifying circuit includes MOSFETs (M3) to (M10). MOSFETs (M3) to (M7) constitute a differential amplifier circuit, and MOSFETs (M8) to (M10) constitute an output amplifier circuit. The resistor (R4) and the capacitor (C1) perform phase compensation of the error amplifier circuit.
The drain current of the MOSFET (M7) becomes a bias current of the differential amplifier circuit. The gate of the MOSFET (M7) is connected to the reference voltage (Vref).

Since the MOSFET (M2) and the MOSFET (M7) constitute a current mirror circuit, the drain current of the MOSFET (M7) (the bias current of the differential amplifier circuit) is the drain current of the MOSFET (M2), that is, the reference voltage generating circuit. Proportional to current consumption.
Since the MOSFET (M9) is a load of the output amplifier circuit and forms a current mirror circuit with the MOSFET (M2) like the MOSFET (M7), the drain current of the MOSFET (M9) is also consumed by the reference voltage generating circuit. Is proportional to

That is, in the manufacturing process of the semiconductor device, when the process variation occurs and the consumption current of the reference voltage generation circuit (the drain current of the depletion type NchMOSFET (M1) at 0 bias) varies, the reference voltage output from the reference voltage generation circuit As (Vref) changes, the bias current of the error amplifier circuit also changes.
When the bias current changes, the current consumption of the semiconductor device changes, which may deviate from the current consumption standard. Further, since the value necessary for phase compensation of the error amplifier circuit also changes, there may occur a case where the phase compensation circuit formed by the resistor (R4) and the capacitor (C1) built in the semiconductor device cannot be compensated. The operation of the error amplification circuit may become unstable. For this reason, it is necessary to keep the bias current within a predetermined range.

When the reference voltage (Vref) varies, the output voltage (Vout) also varies. Therefore, when the output voltage (Vout) exceeds a predetermined range, the ratio between the output voltage detection resistors (R1) and (R2) is set. It is necessary to change to be within a predetermined voltage range.
The output voltage detection resistors (R1) and (R2) are resistors built in the semiconductor device, and the ratio of the resistor (R1) and the resistor (R2) is made relatively accurately, but the resistance value varies depending on the process. It varies greatly depending on.
The current detection resistor (R3) is also a resistor built in the semiconductor device, and detects a current flowing through the MOSFET (M10). The voltage drop of the resistor (R3) passes through a current detection circuit (not shown) and is input to the overcurrent protection circuit to protect the constant voltage circuit from overcurrent. The resistance value of the current detection resistor (R3) needs to ensure the accuracy of the resistance value for current detection, but greatly changes due to process variations during manufacturing.

  In the present invention, a semiconductor device including a plurality of constant voltage circuits as shown in FIG. 1 in a chip has the same configuration and the same configuration as the reference voltage generation circuit used in the constant voltage circuit as shown in FIG. A characteristic monitor reference voltage generation circuit is provided. The monitor reference voltage generation circuit includes dedicated pads (T1) to (T3) for contacting the test probe, and the current consumption (I) and the reference voltage (Vref) of only the monitor reference voltage generation circuit can be measured. ing. However, the pad (T2) may be shared with the power source (Vss) on the negative side of the chip.

  In the wafer test 1, the current consumption (I) and the reference voltage (Vref) of the monitor reference voltage generation circuit are measured. As shown in FIG. 4, the characteristics of the semiconductor device may be quite different in the chip B that is far from the chip A on the wafer. However, the semiconductor device is in a very narrow range if it is on the same chip. These characteristics can be regarded as almost the same. Therefore, the characteristics of the monitor reference voltage generation circuit and the characteristics of the reference voltage generation circuit included in another constant voltage circuit in the same chip can be regarded as substantially the same.

  For this reason, as described above, by measuring the characteristics of the monitor reference voltage generation circuit, the bias current and output voltage (Vout) of the error amplification circuit constituting the constant voltage circuit in the same chip are actually measured. Therefore, the correction value necessary for trimming the bias current and the output voltage detection resistors (R1) and (R2) can be obtained. As described above, it is possible to move from the process in which the measurement is conventionally repeated by the number of constant voltage circuits included in the chip to the next process only by measuring the characteristic of one monitor reference voltage generation circuit. As a result, it has become possible to greatly improve the process time.

  FIG. 6 shows an example in which the Nch MOSFET (M7) for generating the bias current of the differential amplifier circuit can be trimmed. In FIG. 6, the Nch MOSFET (M7) is composed of three elements NchMOSFETs (M7A) to (M7C), and fuses (F1) to (F3) are connected to the drains of the elements. Since the consumption current (I) of the monitor reference voltage generation circuit and the bias current are in a proportional relationship, the consumption current (I) of the monitor reference voltage generation circuit is measured in the wafer test step 1, and the difference from the reference value is examined. Decide how to trim the bias current. When the bias current is configured by three elements NchMOSFETs (M7A) to (M7C) as shown in FIG. 6, seven types of bias current values can be set according to the trimming method. Of course, if the number is four or more, it is possible to further increase the types of current values that can be set by trimming.

The Nch MOSFET (M9) generating the bias current of the output amplifier circuit is exactly the same as the Nch MOSFET (M7) described above.
FIG. 7 shows an embodiment for trimming the output voltage detection resistors (R1) and (R2). The resistor (R1) is composed of three resistors (R1A) to (R1C), and fuses (F4) and (F5) are connected in series to the resistor (R1B) and the resistor (R1C) respectively. A series connection is connected in parallel, and is further connected in series with a resistor (R1A). The resistor (R2) also includes resistors (R2A) to (R2C), a fuse (F6), and a fuse (F7), and the connection is the same as that of the resistor (R1).

  The output voltage (Vout) of the constant voltage circuit is a value obtained by multiplying the reference voltage (Vref) by the ratio of the output voltage detection resistors (R1) and (R2). In process fluctuations during semiconductor manufacturing, even if the absolute value of the resistance changes greatly, the direction of change is the same, so the change in the ratio between the resistors is small, and the accuracy of the ratio is extremely high. The output voltage (Vout) of the constant voltage circuit can be predicted only by measuring the voltage (Vref). Therefore, it is possible to know how to set the ratio of the resistor (R1) and the resistor (R2) without measuring the output voltage (Vout) of the constant voltage circuit. Based on the setting, in the laser trimming process, The fuses (F4) to (F7) are trimmed. In the embodiment of FIG. 7, the ratio of the resistor (R1) to the resistor (R2) can be nine combinations, but if the number of resistors connected in series with a fuse is further added, finer trimming can be set. It is.

As shown in FIG. 3, a monitoring resistive element is added to arbitrary pads (T1) to (T3) of the monitor reference voltage generating circuit shown in FIG. 2, for example, pad (T2) and newly added pad (T4) in FIG. By measuring the resistance value of this resistor in the wafer test 1, it is possible to measure the effect of process variations on the resistance value. Since the resistance value of the current detection resistor (R3) in FIG. 1 is proportional to the resistance value of the resistor (R0) in FIG. 3, the resistor (R0) connected between the pad (T2) and the pad (T4) in FIG. ) Is measured, and the trimming amount of the resistor (R3) can be estimated from the deviation from the reference resistance value.
For the trimming configuration of the resistor (R3), a method generally used conventionally such as the configuration of the resistor (R1) can be used.

The example of the constant voltage circuit used for this invention is shown. FIG. 2 is a diagram illustrating an example of a monitor reference voltage generation circuit having the same configuration and the same characteristics as the reference voltage generation circuit used in the constant voltage circuit of FIG. 1. It is the figure which showed the other example of the monitor reference voltage generation circuit. It is the figure which showed the example of the wafer. An example of a schematic process for manufacturing a conventional semiconductor device will be described. This is an example in which the Nch MOSFET (M7) of FIG. It is the figure which showed the structural example of the output voltage detection resistance (R1) of FIG. 1, (R2).

Explanation of symbols

M1 Depletion type NchMOSFET
M2, M5 to M10, M7A to M7C NchMOSFET
M3, M4 PchMOSFET
R0-R4, R1A-R1C, R2A-R2C Resistor C1 Capacitor T1-T4 Pad F1-F7 Fuse

Claims (13)

In a semiconductor device comprising a plurality of reference voltage generation circuits on one chip of a semiconductor device formed in large numbers on a wafer, and using the output voltage and / or current consumption of the reference voltage generation circuit in a circuit in the chip ,
A semiconductor device comprising a monitor reference voltage generation circuit having the same circuit configuration as that of the reference voltage generation circuit formed on the chip. The monitor reference voltage generation circuit includes:
A depletion type Nch MOSFET,
Enhancement type NchMOSFET,
With
The source of the depletion type NchMOSFET is connected to the drain of the enhancement type NchMOSFET, and the gates of both FETs are connected to the connection point.
Using the voltage between the source and drain of the enhancement type Nch MOSFET as a reference voltage output,
2. The semiconductor device according to claim 1, wherein a probe contact pad is provided on the drain of the depletion type Nch MOSFET, the source of the enhancement type Nch MOSFET, and the reference voltage output.   3. The semiconductor device according to claim 2, wherein a source of the enhancement type Nch MOSFET is connected to a negative power source (Vss) of the semiconductor device, and a pad provided on the source is omitted. 4. The semiconductor device according to claim 1, wherein a circuit test in the chip is performed in a wafer test step 1, and at least an output voltage and / or current consumption of the reference voltage generation circuit is performed in a next step. In a method of manufacturing a semiconductor device comprising a laser trimming step for correcting the characteristics of the circuit due to manufacturing variations of
In the wafer test 1 step, the output voltage and / or current consumption of the monitor reference voltage generation circuit is measured,
A method of manufacturing a semiconductor device, wherein the circuit is trimmed on the same chip as the monitor reference voltage generation circuit in a laser trimming step of the next step based on the measurement result. A plurality of constant voltage circuits each including at least a reference voltage generation circuit, an error amplification circuit, and an output voltage detection resistor are built on one chip, and the output voltage detection is performed to adjust the output voltage of the plurality of constant voltage circuits. In the semiconductor device in which trimming of the resistor is performed so that the output voltage of the constant voltage circuit falls within a predetermined voltage range,
A semiconductor device comprising a monitor reference voltage generation circuit having the same circuit configuration as that of the reference voltage generation circuit formed on the chip. In the manufacturing method of the semiconductor device of Claim 5,
The output voltage of the monitor reference voltage generation circuit is measured in one wafer test process, and the plurality of constant voltages on the same chip as the monitor reference voltage generation circuit are measured in the next laser trimming process based on the measurement result. A method of manufacturing a semiconductor device, wherein trimming of each of the output voltage detection resistors included in a circuit is performed. A plurality of constant voltage circuits each including at least a reference voltage generation circuit, an error amplification circuit, and an output voltage detection resistor are built on one chip, and the bias current of the error amplification circuit included in the plurality of constant voltage circuits is In the semiconductor device in which trimming is performed so that the bias current of the error amplifier circuit falls within a predetermined current range,
The bias current of the error amplifier circuit is proportional to the current consumption of the reference voltage generation circuit,
A semiconductor device comprising a monitor reference voltage generation circuit having the same circuit configuration as that of the reference voltage generation circuit formed on the chip. 8. The semiconductor device according to claim 7, wherein the current consumption of the monitor reference voltage generation circuit is measured in one wafer test step, and in the next laser trimming step performed based on the measurement result,
A method of manufacturing a semiconductor device, characterized in that a bias current of the error amplification circuit included in the plurality of constant voltage circuits on the same chip as the monitor reference voltage generation circuit is trimmed. The monitor reference voltage generation circuit includes:
A depletion type Nch MOSFET,
Enhancement type NchMOSFET,
With
The source of the depletion type NchMOSFET is connected to the drain of the enhancement type NchMOSFET, and the gates of both FETs are connected to the connection point.
Using the voltage between the source and drain of the enhancement type Nch MOSFET as a reference voltage output,
8. The semiconductor device according to claim 5, wherein a probe contact pad is provided on the drain of the depletion type Nch MOSFET, the source of the enhancement type Nch MOSFET, and the reference voltage output.   10. The semiconductor device according to claim 9, wherein a source of the enhancement type Nch MOSFET is connected to the negative power source (Vss), and a pad provided on the source is omitted.   11. The semiconductor device according to claim 9, further comprising a monitor resistor having one end connected to an arbitrary pad of the monitor reference voltage generating circuit and the other end connected to an independent pad. In the manufacturing method of the semiconductor device of Claim 11,
The resistance value of the monitor resistor is measured in one wafer test process,
Based on the measurement result, in the next laser trimming step, trimming of the fixed resistor on the same chip as the monitor reference voltage generating circuit and requiring the absolute value of the resistance value included in the plurality of constant voltage circuits is performed. A method of manufacturing a semiconductor device, wherein the method is performed. The bias current generation circuit of the error amplifier circuit is composed of an enhancement type NchMOSFET that constitutes a reference voltage and a plurality of NchMOSFETs that constitute a current mirror circuit, and a trimming fuse is connected to the drain or source of the plurality of NchMOSFETs 9. The semiconductor device according to claim 7 or 8, wherein:

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