CN114690837B - Band-gap reference voltage generating circuit based on power supply voltage - Google Patents
Band-gap reference voltage generating circuit based on power supply voltage Download PDFInfo
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- CN114690837B CN114690837B CN202210499365.8A CN202210499365A CN114690837B CN 114690837 B CN114690837 B CN 114690837B CN 202210499365 A CN202210499365 A CN 202210499365A CN 114690837 B CN114690837 B CN 114690837B
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- 230000001360 synchronised effect Effects 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 claims description 4
- 230000003362 replicative effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
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Abstract
The invention discloses a band gap reference voltage generating circuit based on power supply voltage, which comprises: the reference voltage acquisition circuit, the reference current acquisition circuit, the reference voltage acquisition circuit and the synchronous control circuit are connected among the reference voltage acquisition circuit, the reference current acquisition circuit and the reference voltage acquisition circuit. According to the band-gap reference voltage generating circuit based on the power supply voltage, the reference voltage acquiring circuit acquires the reference voltage in cooperation with the power supply voltage, the reference current acquiring circuit acquires the reference current according to the reference voltage and the power supply voltage, and the reference voltage acquiring circuit acquires the reference voltage according to the reference current, so that stable reference voltage based on the power supply voltage is obtained to be used in the floating PSUB circuit.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a bandgap reference voltage generating circuit based on a supply voltage.
Background
The bandgap reference voltage generating circuit is used for generating a reference voltage, and is a very common circuit in a semiconductor chip. Conventional bandgap reference voltage generating circuits generate reference voltages directly and oppositely, but in the design of some special circuits (such as floating PSUB circuits), reference voltages need to be generated for power supply voltages, and conventional bandgap reference voltage generating circuits cannot meet the requirements.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a band gap reference voltage generating circuit based on a power supply voltage, which can generate a reference voltage based on the power supply voltage.
To achieve the above object, an embodiment of the present invention provides a bandgap reference voltage generating circuit based on a power supply voltage, including: reference voltage acquisition circuit, reference current acquisition circuit, reference voltage acquisition circuit and synchronous control circuit.
The reference voltage acquisition circuit is used for acquiring a reference voltage through a power supply voltage; the reference current acquisition circuit is used for acquiring a reference current through a power supply voltage and a reference voltage; the reference voltage acquisition circuit is used for acquiring a reference voltage through a reference current; the synchronous control circuit is connected among the reference voltage acquisition circuit, the reference current acquisition circuit and the reference voltage acquisition circuit and is used for synchronizing the reference voltage to the reference current acquisition circuit and controlling the synchronous state between the reference current acquisition circuit and the reference voltage acquisition circuit.
In one or more embodiments of the present invention, the reference voltage acquisition circuit includes a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, and a potential synchronization unit;
the base and collector of first triode and second triode all connect power supply voltage, the first end of first resistance is connected to the projecting pole of first triode, the first end of second resistance is connected to the projecting pole of second triode, the first end of third resistance is connected to the second end of second resistance, the second end of third resistance links to each other with the second end of first resistance to link to each other with the potential synchronization unit, the second end of third resistance still is used for outputting reference voltage, the potential synchronization unit is used for controlling the projecting pole potential of first triode and the second end potential of second resistance equal.
In one or more embodiments of the present invention, the reference voltage is:
wherein ,VBE1 is the voltage between the base and the emitter of the first triode, VBE2 is the voltage between the base and the emitter of the second triode, k is the Boltzmann constant, q is the charge value constant of electrons, T is the absolute temperature, n is the size ratio of the second triode to the first triode, ln (n) is the natural logarithm of n>At normal temperature, VIN is power supply voltage, and R2 and R3 are the resistance values of the second resistor and the third resistor respectively.
In one or more embodiments of the present invention, the potential synchronization unit includes a first amplifier and a first MOS transistor, a first input end of the first amplifier is connected to an emitter of the first transistor, a second input end of the first amplifier is connected to a second end of the second resistor, a drain electrode of the first MOS transistor is connected to the second end of the first resistor, an output end of the first amplifier is connected to a gate electrode of the first MOS transistor, and a source electrode of the first MOS transistor is grounded.
In one or more embodiments of the present invention, the potential synchronization unit further includes a second MOS transistor, a gate of the second MOS transistor is connected to an output end of the first amplifier, a drain of the second MOS transistor is connected to a source of the first MOS transistor, the source of the second MOS transistor is grounded, and a gate of the first MOS transistor is connected to a control voltage.
In one or more embodiments of the present invention, the reference current obtaining circuit includes a fourth resistor, a first end of the fourth resistor is connected to a power supply voltage, and a second end of the fourth resistor is connected to a synchronization control circuit.
In one or more embodiments of the present invention, the synchronization control circuit includes a second amplifier and a third MOS transistor, a first input end of the second amplifier is connected to the reference current acquisition circuit and a source electrode of the third MOS transistor, a second input end of the second amplifier is connected to the reference voltage acquisition circuit to acquire the reference voltage and synchronize the reference voltage to the reference current acquisition circuit through the first input end, an output end of the second amplifier is connected to a gate electrode of the third MOS transistor, and a drain electrode of the third MOS transistor is connected to the reference voltage acquisition circuit.
In one or more embodiments of the present invention, the first MOS transistor and the third MOS transistor are both high voltage isolation bias transistors.
In one or more embodiments of the present invention, a plurality of current mirrors for copying the reference current are provided between the synchronization control circuit and the reference voltage acquisition circuit.
In one or more embodiments of the present invention, the reference voltage acquiring circuit includes a fifth resistor, one end of which is connected to the current mirror and the output end to output the reference voltage, and the other end is grounded.
In one or more embodiments of the invention, the first transistor and the second transistor are each non-fully isolated parasitic vertical NPN transistors.
Compared with the prior art, the band-gap reference voltage generating circuit based on the power supply voltage acquires the reference voltage through the reference voltage acquiring circuit matched with the power supply voltage, acquires the reference current according to the reference voltage and the power supply voltage through the reference current acquiring circuit, and acquires the reference voltage according to the reference current through the reference voltage acquiring circuit, so that the stable reference voltage based on the power supply voltage is obtained to be used in the floating PSUB circuit.
Drawings
Fig. 1 is a circuit schematic of a bandgap reference voltage generating circuit based on a supply voltage according to an embodiment of the invention.
Fig. 2 is an effect verification diagram of a bandgap reference voltage generating circuit based on a power supply voltage according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a non-fully isolated parasitic vertical NPN transistor according to an embodiment of the invention.
Fig. 4 is a flowchart of a voltage generation method of a bandgap reference voltage generation circuit based on a supply voltage according to an embodiment of the invention.
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
As shown in fig. 1, a bandgap reference voltage generating circuit based on a power supply voltage according to an embodiment of the invention includes: reference voltage acquisition circuit 10, synchronization control circuit 20, reference current acquisition circuit 30, and reference voltage acquisition circuit 40. The reference voltage acquisition circuit 10, the reference current acquisition circuit 30, and the reference voltage acquisition circuit 40 are all connected to the synchronization control circuit 20.
As shown in fig. 1, the reference voltage acquisition circuit 10 is simultaneously connected to a power supply voltage VIN, and the reference voltage acquisition circuit 10 acquires a reference voltage VCM through the power supply voltage VIN and outputs the reference voltage VCM to the synchronization control circuit 20.
It should be noted that in one embodiment, synchronization as used herein refers to making the voltage values of two points equal or having a known relationship. In yet another embodiment, the synchronization described in the present invention refers to making the current values of the two branches equal or having a known relationship.
The reference voltage acquisition circuit 10 in the present embodiment includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a potential synchronization unit 11.
Specifically, the base and collector of the first triode Q1 and the second triode Q2 are both connected to the power supply voltage VIN, the emitter of the first triode Q1 is connected to the first end of the first resistor R1, the emitter of the second triode Q2 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the second end of the first resistor R1 and is connected to the potential synchronization unit 11, the second end of the third resistor R3 is further used for outputting the reference voltage VCM, and the potential synchronization unit 11 is used for controlling the emitter potential of the first triode Q1 to be equal to the potential of the second end of the second resistor R2.
In addition, the potential synchronization unit 11 includes a first amplifier A1, a first MOS transistor M1, and a second MOS transistor M2.
Specifically, a first input end of the first amplifier A1 is connected to an emitter of the first triode Q1, and a second input end of the first amplifier A1 is connected to a second end of the second resistor R2. The drain electrode of the first MOS tube M1 is connected with the second end of the first resistor R1, the grid electrode of the first MOS tube M1 is connected with the control voltage VBIAS, and the source electrode of the first MOS tube M1 is connected with the drain electrode of the second MOS tube M2. The grid electrode of the second MOS tube M2 is connected with the output end of the first amplifier A1, and the source electrode of the second MOS tube M2 is grounded.
In other embodiments, the second MOS transistor M2 may be omitted, and the output end of the first amplifier A1 is directly connected to the first MOS transistor M1, that is, the first input end of the first amplifier A1 is connected to the emitter of the first triode Q1, and the second input end of the first amplifier A1 is connected to the second end of the second resistor R2. The drain electrode of the first MOS tube M1 is connected with the second end of the first resistor R1, the output end of the first amplifier A1 is connected with the grid electrode of the first MOS tube M1, and the source electrode of the first MOS tube M1 is grounded.
The first input terminal of the first amplifier A1 in this embodiment is a negative input terminal, and the second input terminal of the first amplifier A1 is a positive input terminal. In other embodiments, the first input of the first amplifier A1 may be a positive input and the second input of the first amplifier A1 may be a negative input.
In the present embodiment, according to the characteristic that the potentials of the first input terminal and the second input terminal of the first amplifier A1 are equal, the potential between the emitter of the first transistor Q1 and the first resistor R1 is made equal to the potential between the second resistor R2 and the third resistor R3, thereby obtaining the reference voltage:
wherein ,VBE1 is the voltage between the base and emitter of the first transistor Q1, VBE2 is the voltage between the base and emitter of the second transistor Q2, k is the Boltzmann constant, Q is the charge value constant of the electrons, T is absolute temperature, n is the size ratio of the second transistor Q2 to the first transistor Q1, ln (n) is the natural logarithm of n>Constant at normal temperature (about 26 mV), VIN is the power supply voltage, and R2 and R3 are the resistances of the second resistor and the third resistor, respectively.
As shown in fig. 1, the synchronization control circuit 20 is configured to synchronize the reference voltage VCM to the reference current acquisition circuit 30 and control a synchronization state between the reference current acquisition circuit 30 and the reference voltage acquisition circuit 40.
The synchronization control circuit 20 in this embodiment includes a second amplifier A2 and a third MOS transistor M3.
Specifically, the first input terminal of the second amplifier A2 is connected to the reference current acquisition circuit 30 and the source of the third MOS transistor M3, and the second input terminal of the second amplifier A2 is connected to the reference voltage acquisition circuit 10 to acquire the reference voltage VCM and synchronize the reference voltage VCM to the reference current acquisition circuit 30 through the first input terminal. I.e. the second input of the second amplifier A2 is connected to the second terminal of the first resistor R1 for receiving the reference voltage VCM. The output end of the second amplifier A2 is connected with the grid electrode of the third MOS tube, and the drain electrode of the third MOS tube is connected with the reference voltage acquisition circuit 40.
As can be seen from the above, the reference voltage VCM can be synchronized to the reference current obtaining circuit 30 to obtain the reference current I1 according to the characteristic that the potentials of the first input terminal and the second input terminal of the second amplifier A2 are equal.
In addition, in the on state of the third MOS transistor M3, the reference current acquiring circuit 30 and the reference voltage acquiring circuit 40 are in a synchronous state. That is, the third MOS transistor M3 is controlled to be turned on by the second amplifier A2, so that the reference current I1 can be introduced into the reference voltage acquisition circuit 40.
In this embodiment, the first input terminal of the second amplifier A2 is a negative input terminal, and the second input terminal of the second amplifier A2 is a positive input terminal. In other embodiments, the first input of the second amplifier A2 may be a positive input and the second input of the second amplifier A2 may be a negative input.
As shown in fig. 1, the reference current acquisition circuit 30 is simultaneously connected to the power supply voltage VIN, and acquires the reference current I1 from the voltage difference between the power supply voltage VIN and the reference voltage VCM.
The reference current acquisition circuit 30 in the present embodiment includes a fourth resistor R4 that connects the power supply voltage VIN and the synchronization control circuit 20. That is, the first end of the fourth resistor R4 is connected to the power supply voltage VIN, and the second end of the fourth resistor R4 is connected to the first input end of the second amplifier A2, thereby obtaining a reference current i1= (VIN-VCM)/R4.
As shown in fig. 1, the reference current I1 flows into the reference voltage acquisition circuit 40 via the synchronization control circuit 20, and the reference voltage acquisition circuit 40 acquires the reference voltage VREF by the reference current I1. In the present embodiment, a current mirror for reproducing the reference current I1 is also provided between the synchronization control circuit 20 and the reference voltage acquisition circuit 40.
The current mirrors in this embodiment are provided with two sets, a first current mirror 51 and a second current mirror 52, respectively. In other embodiments, no current mirror or other number of current mirrors may be provided. The synchronization control circuit 20, the first current mirror 51, and the second current mirror 52 are sequentially connected to the reference voltage acquisition circuit 40. The first current mirror 51 includes a fourth MOS transistor M4 and a fifth MOS transistor M5 that are connected in a common gate, and the second current mirror 52 includes a sixth MOS transistor M6 and a seventh MOS transistor M7 that are connected in a common gate.
Specifically, the gate and the drain of the fourth MOS transistor M4 are connected to each other and to the drain of the third MOS transistor M3, the sources of the fourth MOS transistor M4 and the fifth MOS transistor M5 are both grounded, the drain of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6, the drain of the sixth MOS transistor M6 is connected to the gate, and the sources of the sixth MOS transistor M6 and the seventh MOS transistor M7 are connected to each other and to the voltage PREVDD.
The reference voltage acquisition circuit 40 in the present embodiment includes a fifth resistor R5. The first end of the fifth resistor R5 is configured to receive the reference current I1 and output the reference voltage VREF, and the second end of the fifth resistor R5 is grounded.
Specifically, the first end of the fifth resistor R5 is connected to the second current mirror 52 and the output end to output the reference voltage VREF, and the second end of the fifth resistor R5 is grounded. That is, a first end of the fifth resistor R5 is connected to the drain electrode and the output end of the seventh MOS transistor M7, a second end of the fifth resistor is grounded, and the reference voltage VREF is output through the output end.
In the present embodiment, the reference current I1 flows to the fifth resistor R5 through the third MOS transistor M3, the first current mirror 51, and the second current mirror 52, so as to obtain the reference voltage vref=i1×r5.
As shown in fig. 2, in the present embodiment, when the power supply voltage VIN is 30V, a stable reference voltage VREF of 1.20977V can be obtained.
The first transistor Q1 and the second transistor Q2 in this embodiment are all non-fully isolated parasitic vertical NPN transistors as shown in fig. 3, so as to ensure independence from PSUB.
The first MOS transistor M1 in this embodiment is a high-voltage isolation bias transistor to protect the second MOS transistor M2 as a low-voltage transistor, and the third MOS transistor M3 is a high-voltage isolation bias transistor to protect each current mirror.
In the embodiment, the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, and the fifth MOS transistor M5 are all NMOS transistors; the third MOS tube M3, the sixth MOS tube M6 and the seventh MOS tube M7 are PMOS tubes. In other embodiments, the NMOS and PMOS tubes may be interchanged.
In the present embodiment, the reference voltage obtaining circuit 10 is matched with the power supply voltage VIN to obtain the reference voltage VCM, the reference current obtaining circuit 30 is used for obtaining the reference current I1 according to the reference voltage and the power supply voltage, and the reference voltage obtaining circuit 40 is used for obtaining the reference voltage VREF based on the stability of the power supply voltage VIN for the floating PSUB circuit according to the reference current I1.
As shown in fig. 4, the present embodiment further discloses a voltage generation method of the bandgap reference voltage generation circuit based on the power supply voltage, including:
acquiring a reference voltage through a power supply voltage;
acquiring a reference current through a power supply voltage and a reference voltage;
the reference voltage is obtained by the reference current.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (9)
1. A bandgap reference voltage generation circuit based on a supply voltage, comprising:
a reference voltage acquisition circuit for acquiring a reference voltage by a power supply voltage;
the reference voltage acquisition circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor and a potential synchronization unit;
the base and collector of the first triode and the second triode are both connected with power supply voltage, the emitter of the first triode is connected with the first end of the first resistor, the emitter of the second triode is connected with the first end of the second resistor, the second end of the second resistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the second end of the first resistor and is connected with the potential synchronization unit, the second end of the third resistor is also used for outputting reference voltage, and the potential synchronization unit is used for controlling the emitter potential of the first triode to be equal to the potential of the second end of the second resistor;
the potential synchronization unit comprises a first amplifier and a first MOS tube, wherein a first input end of the first amplifier is connected with an emitter of the first triode, a second input end of the first amplifier is connected with a second end of the second resistor, a drain electrode of the first MOS tube is connected with the second end of the first resistor, an output end of the first amplifier is connected with a grid electrode of the first MOS tube, and a source electrode of the first MOS tube is grounded;
a reference current acquisition circuit for acquiring a reference current through a power supply voltage and a reference voltage; a reference voltage acquisition circuit for acquiring a reference voltage by a reference current; and
and the synchronous control circuit is connected among the reference voltage acquisition circuit, the reference current acquisition circuit and the reference voltage acquisition circuit and is used for synchronizing the reference voltage to the reference current acquisition circuit and controlling the synchronous state between the reference current acquisition circuit and the reference voltage acquisition circuit.
2. The bandgap reference voltage generation circuit based on supply voltage of claim 1, wherein said reference voltage is:
wherein ,VBE1 is the voltage between the base and the emitter of the first triode, VBE2 is the voltage between the base and the emitter of the second triode, k is the Boltzmann constant, q is the charge value constant of electrons, T is the absolute temperature, n is the size ratio of the second triode to the first triode, ln (n) is the natural logarithm of n>At normal temperature, VIN is power supply voltage, and R2 and R3 are the resistance values of the second resistor and the third resistor respectively.
3. The bandgap reference voltage generation circuit based on supply voltage according to claim 1, wherein said potential synchronization unit further comprises a second MOS transistor, a gate of said second MOS transistor is connected to an output terminal of said first amplifier, a drain of said second MOS transistor is connected to a source of said first MOS transistor, a source of said second MOS transistor is grounded, and a gate of said first MOS transistor is connected to a control voltage.
4. The bandgap reference voltage generation circuit based on supply voltage according to claim 1, wherein said reference current acquisition circuit comprises a fourth resistor, a first terminal of said fourth resistor being connected to the supply voltage, and a second terminal of said fourth resistor being connected to the synchronization control circuit.
5. The bandgap reference voltage generation circuit based on supply voltage according to claim 1, wherein the synchronization control circuit comprises a second amplifier and a third MOS transistor, a first input terminal of the second amplifier is connected to the reference current acquisition circuit and a source of the third MOS transistor, a second input terminal of the second amplifier is connected to the reference voltage acquisition circuit to acquire the reference voltage and synchronize the reference voltage to the reference current acquisition circuit through the first input terminal, an output terminal of the second amplifier is connected to a gate of the third MOS transistor, and a drain of the third MOS transistor is connected to the reference voltage acquisition circuit.
6. The bandgap reference voltage generation circuit based on supply voltage according to claim 5, wherein said first and third MOS transistors are high voltage isolation bias transistors.
7. The bandgap reference voltage generation circuit based on supply voltage according to claim 1, wherein a plurality of current mirrors for replicating a reference current are provided between said synchronization control circuit and said reference voltage acquisition circuit.
8. The bandgap reference voltage generation circuit based on supply voltage according to claim 1, wherein said reference voltage acquisition circuit comprises a fifth resistor, a first end of said fifth resistor for receiving a reference current and outputting a reference voltage, a second end of said fifth resistor being grounded.
9. The bandgap reference voltage generation circuit based on supply voltage of claim 1, wherein said first transistor and said second transistor are non-fully isolated parasitic vertical NPN transistors.
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| CN202210499365.8A CN114690837B (en) | 2022-04-27 | 2022-04-27 | Band-gap reference voltage generating circuit based on power supply voltage |
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