CN114690837A - Band-gap reference voltage generating circuit based on power supply voltage - Google Patents
Band-gap reference voltage generating circuit based on power supply voltage Download PDFInfo
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Abstract
The invention discloses a band-gap reference voltage generating circuit based on power supply voltage, which comprises: the synchronous control circuit is connected among the reference voltage acquisition circuit, the reference current acquisition circuit and the reference voltage acquisition circuit. According to the band-gap reference voltage generating circuit based on the power supply voltage, the reference voltage obtaining circuit is matched with the power supply voltage to obtain the reference voltage, the reference current obtaining circuit obtains the reference current according to the reference voltage and the power supply voltage, and the reference voltage obtaining circuit obtains the reference voltage according to the reference current, so that the stable reference voltage based on the power supply voltage is obtained and used in the floating PSUB circuit.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a bandgap reference voltage generating circuit based on a power supply voltage.
Background
The bandgap reference voltage generating circuit is used for generating a reference voltage, and is a very common circuit in a semiconductor chip. The conventional bandgap reference voltage generation circuit directly generates a reference voltage for ground, but in the design of some special circuits (such as a floating PSUB circuit), the reference voltage needs to be generated for a power supply voltage, and the conventional bandgap reference voltage generation circuit cannot meet the requirements.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a band-gap reference voltage generating circuit based on a power supply voltage, which can generate a reference voltage based on the power supply voltage.
To achieve the above object, an embodiment of the present invention provides a bandgap reference voltage generating circuit based on a power supply voltage, including: the circuit comprises a reference voltage acquisition circuit, a reference current acquisition circuit, a reference voltage acquisition circuit and a synchronous control circuit.
The reference voltage acquisition circuit is used for acquiring reference voltage through power supply voltage; the reference current acquisition circuit is used for acquiring reference current through power voltage and reference voltage; the reference voltage acquisition circuit is used for acquiring reference voltage through reference current; the synchronous control circuit is connected among the reference voltage acquisition circuit, the reference current acquisition circuit and the reference voltage acquisition circuit, and is used for synchronizing the reference voltage to the reference current acquisition circuit and controlling the synchronous state between the reference current acquisition circuit and the reference voltage acquisition circuit.
In one or more embodiments of the present invention, the reference voltage obtaining circuit includes a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, and a potential synchronizing unit;
the base electrode and the collector electrode of the first triode and the second triode are both connected with a power supply voltage, the emitter electrode of the first triode is connected with the first end of the first resistor, the emitter electrode of the second triode is connected with the first end of the second resistor, the second end of the second resistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the second end of the first resistor and is connected with the potential synchronization unit, the second end of the third resistor is also used for outputting a reference voltage, and the potential synchronization unit is used for controlling the potential of the emitter electrode of the first triode to be equal to the potential of the second end of the second resistor.
In one or more embodiments of the present invention, the reference voltage is:
wherein ,
VBE1 is the voltage between the base and emitter of the first transistor, VBE2 is the voltage between the base and emitter of the second transistor, k is Boltzmann's constant, q is the charge value constant of the electrons, T is the absolute temperature, n is the dimensional ratio of the second transistor to the first transistor, ln (n) is the natural logarithm of n,
and the constant is constant at normal temperature, VIN is power supply voltage, and R2 and R3 are resistance values of the second resistor and the third resistor respectively.
In one or more embodiments of the present invention, the potential synchronization unit includes a first amplifier and a first MOS transistor, a first input terminal of the first amplifier is connected to an emitter of the first triode, a second input terminal of the first amplifier is connected to a second terminal of the second resistor, a drain of the first MOS transistor is connected to a second terminal of the first resistor, an output terminal of the first amplifier is connected to a gate of the first MOS transistor, and a source of the first MOS transistor is grounded.
In one or more embodiments of the present invention, the potential synchronization unit further includes a second MOS transistor, a gate of the second MOS transistor is connected to the output terminal of the first amplifier, a drain of the second MOS transistor is connected to a source of the first MOS transistor, a source of the second MOS transistor is grounded, and a gate of the first MOS transistor is connected to the control voltage.
In one or more embodiments of the present invention, the reference current obtaining circuit includes a fourth resistor, a first terminal of the fourth resistor is connected to the power supply voltage, and a second terminal of the fourth resistor is connected to the synchronization control circuit.
In one or more embodiments of the present invention, the synchronous control circuit includes a second amplifier and a third MOS transistor, a first input terminal of the second amplifier is connected to the reference current obtaining circuit and a source of the third MOS transistor, a second input terminal of the second amplifier is connected to the reference voltage obtaining circuit to obtain a reference voltage and synchronize the reference voltage to the reference current obtaining circuit through the first input terminal, an output terminal of the second amplifier is connected to a gate of the third MOS transistor, and a drain of the third MOS transistor is connected to the reference voltage obtaining circuit.
In one or more embodiments of the present invention, the first MOS transistor and the third MOS transistor are both high-voltage isolation bias transistors.
In one or more embodiments of the invention, a plurality of current mirrors for copying the reference current are arranged between the synchronous control circuit and the reference voltage acquisition circuit.
In one or more embodiments of the present invention, the reference voltage obtaining circuit includes a fifth resistor, one end of the fifth resistor is connected to the current mirror and the output terminal to output the reference voltage, and the other end of the fifth resistor is grounded.
In one or more embodiments of the present invention, the first transistor and the second transistor are both non-fully isolated parasitic vertical NPN transistors.
Compared with the prior art, according to the band-gap reference voltage generating circuit based on the power supply voltage, the reference voltage is obtained through the reference voltage obtaining circuit in cooperation with the power supply voltage, the reference current is obtained through the reference current obtaining circuit according to the reference voltage and the power supply voltage, the reference voltage is obtained through the reference voltage obtaining circuit according to the reference current, and therefore stable reference voltage based on the power supply voltage is obtained and used in the floating PSUB circuit.
Drawings
Fig. 1 is a circuit schematic diagram of a bandgap reference voltage generating circuit based on a power supply voltage according to an embodiment of the present invention.
Fig. 2 is a diagram for verifying the effect of the bandgap reference voltage generating circuit based on the power supply voltage according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a non-fully isolated parasitic vertical NPN transistor according to an embodiment of the invention.
Fig. 4 is a flowchart of a voltage generation method of a bandgap reference voltage generation circuit based on a power supply voltage according to an embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
As shown in fig. 1, in an embodiment of the present invention, a bandgap reference voltage generating circuit based on a power supply voltage includes: a reference voltage acquisition circuit 10, a synchronization control circuit 20, a reference current acquisition circuit 30, and a reference voltage acquisition circuit 40. The reference voltage acquisition circuit 10, the reference current acquisition circuit 30, and the reference voltage acquisition circuit 40 are all connected to the synchronous control circuit 20.
As shown in fig. 1, the reference voltage obtaining circuit 10 is connected to the power voltage VIN, and the reference voltage obtaining circuit 10 obtains the reference voltage VCM from the power voltage VIN and outputs the reference voltage VCM to the synchronization control circuit 20.
It is noted that in one embodiment, the synchronization described herein refers to equalizing or having a known relationship between the voltage values of two points. In yet another embodiment, the synchronization described herein refers to making the current values of the two branches equal or have a known relationship.
The reference voltage obtaining circuit 10 in this embodiment includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a potential synchronization unit 11.
Specifically, the base electrodes and the collector electrodes of the first transistor Q1 and the second transistor Q2 are both connected to the supply voltage VIN, the emitter electrode of the first transistor Q1 is connected to the first end of the first resistor R1, the emitter electrode of the second transistor Q2 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the second end of the first resistor R1 and is connected to the potential synchronization unit 11, the second end of the third resistor R3 is further configured to output a reference voltage, and the VCM potential synchronization unit 11 is configured to control the potential of the emitter electrode of the first transistor Q1 to be equal to the potential of the second end of the second resistor R2.
In addition, the potential synchronizing unit 11 includes a first amplifier a1, a first MOS transistor M1, and a second MOS transistor M2.
Specifically, a first input terminal of the first amplifier a1 is connected to an emitter of the first transistor Q1, and a second input terminal of the first amplifier a1 is connected to a second terminal of the second resistor R2. The drain of the first MOS transistor M1 is connected to the second terminal of the first resistor R1, the gate of the first MOS transistor M1 is connected to the control voltage VBIAS, and the source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2. The gate of the second MOS transistor M2 is connected to the output terminal of the first amplifier a1, and the source of the second MOS transistor M2 is grounded.
In other embodiments, the second MOS transistor M2 may be eliminated, and the output terminal of the first amplifier a1 is directly connected to the first MOS transistor M1, that is, the first input terminal of the first amplifier a1 is connected to the emitter of the first transistor Q1, and the second input terminal of the first amplifier a1 is connected to the second terminal of the second resistor R2. The drain of the first MOS transistor M1 is connected to the second end of the first resistor R1, the output end of the first amplifier a1 is connected to the gate of the first MOS transistor M1, and the source of the first MOS transistor M1 is grounded.
In this embodiment, the first input terminal of the first amplifier a1 is a negative input terminal, and the second input terminal of the first amplifier a1 is a positive input terminal. In other embodiments, the first input of the first amplifier a1 may be a positive input and the second input of the first amplifier a1 may be a negative input.
In the present embodiment, according to the characteristic that the potentials of the first input terminal and the second input terminal of the first amplifier a1 are equal, the potential between the emitter of the first transistor Q1 and the first resistor R1 is made equal to the potential between the second resistor R2 and the third resistor R3, so that the reference voltage is obtained:
wherein ,
VBE1 is the voltage between the base and emitter of the first transistor Q1, VBE2 is the voltage between the base and emitter of the second transistor Q2, k is the boltzmann constant, Q is the charge value constant of electrons, T is the absolute temperature, n is the ratio of the dimensions of the second transistor Q2 and the first transistor Q1, ln (n) is the natural logarithm of n,
constant (about 26mV) at normal temperature, VIN is the power supply voltage, and R2 and R3 are the resistances of the second resistor and the third resistor, respectively.
As shown in fig. 1, the synchronization control circuit 20 is configured to synchronize the reference voltage VCM to the reference current obtaining circuit 30 and control a synchronization state between the reference current obtaining circuit 30 and the reference voltage obtaining circuit 40.
The synchronous control circuit 20 in the present embodiment includes a second amplifier a2 and a third MOS transistor M3.
Specifically, a first input terminal of the second amplifier a2 is connected to the reference current obtaining circuit 30 and the source of the third MOS transistor M3, and a second input terminal of the second amplifier a2 is connected to the reference voltage obtaining circuit 10 to obtain the reference voltage VCM and synchronize the reference voltage VCM to the reference current obtaining circuit 30 through the first input terminal. That is, the second input terminal of the second amplifier a2 is connected to the second terminal of the first resistor R1 to receive the reference voltage VCM. The output end of the second amplifier a2 is connected to the gate of the third MOS transistor, and the drain of the third MOS transistor is connected to the reference voltage acquisition circuit 40.
As can be seen from the above, according to the characteristic that the potentials of the first input terminal and the second input terminal of the second amplifier a2 are equal, the reference voltage VCM can be synchronized to the reference current obtaining circuit 30 to obtain the reference current I1.
In addition, when the third MOS transistor M3 is in the on state, the reference current obtaining circuit 30 and the reference voltage obtaining circuit 40 are in the synchronous state. That is, the third MOS transistor M3 is controlled to be turned on by the second amplifier a2, so that the reference current I1 can be introduced into the reference voltage obtaining circuit 40.
In this embodiment, the first input terminal of the second amplifier a2 is a negative input terminal, and the second input terminal of the second amplifier a2 is a positive input terminal. In other embodiments, the first input of the second amplifier a2 may be a positive input and the second input of the second amplifier a2 may be a negative input.
As shown in fig. 1, the reference current obtaining circuit 30 is connected to the power voltage VIN to obtain the reference current I1 according to the voltage difference between the power voltage VIN and the reference voltage VCM.
The reference current obtaining circuit 30 in this embodiment includes a fourth resistor R4 connected between the power supply voltage VIN and the synchronous control circuit 20. That is, a first end of the fourth resistor R4 is connected to the power voltage VIN, and a second end of the fourth resistor R4 is connected to a first input end of the second amplifier a2, so as to obtain the reference current I1 ═ (VIN-VCM)/R4.
As shown in fig. 1, the reference current I1 flows into the reference voltage obtaining circuit 40 through the synchronous control circuit 20, and the reference voltage obtaining circuit 40 obtains the reference voltage VREF through the reference current I1. In the present embodiment, a current mirror for copying the reference current I1 is further provided between the synchronous control circuit 20 and the reference voltage acquisition circuit 40.
The current mirrors in this embodiment are provided in two sets, a first current mirror 51 and a second current mirror 52. In other embodiments, no current mirrors or other numbers of current mirrors may be provided. The synchronization control circuit 20, the first current mirror 51, and the second current mirror 52 are connected to the reference voltage acquisition circuit 40 in this order. The first current mirror 51 comprises a fourth MOS transistor M4 and a fifth MOS transistor M5 which are connected in a common gate mode, and the second current mirror 52 comprises a sixth MOS transistor M6 and a seventh MOS transistor M7 which are connected in a common gate mode.
Specifically, the gate and the drain of the fourth MOS transistor M4 are connected to the drain of the third MOS transistor M3, the sources of the fourth MOS transistor M4 and the fifth MOS transistor M5 are both grounded, the drain of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6, the drain of the sixth MOS transistor M6 is connected to the gate, and the sources of the sixth MOS transistor M6 and the seventh MOS transistor M7 are connected to the voltage PREVDD.
The reference voltage acquisition circuit 40 in the present embodiment includes a fifth resistor R5. The first end of the fifth resistor R5 is used for receiving the reference current I1 and outputting the reference voltage VREF, and the second end of the fifth resistor R5 is grounded.
Specifically, a first terminal of the fifth resistor R5 is connected to the second current mirror 52 and the output terminal to output the reference voltage VREF, and a second terminal of the fifth resistor R5 is grounded. That is, a first end of the fifth resistor R5 is connected to the drain of the seventh MOS transistor M7 and the output terminal, and a second end of the fifth resistor is grounded to output the reference voltage VREF through the output terminal.
In the present embodiment, the reference current I1 flows to the fifth resistor R5 through the third MOS transistor M3, the first current mirror 51, and the second current mirror 52, so as to obtain the reference voltage VREF I1 × R5.
As shown in fig. 2, in the present embodiment, when the power supply voltage VIN is 30V, a stable reference voltage VREF of 1.20977V can be obtained.
In this embodiment, the first transistor Q1 and the second transistor Q2 both use a non-fully isolated parasitic vertical NPN transistor as shown in fig. 3, thereby ensuring independence from PSUB.
The first MOS transistor M1 in this embodiment is a high-voltage isolation bias transistor to protect the second MOS transistor M2, which is a low-voltage transistor, and the third MOS transistor M3 is a high-voltage isolation bias transistor to protect the current mirrors.
In the embodiment, the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, and the fifth MOS transistor M5 are all NMOS transistors; the third MOS transistor M3, the sixth MOS transistor M6 and the seventh MOS transistor M7 are all PMOS transistors. In other embodiments, the NMOS and PMOS transistors may be interchanged.
In this embodiment, the reference voltage VCM is obtained by the reference voltage obtaining circuit 10 in cooperation with the power supply voltage VIN, the reference current I1 is obtained by the reference current obtaining circuit 30 according to the reference voltage and the power supply voltage, and the reference voltage VREF is obtained by the reference voltage obtaining circuit 40 according to the reference current I1, so that the stable reference voltage VREF based on the power supply voltage VIN is obtained for the floating PSUB circuit.
As shown in fig. 4, the present embodiment further discloses a voltage generating method of a bandgap reference voltage generating circuit based on a power supply voltage, including:
acquiring a reference voltage through a power supply voltage;
acquiring a reference current through a power supply voltage and a reference voltage;
the reference voltage is obtained by the reference current.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (11)
1. A bandgap reference voltage generating circuit based on a supply voltage, comprising:
the reference voltage acquisition circuit is used for acquiring reference voltage through power supply voltage;
the reference current acquisition circuit is used for acquiring reference current through power voltage and reference voltage;
a reference voltage acquisition circuit for acquiring a reference voltage by a reference current; and
and the synchronous control circuit is connected among the reference voltage acquisition circuit, the reference current acquisition circuit and the reference voltage acquisition circuit and is used for synchronizing the reference voltage to the reference current acquisition circuit and controlling the synchronous state between the reference current acquisition circuit and the reference voltage acquisition circuit.
2. The supply voltage based bandgap reference voltage generating circuit of claim 1, wherein the reference voltage obtaining circuit comprises a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a potential synchronizing unit;
the base electrode and the collector electrode of the first triode and the second triode are both connected with a power supply voltage, the emitter electrode of the first triode is connected with the first end of the first resistor, the emitter electrode of the second triode is connected with the first end of the second resistor, the second end of the second resistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the second end of the first resistor and is connected with the potential synchronization unit, the second end of the third resistor is also used for outputting a reference voltage, and the potential synchronization unit is used for controlling the potential of the emitter electrode of the first triode to be equal to the potential of the second end of the second resistor.
3. The supply voltage based bandgap reference voltage generating circuit of claim 2, wherein said reference voltage is:
wherein ,
VBE1 is the voltage between the base and emitter of the first transistor, VBE2 is the voltage between the base and emitter of the second transistor, k is Boltzmann's constant, q is the charge value constant of electrons, T is the absolute temperature, n is the dimensional ratio of the second transistor to the first transistor, ln (n) is the natural logarithm of n,
constant at normal temperature, VIN is power voltage, and R2 and R3 are resistance values of the second resistor and the third resistor respectively.
4. The supply voltage based bandgap reference voltage generating circuit of claim 2, wherein said potential synchronizing unit comprises a first amplifier and a first MOS transistor, a first input terminal of said first amplifier is connected to an emitter of a first transistor, a second input terminal of said first amplifier is connected to a second terminal of a second resistor, a drain of said first MOS transistor is connected to a second terminal of said first resistor, an output terminal of said first amplifier is connected to a gate of said first MOS transistor, and a source of said first MOS transistor is grounded.
5. The supply voltage based bandgap reference voltage generating circuit of claim 4, wherein said potential synchronizing unit further comprises a second MOS transistor, a gate of said second MOS transistor is connected to the output terminal of said first amplifier, a drain of said second MOS transistor is connected to the source of said first MOS transistor, a source of said second MOS transistor is grounded, and a gate of said first MOS transistor is connected to said control voltage.
6. The supply voltage based bandgap reference voltage generating circuit of claim 1, wherein said reference current obtaining circuit comprises a fourth resistor, a first terminal of said fourth resistor is connected to a supply voltage, and a second terminal of said fourth resistor is connected to a synchronous control circuit.
7. The supply voltage based bandgap reference voltage generating circuit according to claim 4, wherein said synchronous control circuit comprises a second amplifier and a third MOS transistor, a first input terminal of said second amplifier is connected to said reference current obtaining circuit and a source of said third MOS transistor, a second input terminal of said second amplifier is connected to said reference voltage obtaining circuit for obtaining a reference voltage and synchronizing said reference voltage to said reference current obtaining circuit through said first input terminal, an output terminal of said second amplifier is connected to a gate of said third MOS transistor, and a drain of said third MOS transistor is connected to said reference voltage obtaining circuit.
8. The supply voltage based bandgap reference voltage generating circuit of claim 7, wherein said first and third MOS transistors are high voltage isolation bias transistors.
9. The supply voltage based bandgap reference voltage generating circuit as claimed in claim 1, wherein a plurality of current mirrors for copying the reference current are arranged between said synchronous control circuit and the reference voltage obtaining circuit.
10. The supply voltage based bandgap reference voltage generating circuit of claim 1, wherein said reference voltage obtaining circuit comprises a fifth resistor, a first end of said fifth resistor is used for receiving a reference current and outputting a reference voltage, and a second end of said fifth resistor is connected to ground.
11. The supply voltage based bandgap reference voltage generating circuit of claim 2, wherein said first and second transistors are non-fully isolated parasitic vertical NPN transistors.
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