CN107861562B - Current generating circuit and implementation method thereof - Google Patents
Current generating circuit and implementation method thereof Download PDFInfo
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- CN107861562B CN107861562B CN201711072180.4A CN201711072180A CN107861562B CN 107861562 B CN107861562 B CN 107861562B CN 201711072180 A CN201711072180 A CN 201711072180A CN 107861562 B CN107861562 B CN 107861562B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/267—Current mirrors using both bipolar and field-effect technology
Abstract
The invention discloses a current generating circuit and a realization method thereof, wherein the circuit comprises: a positive temperature coefficient PTAT current generating circuit for generating a positive temperature coefficient current I0(ii) a A bias circuit for stabilizing the gate voltage of each PMOS tube of the mirror constant current sourceA design value; a first mirror constant current source for providing the current I for the positive temperature coefficient PTAT current generating circuit0And the current is sent to a second mirror image constant current source; a second mirror constant current source for supplying a positive temperature coefficient current I in the form of a current source0A current Iref of positive temperature coefficient converted into a current sink form; the invention provides a negative temperature coefficient CTAT current generating and synthesizing circuit which is used for generating a current with a negative temperature coefficient and combining the current with a current Iref with a positive temperature coefficient to form an output current with small temperature dependence.
Description
Technical Field
The present invention relates to a current generating circuit and a method for implementing the same, and more particularly, to a current generating circuit with less or even no temperature dependency and a method for implementing the same.
Background
In a digital-analog hybrid system on chip, a reference current source provides an appropriate bias for each analog module of the system, and becomes an indispensable part of the system, and is widely used in circuits such as an operational amplifier and a/D, D/a.
The reference current source should be invariant to temperature, voltage, and various process parameters based on the requirements of the on-chip application. However, several mainstream Reference currents currently exist, and the problem of high power consumption of the Circuit due to large Temperature Coefficient or complicated Circuit design generally exists, for example, the Temperature Coefficient of the Circuit test proposed in document 1(Chen J, Shi B.1V CMOS Current Reference with 50 ppm/DEG C Temperature Coefficient [ J ]. Electron.Lett.,2003,39:209-210) is 50 ppm/DEG C, and the Reference 2(Franco Fiori, Paolo Steno Croverti.A New Component Temperature Compensated CMOS Current Reference [ J ]. IEEE trans.on Circuit and System II: Briefs, 52.) proposes a non-bandgap Circuit to generate the Reference Current by second-order Temperature compensation, and the Temperature Coefficient is 28 ppm/DEG C. Document 3(Dehg hani R, Ataro di S M.A New Low Voltage precision CMOS Current reference w ith no Ex terminal Compounds [ J ]. IEEE Trans. on Cir c. Syst. II: Analo g and Digital Signal Processing,2003,50(12):928-932) proposes that the negative temperature effects of generating the positive temperature coefficient reference voltage and mobility using a bandgap reference circuit cancel each other out to generate the reference Current, but the temperature coefficient is greater than 15 ppm/DEG C. Document 4 (zhongyun, lujian, wu shiming, jiang asia dong. a low-voltage low-temperature-drift reference current source [ J ] modern electronic technology, 2009,285 (8): 178-.
Disclosure of Invention
In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a current generating circuit and a method for implementing the same, so as to generate a current reference source with low power consumption and small temperature dependency.
To achieve the above and other objects, the present invention provides a current generating circuit, including:
a positive temperature coefficient PTAT current generating circuit for generating a positive temperature coefficient current I0；
The bias circuit is used for stabilizing the grid voltage of each PMOS tube of the mirror constant current source at a design value;
a first mirror constant current source for providing the current I for the positive temperature coefficient PTAT current generating circuit0And the current is sent to a second mirror image constant current source;
a second mirror constant current source for supplying a positive temperature coefficient current I in the form of a current source0A current Iref of positive temperature coefficient converted into a current sink form;
the negative temperature coefficient CTAT current generating and synthesizing circuit is used for generating a current with a negative temperature coefficient and combining the current with a current Iref with a positive temperature coefficient to form an output current with small temperature dependence.
Further, the positive temperature coefficient PTAT current generating circuit includes a first PNP triode, a second PNP triode, and a first resistor, collectors and bases of the first PNP triode and the second PNP triode are grounded, an emitter of the first PNP triode is connected to one end of the first resistor, the other end of the first resistor is connected to the bias circuit and the first mirror image constant current source, and an emitter of the second PNP triode is connected to the bias circuit and the first mirror image constant current source.
Further, the size ratio of the first PNP triode to the second PNP triode is N: 1.
further, the bias circuit comprises a first operational amplifier, an inverting input end of the first operational amplifier is connected with the first resistor and the first mirror image constant current source, a non-inverting input end of the first operational amplifier is connected with an emitter of the second PNP transistor and the first mirror image constant current source, and an output end of the first operational amplifier is connected with the first mirror image constant current source.
Further, the first mirror image constant current source comprises a first PMOS transistor, a second PMOS transistor and a third PMOS transistor, a gate of the first PMOS transistor is connected with a gate of the second PMOS transistor and a gate of the third PMOS transistor and connected to an output end of the first operational amplifier, a source of the first PMOS transistor, a source of the second PMOS transistor and a source of the third PMOS transistor are connected with a power voltage, a drain of the first PMOS transistor is connected with the first resistor and an inverting input end of the first operational amplifier, a drain of the second PMOS transistor is connected with an emitter of the second PNP transistor and a non-inverting input end of the second operational amplifier, and a drain of the third PMOS transistor outputs a current Iref of a positive temperature coefficient to the second mirror image constant current source.
Further, the size ratio of the first PMOS transistor to the second PMOS transistor to the third PMOS transistor is 1: 1: 1.
furthermore, the second mirror image constant current source comprises a first NMOS tube and a second NMOS tube, the drain electrode of the first NMOS tube is connected to the drain electrode of the third PMOS tube, the gate drain electrode of the second NMOS tube is connected to the gate electrode of the first NMOS tube and connected to the negative temperature coefficient CTAT current generation and synthesis circuit, and the source electrodes of the first NMOS tube and the second NMOS tube are grounded.
Furthermore, the negative temperature coefficient CTAT current generating and synthesizing circuit comprises a fourth PMOS tube and a second resistor, wherein the drain electrode of the fourth PMOS tube is connected with the gate drain electrode of the second NMOS tube, the source electrode of the fourth PMOS tube is connected with the power voltage, the second resistor is connected between the gate electrode of the fourth PMOS tube and the power voltage, and the gate electrode of the fourth PMOS tube outputs the output current with small temperature dependence.
Further, the current output by the grid electrode of the fourth PMOS tube is
Wherein, IrefIs the current of the positive temperature coefficient of the current sink type, M is the ratio of the sizes of the first NMOS tube and the second NMOS tube, (W/L)P4Is the width-to-length ratio of the fourth PMOS tube, COXIs a unit area gate capacitance, Vth4The hole mobility μ of the fourth PMOS transistor PM4pIs a quantity inversely proportional to temperature, R2Is the resistance of the second resistor.
In order to achieve the above object, the present invention further provides a method for implementing a current generating circuit, including the following steps:
step one, a positive temperature coefficient PTAT current generating circuit is used for generating a current I with a positive temperature coefficient0；
Step two, utilizing a first mirror constant current source to convert the current I0Outputting to a second mirror constant current source to output a current I with positive temperature coefficient in the form of a current source0A current Iref of positive temperature coefficient converted into a current sink form;
and step three, generating and synthesizing a current with a negative temperature coefficient by using the negative temperature coefficient CTAT current, combining the current with the current Iref with the positive temperature coefficient, and generating and outputting an output current with small temperature dependence.
Compared with the prior art, the current generation circuit and the implementation method thereof generate a current with a positive temperature coefficient through the positive temperature coefficient current generation circuit, the current with a negative temperature coefficient is generated by the negative temperature coefficient current generation and synthesis circuit and is combined with the current with the positive temperature coefficient, and the purpose of generating a current reference source which is not related to temperature is achieved based on a mechanism that mobility and threshold voltage are mutually compensated.
Drawings
FIG. 1 is a circuit diagram of a current generating circuit according to the present invention;
fig. 2 is a flowchart illustrating steps of a method for implementing a current generation circuit according to the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 1 is a circuit diagram of a current generating circuit according to the present invention. As shown in fig. 1, a current generation circuit of the present invention includes: a positive temperature coefficient PTAT current generating circuit 10, a bias circuit 20, a first mirror constant current source 30, a second mirror constant current source 40 and a negative temperature coefficient CTAT current generating and synthesizing circuit 50.
The positive temperature coefficient PTAT current generating circuit 10 comprises a first PNP triode PNP1, a second PNP triode PNP2 and a first resistor R1, and is used for generating a current I of the positive temperature coefficient PTAT0(ii) a The bias circuit 20 is composed of a first operational amplifier OPA1, and is used for stabilizing the gate voltage of the first-third PMOS transistors PM 1-PM 3 of the mirror constant current source 30 at a design value; the mirror constant current source 30 is composed of a first PMOS transistor PM1, a second PMOS transistor PM2 and a third PMOS transistor PM3, and is configured to provide equal current I to the first PNP triode PNP1 and the second PNP triode PNP20And outputs the current to the second mirror constant current source 40; the second mirror image constant current Source 40 is composed of a first NMOS transistor NM1 and a second NMOS transistor NM2, and is used for converting the current I of the positive temperature coefficient PTAT in the form of a current Source (Source)0Current Iref converted to positive temperature coefficient PTAT in the form of a current Sink (Sink); the negative temperature coefficient CTAT current generating and synthesizing circuit 50 consists of a fourth PMOS tube PM4 and a second resistor R2, is used for generating a negative temperature coefficient current and combining the negative temperature coefficient current with a positive temperature coefficient current Iref to obtain the sum of the negative temperature coefficient current and the positive temperature coefficient current, and the negative temperature coefficient current is the threshold voltage V of the fourth PMOS tube with negative temperature characteristicsth4And (4) generating. It should be noted that 60 in the figure is a load circuit, which is composed of a third NMOS transistor NM3 and is used for simulating the load of the circuit.
In the specific embodiment of the invention, the collectors and the bases of a first PNP transistor PNP1 and a second PNP transistor PNP2 are grounded, the emitter of the first PNP transistor PNP1 is connected to one end of a first resistor R1, the other end of the first resistor R1 is connected to the inverting input terminal of a first operational amplifier OPA1 and the drain of a first PMOS transistor PM1, the emitter of a first PNP transistor PNP1 is connected to the non-inverting input terminal of the first operational amplifier OPA1, the drain of a second PMOS transistor PM2 and the non-inverting input terminal of the second operational amplifier OPA2, the gate of the first PMOS transistor PM1 is connected to the gate of a second PMOS transistor PM2 and the gate of a third PMOS transistor PM3, the source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, the source of a third PMOS transistor PM3 and the source of a fourth PMOS transistor PM4, the drain of the third PMOS transistor PM1 is connected to the drain of a first NMOS transistor NM drain 1 and the NM drain of the third NMOS transistor NM 6324, the gate of the first PMOS transistor PNP 599 and the drain of the NMOS transistor VDD, and the drain of the first NMOS transistor NMOS 639 are connected to the drain of the first PMOS transistor NMOS, The sources of the second NMOS transistor NM2 and the third NMOS transistor NM3 are grounded, the drain of the third NMOS transistor NM3 is connected to the gate of the fourth PMOS transistor PM4 and one end of the second resistor R2, and the other end of the second resistor R2 is connected to the power supply VDD.
Specifically, if the current flowing through the first PNP transistor PNP1 is I0Since the ratio of the size of the PMOS transistors supplying current to the first PNP transistor PNP1 and the second PNP transistor PNP2 is 1: 1, so the current flowing through the second PNP transistor PNP2 is also I0If the saturation current of the second PNP transistor PNP2 is ISSince the size ratio of the first PNP transistor PNP1 to the second PNP transistor PNP2 is N: 1, the saturation current of the first PNP transistor PNP1 is known to be N x I according to microelectronics theorySBased on the knowledge of the transistors, there is a base emitter voltage V of a second PNP transistor PNP2be2And the base-emitter voltage V of the first PNP transistor PNP1be1Respectively as follows:
the voltage difference is:
due to the first operational amplifierPresence of OPA1, voltage V1 ═ V2 ═ Vbe2Therefore, the voltage difference is the voltage drop of the first resistor R1, and the current flowing through the PNP1 is I0＝ΔVbeThe first PMOS tube PM1 is connected with the first PNP triode PNP1 in series, and the current flowing through the first PMOS tube PM1 is I0＝ΔVbeOn the other hand, the gate-source voltage of the third PMOS tube PM3 is the same as the gate-source voltage of the first PMOS tube PM1 and the gate-source voltage of the second PMOS tube PM2, so that the current flowing through the third PMOS tube PM3 is the same as the current flowing through the first PMOS tube PM1, and both I and I are I0＝ΔVbeand/R1, when VT is KT/q (where K is boltzmann's constant, T is thermodynamic temperature, and q is electronic charge), the current flowing through the first, second, and third PMOS transistors PM1, PM2, and PM3 is:
i.e. the current is a current proportional to the temperature.
The current flowing through the fourth PMOS transistor PM4 is:
therefore, the gate-source voltage of the fourth PMOS transistor PM4 is:
in the formula IP4＝M×Iref
Then output current
Wherein M is the ratio of transistors NM1 to NM2, (W/L)P4Is the width-to-length ratio, C, of the fourth PMOS transistor PM4OXIs a unit area gate capacitance, Vth4The hole mobility μ of the fourth PMOS transistor PM4pIs a quantity inversely proportional to temperature (temperature coefficient-1.5, which parameter has some correlation with the process), thus obtaining
Is a quantity proportional to temperature; vthIs a parameter inversely proportional to temperature by adjusting M (W/L) in the formulap4So that a current I with little or no temperature dependence can be obtainedout。
Therefore, the invention can generate a current reference source independent of temperature based on the mechanism that the mobility and the threshold voltage compensate each other. Experiments prove that the temperature coefficient of the reference current source obtained by the invention is 5 ppm/DEG C within a wide temperature range of-40-80 ℃, and the power consumption of the circuit is less than 10 microwatts.
Fig. 2 is a flowchart illustrating steps of a method for implementing a current generation circuit according to the present invention. As shown in fig. 2, the method for implementing a current generation circuit of the present invention includes the following steps:
In summary, the current generating circuit and the implementation method thereof of the present invention generate a current with positive temperature coefficient through the positive temperature coefficient current generating circuit, and the negative temperature coefficient current generating and synthesizing circuit generates a current with negative temperature coefficient and combines with the current with positive temperature coefficient, so as to achieve the purpose of generating a current reference source independent of temperature based on the mechanism of mutual compensation between mobility and threshold voltage.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (9)
1. A current generating circuit comprising:
a positive temperature coefficient PTAT current generating circuit for generating a positive temperature coefficient current I0；
The bias circuit is used for stabilizing the grid voltage of each PMOS tube of the mirror constant current source at a design value;
a first mirror constant current source for providing the current I for the positive temperature coefficient PTAT current generating circuit0And the current is sent to a second mirror image constant current source;
a second mirror constant current source for supplying a positive temperature coefficient current I in the form of a current source0A current Iref of positive temperature coefficient converted into a current sink form;
the negative temperature coefficient CTAT current generation and synthesis circuit is used for generating a current with a negative temperature coefficient and combining the current with a current Iref with a positive temperature coefficient to form an output current with small temperature dependence, the negative temperature coefficient CTAT current generation and synthesis circuit comprises a fourth PMOS tube and a second resistor, the drain electrode of the fourth PMOS tube is connected with the gate drain electrode of a second NMOS tube of the second mirror constant current source, the source electrode of the fourth PMOS tube is connected with power voltage, the second resistor is connected between the grid electrode of the fourth PMOS tube and the power voltage, and the grid electrode of the fourth PMOS tube outputs the output current with small temperature dependence.
2. A current generating circuit as claimed in claim 1, wherein: the positive temperature coefficient PTAT current generating circuit comprises a first PNP triode, a second PNP triode and a first resistor, wherein collecting electrodes and bases of the first PNP triode and the second PNP triode are grounded, an emitting electrode of the first PNP triode is connected to one end of the first resistor, the other end of the first resistor is connected with the bias circuit and the first mirror image constant current source, and an emitting electrode of the second PNP triode is connected to the bias circuit and the first mirror image constant current source.
3. A current generating circuit as claimed in claim 2, wherein: the size ratio of the first PNP triode to the second PNP triode is N: 1.
4. a current generating circuit as claimed in claim 2, wherein: the bias circuit comprises a first operational amplifier, the inverting input end of the first operational amplifier is connected with the first resistor and the first mirror image constant current source, the non-inverting input end of the first operational amplifier is connected with the emitter of the second PNP tube and the first mirror image constant current source, and the output end of the first operational amplifier is connected with the first mirror image constant current source.
5. A current generating circuit as claimed in claim 4, wherein: the first mirror image constant current source comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube and a third PMOS tube, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube and is connected to the output end of the first operational amplifier, the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected with power voltage, the drain electrode of the first PMOS tube is connected with the first resistor and the reverse-phase input end of the first operational amplifier, the drain electrode of the second PMOS tube is connected with the emitter electrode of the second PMOS tube and the in-phase input end of the second operational amplifier, and the drain electrode of the third PMOS tube outputs the current Iref of the positive temperature coefficient to the second mirror image constant current source.
6. A current generating circuit as claimed in claim 5, wherein: the sizes of the first PMOS tube, the second PMOS tube and the third PMOS tube are 1: 1: 1.
7. a current generating circuit as claimed in claim 5, wherein: the second mirror image constant current source comprises a first NMOS tube and a second NMOS tube, the drain electrode of the first NMOS tube is connected to the drain electrode of the third PMOS tube, the gate drain electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube after being connected, and is connected to the negative temperature coefficient CTAT current generation and synthesis circuit, and the source electrodes of the first NMOS tube and the second NMOS tube are grounded.
8. A current generating circuit as claimed in claim 1, wherein: the current output by the grid electrode of the fourth PMOS tube is
Wherein, IrefIs the current of the positive temperature coefficient of the current sink type, M is the ratio of the sizes of the first NMOS tube and the second NMOS tube, (W/L)P4Is the width-to-length ratio of the fourth PMOS tube, COXIs a unit area gate capacitance, Vth4The hole mobility μ of the fourth PMOS transistor PM4pIs a quantity inversely proportional to temperature, R2Is the resistance value of the second resistor.
9. A method for realizing a current generating circuit comprises the following steps:
step one, a positive temperature coefficient PTAT current generating circuit is used for generating a current I with a positive temperature coefficient0；
Step two, utilizing a first mirror constant current source to convert the current I0Outputting to a second mirror constant current source to output a current I with positive temperature coefficient in the form of a current source0A current Iref of positive temperature coefficient converted into a current sink form;
and step three, generating and synthesizing circuit by utilizing the current with negative temperature coefficient CTAT to generate a current with negative temperature coefficient, combining the current with the current Iref of positive temperature coefficient, generating and outputting an output current with small temperature correlation, wherein the current with negative temperature coefficient CTAT comprises a fourth PMOS tube and a second resistor, the drain electrode of the fourth PMOS tube is connected with the grid drain electrode of a second NMOS tube of the second mirror constant current source, the source electrode of the fourth PMOS tube is connected with the power supply voltage, the second resistor is connected between the grid electrode of the fourth PMOS tube and the power supply voltage, and the output current with small temperature correlation is output through the grid electrode of the fourth PMOS tube.
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| CN109917843B (en) * | 2019-04-17 | 2023-09-12 | 南京芯耐特半导体有限公司 | Self-biased constant current generation circuit structure and constant current generation method |
| EP3734244B1 (en) * | 2019-05-02 | 2021-11-10 | Siemens Aktiengesellschaft | Circuit arrangement and method for controlling a power semiconductor switch |
| CN110708809B (en) * | 2019-11-08 | 2021-07-23 | 四川遂宁市利普芯微电子有限公司 | Constant current source generating circuit of common-anode LED display screen driving chip |
| CN111897209B (en) * | 2020-05-19 | 2021-06-04 | 成都天锐星通科技有限公司 | Millimeter wave chip gain high-low temperature self-adaptive bias structure and method |
| CN112332786B (en) * | 2020-10-30 | 2023-09-05 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Chip-level fully-integrated low-gain temperature drift radio frequency amplifier |
| CN112230704B (en) * | 2020-11-17 | 2022-01-04 | 普冉半导体(上海)股份有限公司 | Reference current source circuit |
| CN113566997A (en) * | 2021-07-26 | 2021-10-29 | 深圳青铜剑技术有限公司 | Temperature sensing circuit |
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| US6911861B2 (en) * | 2003-08-07 | 2005-06-28 | Texas Instruments Incorporated | Current biasing circuit with temperature compensation and related methods of compensating output current |
| US7224210B2 (en) * | 2004-06-25 | 2007-05-29 | Silicon Laboratories Inc. | Voltage reference generator circuit subtracting CTAT current from PTAT current |
| CN102253684B (en) * | 2010-06-30 | 2013-06-26 | 中国科学院电子学研究所 | Bandgap reference circuit employing current subtraction technology |
| US8373496B2 (en) * | 2010-07-08 | 2013-02-12 | Texas Instruments Incorporated | Temperature compensated current source |
| US8947067B1 (en) * | 2011-01-19 | 2015-02-03 | Marvell International Ltd. | Automatic bandgap voltage calibration |
| CN103440015B (en) * | 2013-08-30 | 2015-04-15 | 厦门意行半导体科技有限公司 | Band-gap reference circuit |
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