CN107861562A - A kind of current generating circuit and its implementation - Google Patents

Abstract

The present invention discloses a current generation circuit and its realization method. The circuit comprises: a positive temperature coefficient PTAT current generation circuit for generating a current I ₀ with a positive temperature coefficient; a bias circuit for converting the mirror constant current source The grid voltage of each PMOS transistor is stable at the design value; the first mirror constant current source is used to provide the current _I0 for the positive temperature coefficient PTAT current generating circuit and this current to the second mirror constant current source; The second mirror constant current source is used to convert the current _I0 of the positive temperature coefficient of the current source form into the current Iref of the positive temperature coefficient of the current sink form; the negative temperature coefficient CTAT current generation and synthesis circuit is used to generate the negative temperature coefficient The current is combined with the positive temperature coefficient current Iref to form an output current with little dependence on temperature. Through the present invention, a current reference source with low power consumption and little dependence on temperature can be produced.

Description

A current generating circuit and its realization method

technical field

The present invention relates to a current generation circuit and its realization method, in particular to a current generation circuit with little or no temperature correlation and its realization method.

Background technique

In the digital-analog hybrid system-on-chip, the reference current source provides appropriate bias for each analog module of the system and becomes an indispensable part of the system. It is widely used in operational amplifiers, A/D, D/A and other circuits.

Based on the requirements of on-chip applications, the reference current source should not change with changes in temperature, voltage and various process parameters. However, the current mainstream reference currents generally have the problem of high temperature coefficient or complex circuit design, which leads to high power consumption of the circuit, such as document 1 (Chen J, Shi B. 1V CMOS Current Reference with 50ppm/℃Temperature Coefficient [J].Electron.Lett.,2003,39:209-210) the temperature coefficient of the circuit test is 50ppm/℃, document 2 (Franco Fiori, Paolo Stefano Crovetti.A New CompactTemperature Compensated CMOS Current Reference[J] .IEEE Trans. on Circuit and System II: Express Briefs, 2005, 52.) proposed a non-bandgap circuit to generate a reference current through second-order temperature compensation, with a temperature coefficient of 28ppm/°C. Document 3 (Dehg hani R, Ataro di S M.A New Low Voltage Precision CMOS Current Reference with no Ex ternal Components[J].IEEE Trans.on Cir c.Syst.II:Analog and Digital Signal Processing,2003, 50(12):928-932) proposed to use a bandgap reference circuit to generate a positive temperature coefficient reference voltage and the negative temperature effect of mobility to cancel each other out to generate a reference current, but the temperature coefficient is greater than 15ppm/°C. Document 4 (Zhou Yun, Lu Jian, Wu Zhiming, Jiang Yadong. A reference current source with low voltage and low temperature drift [J]. Modern Electronic Technology, 2009, 285(8): 178-181.) proposed a bandgap based reference The reference current is generated through second-order temperature compensation, the temperature coefficient is 8.1ppm/℃, and the power consumption of the circuit is several hundred microwatts.

Contents of the invention

In order to overcome the shortcomings of the above-mentioned prior art, the object of the present invention is to provide a current generating circuit and its implementation method, so as to realize generating a current reference source with low power consumption and little dependence on temperature.

In order to achieve the above and other purposes, the present invention proposes a current generating circuit, comprising:

A positive temperature coefficient PTAT current generating circuit, used to generate a positive temperature coefficient current I ₀ ;

The bias circuit is used to stabilize the gate voltage of each PMOS transistor of the mirror image constant current source at a design value;

The first mirror constant current source is used to provide the current _I0 for the positive temperature coefficient PTAT current generating circuit and the current to the second mirror constant current source;

The second mirror image constant current source is used to convert the current I ₀ of the positive temperature coefficient of the current source form into the current Iref of the positive temperature coefficient of the current sink form;

The negative temperature coefficient CTAT current generation and synthesis circuit is used to generate a negative temperature coefficient current and combine it with the positive temperature coefficient current Iref to form an output current with little temperature dependence.

Further, the positive temperature coefficient PTAT current generating circuit includes a first PNP transistor, a second PNP transistor and a first resistor, the collectors and bases of the first PNP transistor and the second PNP transistor are grounded, and the first The emitter of the PNP transistor is connected to one end of the first resistor, the other end of the first resistor is connected to the bias circuit and the first mirror constant current source, and the emitter of the second PNP transistor is connected to the bias circuit with the first mirror constant current source.

Further, the size ratio of the first PNP transistor to the second PNP transistor is N:1.

Further, the bias circuit includes a first operational amplifier, the inverting input terminal of the first operational amplifier is connected to the first resistor and the first mirror constant current source, and the non-inverting input terminal of the first operational amplifier is The terminal is connected to the emitter of the second PNP transistor and the first image constant current source, and the output end of the first operational amplifier is connected to the first image constant current source.

Further, the first image constant current source includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, and the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor. The gate is connected and connected to the output terminal of the first operational amplifier, the source of the first PMOS transistor, the source of the second PMOS transistor and the source of the third PMOS transistor are connected to the power supply voltage, and the first PMOS transistor is connected to the power supply voltage. The drain of the PMOS transistor is connected to the first resistor and the inverting input terminal of the first operational amplifier, and the drain of the second PMOS transistor is connected to the emitter of the second PNP transistor and the non-inverting input of the second operational amplifier. terminal, the drain of the third PMOS transistor outputs the positive temperature coefficient current Iref to the second mirror image constant current source.

Further, the size ratio of the first PMOS transistor, the second PMOS transistor and the third PMOS transistor is 1:1:1.

Further, the second mirror image constant current source includes a first NMOS transistor and a second NMOS transistor, the drain of the first NMOS transistor is connected to the drain of the third PMOS transistor, and the gate of the second NMOS transistor After the drain is connected, it is connected to the gate of the first NMOS transistor, and connected to the negative temperature coefficient CTAT current generation and synthesis circuit, and the sources of the first NMOS transistor and the second NMOS transistor are grounded.

Further, the negative temperature coefficient CTAT current generation and synthesis circuit includes a fourth PMOS transistor and a second resistor, the drain of the fourth PMOS transistor is connected to the gate-drain of the second NMOS transistor, and the source is connected to the power supply voltage, The second resistor is connected between the gate of the fourth PMOS transistor and a power supply voltage, and the gate of the fourth PMOS transistor outputs the output current with little temperature dependence.

Further, the current output by the gate of the fourth PMOS transistor is

Wherein, I _ref is the current of the positive temperature coefficient of the current sink form, M is the ratio of the size of the first NMOS tube to the second NMOS tube, (W/L) _P4 is the width-to-length ratio of the fourth PMOS tube, C _OX is the gate capacitance per unit area, V _th4 is the threshold voltage of the fourth PMOS transistor PM4, the hole mobility μ _p is a quantity inversely proportional to temperature, and R ₂ is the resistance value of the second resistor.

In order to achieve the above object, the present invention also provides a method for implementing a current generating circuit, comprising the following steps:

Step 1, using a positive temperature coefficient PTAT current generating circuit to generate a positive temperature coefficient current I ₀ ;

Step 2, using the first mirror image constant current source to output the current I ₀ to the second mirror image constant current source, converting the current I ₀ of the positive temperature coefficient of the current source form into the current Iref of the positive temperature coefficient of the current sink form;

Step 3, using the negative temperature coefficient CTAT current generating and synthesizing circuit to generate a negative temperature coefficient current and combine it with the positive temperature coefficient current Iref to generate and output an output current with little temperature dependence.

Compared with the prior art, a current generation circuit and its implementation method of the present invention generate a current with a positive temperature coefficient through a positive temperature coefficient current generation circuit, and a negative temperature coefficient current generation and synthesis circuit generates a current with a negative temperature coefficient and is combined with a positive temperature coefficient current generation circuit. The current combination of temperature coefficient, based on the mechanism of mutual compensation between mobility and threshold voltage, realizes the purpose of generating a temperature-independent current reference source and ground.

Description of drawings

Fig. 1 is the circuit structural diagram of a kind of electric current generating circuit of the present invention;

FIG. 2 is a flow chart of steps of a method for implementing a current generating circuit of the present invention.

Detailed ways

The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Fig. 1 is a circuit structure diagram of a current generating circuit of the present invention. As shown in Figure 1, a current generation circuit of the present invention includes: a positive temperature coefficient PTAT current generation circuit 10, a bias circuit 20, a first mirror image constant current source 30, a second mirror image constant current source 40, and a negative temperature coefficient CTAT Current generating and synthesizing circuit 50 .

Wherein, the positive temperature coefficient PTAT current generating circuit 10 is composed of the first PNP transistor PNP1, the second PNP transistor PNP2 and the first resistor R1, and is used to generate a positive temperature coefficient PTAT current I ₀ ; the bias circuit 20 is composed of the first operation OPA1 is used to stabilize the gate voltages of the first-third PMOS transistors PM1-PM3 of the mirror constant current source 30 at the design value; the mirror constant current source 30 is composed of the first PMOS transistor PM1, the second PMOS transistor PM2 and The 3rd PMOS tube PM3 is formed, is used for providing equal current I ₀ for the first PNP transistor PNP1, the second PNP transistor PNP2 and this current is output to the second mirror image constant current source 40; The second mirror image constant current source 40 is provided by the second mirror image constant current source 40 An NMOS transistor NM1 and a second NMOS transistor NM2 are used to convert the current _I0 of the positive temperature coefficient PTAT in the form of the current source (Source) into the current Iref of the positive temperature coefficient PTAT in the form of the current sink (Sink); the negative temperature coefficient The CTAT current generating and synthesizing circuit 50 is composed of a fourth PMOS transistor PM4 and a second resistor R2 for generating a current with a negative temperature coefficient and combining it with a current Iref with a positive temperature coefficient to obtain the sum of the two, and the current with a negative temperature coefficient is obtained by The threshold voltage V _th4 of the fourth PMOS transistor with negative temperature characteristics is generated. It should be noted here that 60 in the figure is a load circuit, which is composed of a third NMOS transistor NM3 and is used for the load of the analog circuit.

In a specific embodiment of the present invention, the collectors and bases of the first PNP transistor PNP1 and the second PNP transistor PNP2 are grounded, the emitter of the first PNP transistor PNP1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 One end is connected to the inverting input terminal of the first operational amplifier OPA1 and the drain of the first PMOS transistor PM1, and the emitter of the first PNP transistor PNP1 is connected to the non-inverting input terminal of the first operational amplifier OPA1 and the drain of the second PMOS transistor PM2 pole and the non-inverting input terminal of the second operational amplifier OPA2, the gate of the first PMOS transistor PM1 is connected with the gate of the second PMOS transistor PM2 and the gate of the third PMOS transistor PM3, the source of the first PMOS transistor PM1, the gate of the second PMOS transistor PM1 The source of the second PMOS transistor PM2, the source of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected to the power supply VDD, and the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor NM1 and the third NMOS transistor NM3. Gate, the gate of the first NMOS transistor NM1 is connected to the drain of the fourth PMOS transistor, the gate and drain of the second NMOS transistor NM2, the first NMOS transistor NM1, the second NMOS transistor NM2 and the third NMOS transistor NM3 The source of the third NMOS transistor NM3 is connected to the gate of the fourth PMOS transistor PM4 and one end of the second resistor R2, and the other end of the second resistor R2 is connected to the power supply VDD.

Specifically, if the current flowing through the first PNP transistor PNP1 is I ₀ , since the size ratio of the PMOS transistors that provide current to the first PNP transistor PNP1 and the second PNP transistor PNP2 is 1:1, the current flowing through the second PNP transistor The current of PNP2 is also I ₀ , if the saturation current of the second PNP transistor PNP2 is I _S , since the size ratio of the first PNP transistor PNP1 and the second PNP transistor PNP2 is N:1, then according to the theory of microelectronics, it is known that the first The saturation current of the PNP transistor PNP1 is N* _IS . According to the triode knowledge, the base-emitter voltage V _be2 of the second PNP transistor PNP2 and the base-emitter voltage V _be1 of the first PNP transistor PNP1 are respectively:

Its voltage difference is:

Due to the existence of the first operational amplifier OPA1, the voltage V1=V2=V _be2 , so this voltage difference is the voltage drop of the first resistor R1, so the current flowing through PNP1 is I ₀ =ΔV _be /R1, the first PMOS tube PM1 In series with the first PNP transistor PNP1, the current flowing through the first PMOS transistor PM1 is I ₀ =ΔV _be /R1, on the other hand, the gate-source of the third PMOS transistor PM3 and the first PMOS transistor PM1 and the second PMOS transistor PM2 The voltage is the same and the size is the same, so the current flowing through the third PMOS transistor PM3 is consistent with the current flowing through the first PMOS transistor PM1, both of which are I ₀ =ΔV _be /R1, and it is known that VT=KT/q (where K is Boltzmann's constant, T is the thermodynamic temperature, and q is the electronic charge), then the current flowing through the first PMOS transistor PM1, the second PMOS transistor PM2, and the third PMOS transistor PM3 is:

That is, the current is a current proportional to temperature.

The current flowing through the fourth PMOS transistor PM4 is:

Therefore, the gate-source voltage of the fourth PMOS transistor PM4 is:

Where I _P4 ＝M×I _ref

then the output current

Wherein M is the ratio of the transistor NM1 to the NM2 tube, (W/L) _P4 is the width-to-length ratio of the fourth PMOS transistor PM4, C _OX is the gate capacitance per unit area, V _th4 is the threshold voltage of the fourth PMOS transistor PM4, and the hole Mobility μ _p is a quantity that is inversely proportional to temperature (temperature coefficient -1.5, this parameter has a certain correlation with the process), so that is a quantity proportional to temperature; V _th is a parameter inversely proportional to temperature, by adjusting M(W/L) _p4 in the formula, a current I with little or no temperature correlation can be obtained _out .

It can be seen that the present invention can generate a temperature-independent current reference source based on the mutual compensation mechanism of mobility and threshold voltage. Experiments prove that in the wide temperature range of -40°C-80°C, the temperature coefficient of the reference current source obtained by the present invention is 5ppm/°C, and the power consumption of the circuit is less than 10 microwatts.

FIG. 2 is a flow chart of steps of a method for implementing a current generating circuit of the present invention. As shown in Figure 2, a method for realizing a current generating circuit of the present invention includes the following steps:

In step 201, a positive temperature coefficient PTAT current I ₀ is generated by using a positive temperature coefficient PTAT current generating circuit.

Step 202, using the first mirror constant current source to output the current I ₀ to the second mirror constant current source, converting the current I _{0 of the positive temperature coefficient PTAT in the form of the current source (Source) into a positive current I 0} in the form of the current sink (Sink). Current Iref with temperature coefficient PTAT.

Step 203, using the negative temperature coefficient CTAT current generation and synthesis circuit to generate a current with a negative temperature coefficient and combining it with the current Iref with the positive temperature coefficient to obtain the sum of the two, the current with a negative temperature coefficient is composed of a current with a negative temperature The threshold voltage V _th4 of the characteristic PMOS transistor is generated.

In summary, a current generation circuit and its implementation method of the present invention generate a current with a positive temperature coefficient through a current generation circuit with a positive temperature coefficient, and a current with a negative temperature coefficient is generated by a current generation and synthesis circuit with a negative temperature coefficient and combined with a current with a positive temperature coefficient The combination of currents, based on the mechanism of mutual compensation between mobility and threshold voltage, achieves the purpose of generating a temperature-independent current reference source and ground.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Any person skilled in the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (10)

1. a kind of current generating circuit, including：

Positive temperature coefficient PTAT current generation circuit, for producing the electric current I of a positive temperature coefficient₀；

Biasing circuit, for the grid voltage of each PMOS of mirror-image constant flow source is stable in design load；

First mirror-image constant flow source, for providing the electric current I for the positive temperature coefficient PTAT current generation circuit₀And by the electricity Flow to the second mirror-image constant flow source；

Second mirror-image constant flow source, for by the electric current I of the positive temperature coefficient of current source form₀Be converted to the positive temperature of current sink form Spend the electric current Iref of coefficient；

Negative temperature coefficient CTAT current produce and combiner circuit, for produce negative temperature coefficient electric current and with positive temperature coefficient Electric current Iref merges to form the output current small with temperature dependency.

A kind of 2. current generating circuit as claimed in claim 1, it is characterised in that：The positive temperature coefficient PTAT current produces Circuit includes the first PNP triode, the second PNP triode and first resistor, first PNP triode and the poles of the 2nd PNP tri- The colelctor electrode and base earth of pipe, the emitter stage of first PNP triode are connected to one end of first resistor, first electricity The other end of resistance connects the biasing circuit and first mirror-image constant flow source, and the emitter stage of second PNP triode connects To the biasing circuit and first mirror-image constant flow source.

A kind of 3. current generating circuit as claimed in claim 2, it is characterised in that：First PNP triode and described the The size ratio of two PNP triodes is N：1.

A kind of 4. current generating circuit as claimed in claim 2, it is characterised in that：The biasing circuit includes the first amplifier, The inverting input of first amplifier connects the first resistor and first mirror-image constant flow source, first amplifier it is same Phase input connects the emitter stage of second PNP pipe and first mirror-image constant flow source, and the output end of first amplifier connects Connect first mirror-image constant flow source.

A kind of 5. current generating circuit as claimed in claim 4, it is characterised in that：First mirror-image constant flow source includes first PMOS, the second PMOS, the 3rd PMOS, the grid of first PMOS and the grid of the second PMOS and the 3rd PMOS The grid of pipe is connected, and is connected to the output end of first amplifier, the source electrode of first PMOS, the source of the second PMOS The source electrode of pole and the 3rd PMOS connects supply voltage, and the first PMOS drain electrode connects the first resistor and described first The inverting input of amplifier, the drain electrode of second PMOS connect the emitter stage of second PNP pipe, the same phase of the second amplifier Input, the drain electrode of the 3rd PMOS export the electric current Iref of the positive temperature coefficient to second mirror-image constant flow source.

A kind of 6. current generating circuit as claimed in claim 5, it is characterised in that：First PMOS, the second PMOS, The size of 3rd PMOS is 1：1：1.

A kind of 7. current generating circuit as claimed in claim 5, it is characterised in that：Second mirror-image constant flow source includes first NMOS tube, the second NMOS tube, the drain electrode of first NMOS tube are connected to the 3rd PMOS drain electrode, second NMOS tube Grid leak be connected after be connected with the grid of first NMOS tube, and be connected to the negative temperature coefficient CTAT current and produce and conjunction Into circuit, first NMOS tube, the second NMOS tube source ground.

A kind of 8. current generating circuit as claimed in claim 7, it is characterised in that：The negative temperature coefficient CTAT current produces Include the 4th PMOS and second resistance with combiner circuit, the 4th PMOS drain electrode connects the grid leak of second NMOS tube Pole, source electrode connect supply voltage, and the second resistance is connected between the 4th PMOS grid and supply voltage, and described Four PMOS grids export the described and small output current of temperature dependency.

A kind of 9. current generating circuit as claimed in claim 7, it is characterised in that：The electricity of the 4th PMOS grid output Flow and be

<mrow> <msub> <mi>I</mi> <mrow> <mi>O</mi> <mi>U</mi> <mi>T</mi> </mrow> </msub> <mo>=</mo> <mo>|</mo> <mfrac> <msub> <mi>V</mi> <mrow> <mi>G</mi> <mi>S</mi> <mn>4</mn> </mrow> </msub> <mrow> <mi>R</mi> <mn>2</mn> </mrow> </mfrac> <mo>|</mo> <mo>=</mo> <mfrac> <mrow> <msqrt> <mfrac> <mrow> <mn>2</mn> <msub> <mi>I</mi> <mrow> <mi>r</mi> <mi>e</mi> <mi>f</mi> </mrow> </msub> <mo>&amp;times;</mo> <mi>M</mi> </mrow> <mrow> <msub> <mi>&amp;mu;</mi> <mi>P</mi> </msub> <msub> <mi>C</mi> <mrow> <mi>O</mi> <mi>X</mi> </mrow> </msub> <msub> <mrow> <mo>(</mo> <mi>W</mi> <mo>/</mo> <mi>L</mi> <mo>)</mo> </mrow> <mrow> <mi>P</mi> <mn>4</mn> </mrow> </msub> </mrow> </mfrac> </msqrt> <mo>+</mo> <msub> <mi>V</mi> <mrow> <mi>t</mi> <mi>h</mi> <mn>4</mn> </mrow> </msub> </mrow> <mrow> <mi>R</mi> <mn>2</mn> </mrow> </mfrac> </mrow>

Wherein, I_refFor the electric current of the positive temperature coefficient of the current sink form, M is the first NMOS tube and the second NMOS tube size Ratio, (W/L)_P4For the breadth length ratio of the 4th PMOS, C_OXFor unit area gate capacitance, V_th4For the 4th PMOS PM4 threshold Threshold voltage, hole mobility μ_pFor an amount being inversely proportional with temperature, R₂For the resistance of the second resistance.

10. a kind of implementation method of current generating circuit, comprises the following steps：

Step 1, the electric current I of a positive temperature coefficient is produced using positive temperature coefficient PTAT current generation circuit₀；

Step 2, using the first mirror-image constant flow source by electric current I₀Output is to the second mirror-image constant flow source, by the positive temperature of current source form Spend the electric current I of coefficient₀Be converted to the electric current Iref of the positive temperature coefficient of current sink form；

Step 3, using the negative temperature coefficient CTAT current produce with combiner circuit produce a negative temperature coefficient electric current and with The electric current Iref of the positive temperature coefficient merges, and produces and exports an output current small with temperature dependency.