WO2022236890A1 - Bandgap reference voltage generating circuit having high-order temperature compensation - Google Patents

Abstract

A bandgap reference voltage (VBG) generating circuit having high-order temperature compensation, capable of obtaining a temperature-insensitive bandgap reference voltage (VBG). The circuit comprises a first current source (Iptat, IPTAT1), a second current source (Ic, Ic1) and an adder (11, 42); the first current source (Iptat, Iptat1) is linearly related to temperature; the first current source (Iptat, Iptat1) generates a first voltage by means of a first resistor (R1); the second current source (Ic, Ic1) comprises a current item related to a temperature second order; the second current source (Ic, Ic1) generates a second voltage (VBE, VBE1) by means of a first bipolar transistor (Q1); the adder (11, 42) generates a bandgap reference voltage (VBG) independent of the temperature according to the first voltage and the second voltage (VBE, VBE1).

Description

Bandgap Reference Voltage Generation Circuit with High-Order Temperature Compensation technical field

The present application relates to the technical field of integrated circuits, and more particularly to a bandgap reference voltage generating circuit with high-order temperature compensation.

Background technique

Many electronic circuits, such as analog-to-digital converters, digital-to-analog converters, and DC-DC converters, require a stable and accurate reference voltage to operate effectively.

Referring to Figure 1, the conventional method of generating a temperature-insensitive reference voltage is to combine the base-emitter voltage (V _BE ) of a bipolar transistor (BJT) with a negative temperature coefficient and αΔV _BE with a positive temperature coefficient add up.

I _ptat =ΔV _BE /R ₁

V _BG =V _BE +αT

The reference voltage thus generated is generally called a bandgap reference voltage (Bandgap Reference Voltage, BGR) V _BG . By adjusting the coefficient α

It is possible to make V _BG insensitive to temperature and form a bell-shaped temperature curve in FIG. 2 . As can be seen from Figure 2, V _BG still has a temperature dependence, which is unacceptable for applications requiring very high accuracy, such as high-resolution (>16-bit) ADCs.

Contents of the invention

The purpose of the present application is to provide a bandgap reference voltage generation circuit with high-order temperature compensation to obtain a temperature-insensitive bandgap reference voltage.

The present application discloses a bandgap reference voltage generation circuit with high-order temperature compensation, including:

a first current source, the first current source is linearly related to temperature, and its correlation coefficient is α ₁ , and the first current source generates a first voltage through a first resistance;

a second current source, the second current source includes a current term related to the second order temperature with a correlation coefficient β, and the second current source generates a second voltage through the first bipolar transistor;

An adder that generates a temperature-independent bandgap reference voltage based on the first voltage and the second voltage.

In a preferred example, the second current source further includes a current item linearly related to temperature and a current item independent of temperature, the correlation coefficient of the current item linearly related to temperature is α ₄ , and the current item linearly related to temperature The current item and the temperature-independent current item are respectively connected in parallel with the second-order temperature-dependent current item, and the temperature-linearly-dependent current item, temperature-independent current item, and temperature-second-order-dependent current item The superposition forms the second current source.

In a preferred example, it further includes: a current square circuit, configured to generate the current term related to the second order temperature, and the current square circuit includes: third to seventh current sources, first to fifth NMOS transistors, the first and second PMOS transistors, and the second to fifth bipolar transistors, wherein,

The third current source is linearly related to temperature, and its correlation coefficient is α ₂ ;

The fourth current source is linearly related to temperature, and its correlation coefficient is α ₃ ;

The fifth current source is independent of temperature;

The collector of the second bipolar transistor is connected to the third current source and the gate of the first NMOS transistor, the emitter is connected to the ground terminal, and the base is connected to the drain of the third NMOS transistor and the gate of the first NMOS transistor. the emitter of the third bipolar transistor;

The collector of the third bipolar transistor is connected to the fourth current source and the gate of the second NMOS transistor, and the base is connected to the base of the fourth bipolar transistor and the first NMOS transistor source of

The collector of the fourth bipolar transistor is connected to the power supply terminal, and the emitter is connected to the fifth current source and the base of the fifth bipolar transistor;

The collector of the fifth bipolar transistor is connected to the drain of the first PMOS transistor, and the emitter is connected to the ground terminal;

The sixth current source is connected to the bases of the third and fourth bipolar transistors, and the source of the first NMOS transistor;

The drain of the first NMOS transistor is connected to the power supply terminal;

The drain of the second NMOS transistor is connected to the power supply terminal, and the source is connected to the gate of the third NMOS transistor and the drain of the fourth NMOS transistor;

The source of the third NMOS transistor is connected to the ground terminal;

The gate of the fourth NMOS transistor is connected to the gate and drain of the fifth NMOS transistor, and the source is connected to the ground terminal;

The drain of the fifth NMOS transistor is connected to the seventh current source, and the source is connected to the ground terminal;

The sources of the first and second PMOS transistors are connected to the power supply terminal, and the gates of the first and second PMOS transistors are connected, wherein, the connection between the second PMOS transistor and the first PMOS transistor The proportionality coefficient is K, and the drain current of the second PMOS transistor is the current item related to the second-order temperature;

Wherein, the temperature-independent bandgap reference voltage is obtained by adjusting the correlation coefficients to be α ₁ , α ₂ , α ₃ , α ₄ , the proportionality coefficient K, and the size of the fifth current source.

In a preferred example, it further includes: a current square circuit, configured to generate the current item related to the second-order temperature, and the current square circuit includes: third to fifth current sources, a first NMOS transistor, a first and the second PMOS transistor, and the second to fifth bipolar transistors, wherein,

The third current source is linearly related to temperature, and its correlation coefficient is α ₂ ;

The fourth current source is independent of temperature;

The collector of the third bipolar transistor is connected to the third current source, the emitter is connected to the collector of the second bipolar transistor, and the base is connected to the base of the fourth bipolar transistor;

The collector of the fourth bipolar transistor is connected to the power supply terminal, and the emitter is connected to the fifth current source and the base of the fifth bipolar transistor;

The collector of the fifth bipolar transistor is connected to the drain of the first PMOS transistor, and the emitter is connected to the ground terminal;

The gate and drain of the first NMOS transistor are connected to a fifth current source, and the source is connected to a ground terminal;

The sources of the first and second PMOS transistors are connected to the power supply terminal, and the gates of the first and second PMOS transistors are connected, wherein, the connection between the second PMOS transistor and the first PMOS transistor The proportionality coefficient is K, and the drain current of the second PMOS transistor is the current item related to the second-order temperature;

Wherein, the temperature-independent bandgap reference voltage is obtained by adjusting the correlation coefficients to be α ₁ , α ₂ , α ₄ , the proportionality coefficient K, and the size of the fourth current source.

In a preferred example, it also includes: a current square circuit for generating the current item related to the second order temperature, and the current square circuit includes: third to seventh current sources, first to eighth NMOS transistors, the first and second PMOS transistors, and the second to fifth bipolar transistors, wherein,

The third current source is linearly related to temperature, and its correlation coefficient is α ₂ ;

The fourth current source is linearly related to temperature, and its correlation coefficient is α ₃ ;

The fifth current source is independent of temperature;

The collector of the second bipolar transistor is connected to the third current source and the gate of the first NMOS transistor, the emitter is connected to the ground terminal, and the base is connected to the drain of the third NMOS transistor and the gate of the first NMOS transistor. the emitter of the third bipolar transistor;

The collector of the third bipolar transistor is connected to the fourth current source and the gate of the second NMOS transistor, and the base is connected to the base of the fourth bipolar transistor and the first NMOS transistor source of

The collector of the fourth bipolar transistor is connected to the fifth power supply terminal and the gate of the sixth NMOS transistor, and the emitter is connected to the drain of the seventh NMOS transistor and the fifth bipolar transistor. the base;

The collector of the fifth bipolar transistor is connected to the drain of the first PMOS transistor, and the emitter is connected to the ground terminal;

The sixth current source is connected to the bases of the third and fourth bipolar transistors, and the source of the first NMOS transistor;

The drain of the first NMOS transistor is connected to the power supply terminal;

The drain of the second NMOS transistor is connected to the power supply terminal, and the source is connected to the gate of the third NMOS transistor and the drain of the fourth NMOS transistor;

The source of the third NMOS transistor is connected to the ground terminal;

The gate of the fourth NMOS transistor is connected to the gate and drain of the fifth NMOS transistor, and the source is connected to the ground terminal;

The source of the fifth NMOS transistor is connected to the sixth current source, and the drain is connected to the ground terminal;

The drain of the sixth NMOS transistor is connected to the power supply terminal, the source is connected to the gate of the seventh NMOS transistor and the drain of the eighth NMOS transistor, and the source of the eighth NMOS transistor is connected to the ground terminal ;

The sources of the first and second PMOS transistors are connected to the power supply terminal, and the gates of the first and second PMOS transistors are connected, wherein, the connection between the second PMOS transistor and the first PMOS transistor The proportionality coefficient is K, and the drain current of the second PMOS transistor is the current item related to the second-order temperature;

Wherein, the temperature-independent bandgap reference voltage is obtained by adjusting the correlation coefficients to be α ₁ , α ₂ , α ₃ , α ₄ , the proportionality coefficient K, and the size of the fifth current source.

In a preferred example, the adder includes: ninth to twelfth NMOS transistors, wherein,

The gate of the ninth NMOS transistor is connected to the second current source and the collector of the first bipolar transistor, and the drain is connected to the first current source and the gate of the tenth NMOS transistor, source one end of the first resistor;

The emitter of the first bipolar transistor is connected to the ground terminal, and the base is connected to the other end of the first resistor and the drain of the twelfth NMOS transistor;

The drain of the tenth NMOS transistor is connected to the power supply terminal, the source is connected to the drain of the eleventh NMOS transistor and the gate of the twelfth NMOS transistor, and the eleventh and twelfth NMOS transistors The source is connected to the ground terminal;

Wherein, the source of the ninth NMOS transistor outputs the temperature-independent bandgap reference voltage.

In a preferred example, it also includes: a current square circuit for generating the current item related to the second order temperature, and the current square circuit includes: third to seventh current sources, first, second, fourth , fifth, sixth and eighth NMOS transistors, first and second PMOS transistors, second to seventh bipolar transistors and second and third resistors, wherein the first NMOS transistor, the second NMOS transistor and the sixth NMOS transistor is an intrinsic threshold transistor, wherein,

The third current source is linearly related to temperature, and its correlation coefficient is α ₂ ;

The fourth current source is linearly related to temperature, and its correlation coefficient is α ₃ ;

The fifth current source is independent of temperature;

The collector of the second bipolar transistor is connected to the third current source and the gate of the first NMOS transistor, the emitter is connected to the ground terminal, and the base is connected to the collector of the sixth bipolar transistor and an emitter of the third bipolar transistor;

The collector of the third bipolar transistor is connected to the fourth current source and the gate of the second NMOS transistor, and the base is connected to the base of the fourth bipolar transistor and the first NMOS transistor source of

The collector of the fourth bipolar transistor is connected to the fifth power supply terminal and the gate of the sixth NMOS transistor, and the emitter is connected to the collector of the seventh bipolar transistor and the fifth bipolar transistor. type transistor base;

The collector of the fifth bipolar transistor is connected to the drain of the first PMOS transistor, and the emitter is connected to the ground terminal;

The emitter of the sixth bipolar transistor is connected to the ground terminal, and the base is connected to the drain of the fourth NMOS transistor and one end of the second resistor;

The emitter of the seventh bipolar transistor is connected to the ground terminal, and the base is connected to the drain of the eighth NMOS transistor and one end of the third resistor;

The sixth current source is connected to the bases of the third and fourth bipolar transistors, and the source of the first NMOS transistor;

The drain of the first NMOS transistor is connected to the power supply terminal;

The drain of the second NMOS transistor is connected to the power supply terminal, and the source is connected to the other end of the second resistor;

The gate of the fourth NMOS transistor is connected to the gate and drain of the fifth NMOS transistor, and the source is connected to the ground terminal;

The source of the fifth NMOS transistor is connected to the sixth current source, and the drain is connected to the ground terminal;

The drain of the sixth NMOS transistor is connected to the power supply terminal, and the source is connected to the other end of the third resistor;

The source of the eighth NMOS transistor is connected to the ground terminal;

The sources of the first and second PMOS transistors are connected to the power supply terminal, and the gates of the first and second PMOS transistors are connected, wherein, the connection between the second PMOS transistor and the first PMOS transistor The proportionality coefficient is K, and the drain current of the second PMOS transistor is the current item related to the second-order temperature;

Wherein, the temperature-independent bandgap reference voltage is obtained by adjusting the correlation coefficients to be α ₁ , α ₂ , α ₃ , α ₄ , the proportionality coefficient K, and the size of the fifth current source.

In a preferred example, the adder includes: ninth to tenth NMOS transistors, an eighth bipolar transistor, an eighth current source and a fourth resistor, wherein the ninth to tenth NMOS transistors are intrinsic threshold transistor, where,

The gate of the ninth NMOS transistor is connected to the second current source and the collector of the first bipolar transistor, and the drain is connected to the first current source and the gate of the tenth NMOS transistor, source one end of the first resistor;

The emitter of the first bipolar transistor is connected to the ground terminal, and the base is connected to the other end of the first resistor and the collector of the eighth bipolar transistor;

The drain of the tenth NMOS transistor is connected to the power supply terminal, the source is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the first current source, the eighth current source and the first current source. bases of eight bipolar transistors, said eighth current source being temperature independent;

Wherein, the source of the ninth NMOS transistor outputs the temperature-independent bandgap reference voltage.

In a preferred example, the adder includes: an amplifier and a ninth NMOS transistor, wherein the ninth NMOS transistor is an intrinsic threshold transistor, wherein,

The non-inverting input terminal of the amplifier is connected to the second current source, the collector and the base of the first bipolar transistor, the inverting input terminal is connected to one end of the first resistor of the first current source, and the The emitter of the first bipolar transistor is connected to the ground terminal, and the output terminal of the amplifier is connected to the gate of the ninth NMOS transistor;

The drain of the ninth NMOS transistor is connected to the power supply terminal, and the source is connected to the other end of the first resistor;

Wherein, the source of the ninth NMOS transistor outputs the temperature-independent bandgap reference voltage and is connected to a load current.

This application can use the current source I _C =I ₀ +αT+βT ² with high-order terms to obtain the base-emitter voltage V _BE of the BJT with high-order temperature dependence, so as to compensate for the positive temperature dependence of the PLAT current I _ptat =αT characteristics, resulting in a temperature-insensitive bandgap reference voltage.

A large number of technical features are recorded in this specification, which are distributed in various technical solutions. If it is necessary to list all possible combinations of technical features (ie, technical solutions) of this application, the specification will be too lengthy. In order to avoid this problem, the technical features disclosed in the above summary of the invention in this specification, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings can be freely combined with each other to form Various new technical solutions (these technical solutions should be deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, feature A+B+C is disclosed in one example, and feature A+B+D+E is disclosed in another example, and features C and D are equivalent technical means that play the same role. It can be used as soon as it is used, and it is impossible to use it at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as recorded because it is technically infeasible, and A+B+ The C+E scheme should be considered as documented.

Description of drawings

FIG. 1 is a schematic diagram of the generation of a bandgap reference voltage in the prior art.

FIG. 2 is a graph showing the relationship between the bandgap reference voltage and temperature generated by referring to the method in FIG. 1 .

FIG. 3 is a schematic diagram of generating a bandgap reference voltage with high-order temperature compensation in an embodiment of the present application.

FIG. 4 is a schematic diagram of a bandgap reference voltage circuit with high-order temperature compensation in an embodiment of the present application.

FIG. 5 is a temperature curve of a bandgap reference voltage in an embodiment of the present application.

FIG. 6 is a schematic diagram of a bandgap reference voltage circuit with high-order temperature compensation in another embodiment of the present application.

FIG. 7 is a schematic diagram of a bandgap reference voltage circuit with high-order temperature compensation in another embodiment of the present application.

FIG. 8 is a schematic diagram of a bandgap reference voltage circuit with high-order temperature compensation in another embodiment of the present application.

FIG. 9 is a schematic diagram of a bandgap reference voltage circuit with high-order temperature compensation in another embodiment of the present application.

FIG. 10 is a circuit for generating a current I _ptat linearly related to temperature and a current I _const independent of temperature in an embodiment of the present application.

Detailed ways

In the following description, many technical details are proposed in order to enable readers to better understand the application. However, those skilled in the art can understand that the technical solutions claimed in this application can be realized even without these technical details and various changes and modifications based on the following implementation modes.

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manner of the present application will be further described in detail below in conjunction with the accompanying drawings.

An embodiment of the present application provides a bandgap reference voltage generation circuit with high-order temperature compensation. FIG. 3 is a schematic diagram of the generation of a bandgap reference voltage with high-order temperature compensation in an embodiment. The generating circuit of includes a first current source I _plat , a second current source I _C and an adder 11 . The first current source I _plat is linearly related to temperature, I _ptat =αT, and the correlation coefficient of the current item linearly related to temperature is α. The second current source _IC includes a current term that is second-order dependent on temperature with a correlation coefficient β. The second current source I _C also includes a current item linearly related to temperature and a current item independent of temperature, the correlation coefficient of the current item linearly related to temperature is α′, and the current independent of temperature is I ₀ , _IC = I ₀ +α′T+βT ² . The second-order temperature-dependent current term, the temperature-linearly-dependent current term, and the temperature-independent current term are connected in parallel with each other, so that the temperature-linearly-dependent current term, the temperature-independent current term, and the temperature-independent current term The terms add up to form the second current source I _C . The bandgap reference voltage generation circuit also includes a current square circuit for generating a current item related to the second order temperature. The current square circuit will be described in detail below.

The first current source I plat generates the first voltage I _{ptat R 1} through the first resistor R ₁ , and the second current source _IC generates the second voltage V _BE through the first bipolar transistor Q ₁ . The adder 11 generates a temperature-independent bandgap reference voltage V _BG according to the first voltage and the second voltage V _BE . By adjusting the correlation coefficients in the first current source I _plat and the second current source I _C , the bandgap reference voltage V _BG is independent of temperature.

Embodiment one

FIG. 4 shows a schematic diagram of a generation circuit of a bandgap reference voltage in an embodiment. The generation circuit of the bandgap reference voltage includes a first current source I _plat1 , a second current source I _C1 , a current square circuit 41 and an adder 42 . The linear correlation coefficient between the first current source I _plat1 and the temperature is α ₁ , and I _ptat1 =α ₁ T. The second current source I _C1 includes a second-order temperature related current item I _sqT , a temperature linearly related current item I _plat4 and a temperature-independent current item I _const2 , where I _C1 =I ₀ +α′T+βT ² =I _const2 +I _ptat4 +I _sqT , I _ptat4 =α ₄ T. I _sqT = βT ² , I _sqT is generated by the current square circuit 41 , and parameters in the current square circuit can be adjusted to adjust the correlation coefficient β. The second current source I _C1 forms a second voltage V _BE1 through the first bipolar transistor Q ₁ .

The current square circuit 41 includes a third current source I _plat2 , a fourth current source I _plat3 , a fifth current source I _const1 , a sixth current source I ₆ , a seventh current source I ₇ , first to fifth NMOS transistors NM ₁ to NM ₅ , first and second PMOS transistors PM ₁ -PM ₂ , and second to fifth bipolar transistors Q ₂ -Q ₅ .

The third current source I _plat2 is linearly related to temperature, and its correlation coefficient is α ₂ . The fourth current source I _plat3 is linearly related to temperature, and its correlation coefficient is α ₃ . The fifth current source I _const1 is independent of temperature. It should be noted that the correlation coefficient of α ₂ and the correlation coefficient of α ₃ have different values.

The collector of the second bipolar transistor _Q2 is connected to the gate of the third current source I _plat2 and the _first NMOS transistor NM1, the emitter is connected to the ground terminal, and the base is connected to the drain of the _third NMOS transistor NM3 and the third Emitter of bipolar transistor _Q3 .

The collector of the third bipolar transistor _Q3 is connected to the gate of the _fourth current source I _plat3 and the _second NMOS transistor NM2, and the base is connected to the base of the fourth bipolar transistor Q4 and the _first NMOS transistor NM1 source.

The collector of the fourth bipolar transistor _Q4 is connected to the power supply terminal, and the emitter is connected to the fifth current source I _const1 and the base of the _fifth bipolar transistor Q5.

The collector of the fifth bipolar transistor _Q5 is connected to the drain of the _first PMOS transistor NM1, and the emitter is connected to the ground terminal.

The _sixth current source I6 is connected to the bases of the third bipolar transistor _Q3 and the _fourth bipolar transistor Q4, and the source of the _first NMOS transistor NM1.

The drain of the _first NMOS transistor NM1 is connected to the power terminal. The drain of the _second NMOS transistor NM2 is connected to the power supply terminal, and the source is connected to the gate of the _third NMOS transistor NM3 and the drain of the _fourth NMOS transistor NM4. The source of the _third NMOS transistor NM3 is connected to the ground terminal. The gate of the _fourth NMOS transistor NM4 is connected to the gate and drain of the _fifth NMOS transistor NM5, and the source is connected to the ground terminal. The drain of the fifth NMOS transistor NM ₅ is connected to the seventh current source I ₇ , and the source is connected to the ground terminal.

The sources of the first PMOS transistor PM ₁ and the second PMOS transistor PM ₂ are connected to the power terminal, and the gates of the first PMOS transistor PM ₁ and the second PMOS transistor PM ₂ are connected, wherein the second PMOS transistor PM ₂ and the first PMOS _The ratio coefficient between the transistors PM1 is K, that is, the ratio of the width to length ratio between the _second PMOS transistor PM2 and the _first PMOS transistor PM1 is K. The drain current of the second PMOS transistor PM ₂ is the second-order temperature dependent current term I _sqT in the second current source.

Continuing to refer to Fig. 4, there are in the current square circuit 41:

V _BE2 +V _BE3 =V _BE4 +V _BE5

I _C2 · I _C3 = I _C4 · V _C5

Neglecting the base currents of bipolar transistors Q ₂ ~ Q ₅ , there are:

I _C2 =I _ptat2 =α ₂ T

I _C3 =I _ptat3 =α ₃ T

I _C4 = I _const1

According to the proportional relationship between the _first PMOS transistor PM1 and the _second PMOS transistor PM2, the current term related to the second order temperature is obtained:

Therefore, the second current source is:

The base-emitter voltage (ie, the second voltage) of the _first bipolar transistor Q1 is:

Continuing to refer to FIG. 4 , the adder 42 includes ninth to twelfth NMOS transistors NM ₉ -NM ₁₂ , and the gate of the ninth NMOS transistor NM ₉ is connected to the second current source I _C1 and the first bipolar transistor Q ₁ The collector is connected, the drain is connected to the first current source I _plat1 and the gate of the tenth NMOS transistor NM ₁₀ , and the source is one end of the first resistor R ₁ . The emitter of the _first bipolar transistor Q1 is connected to the ground terminal, and the base is connected to the other end of the _first resistor R1 and the drain of the _twelfth NMOS transistor NM12. The drain of the _tenth NMOS transistor NM10 is connected to the power supply terminal, the source is connected to the drain of the _eleventh NMOS transistor NM11 and the gate of the _twelfth NMOS transistor NM12, and the _eleventh NMOS transistor NM11 and the twelfth NMOS The source of the transistor _NM12 is connected to the ground terminal, and the gate of the first NMOS transistor NM11 is connected to the gates of the _fourth NMOS transistor _NM4 and the _fifth NMOS transistor NM5. Wherein, the source of the ninth NMOS transistor NM ₉ outputs a temperature-independent bandgap reference voltage V _BG .

The first current source I _plat1 forms a first voltage I _plat1 R _{1 through the first resistor R 1 .} Neglecting the base current, adder 11 superimposes the first voltage I _plat1 R ₁ with the high-order temperature compensated V _BE1 , and the output voltage can be expressed as:

V _BG =V _BE1 +I _ptat1 R ₁ =V _BE1 +α ₁ T

It can be seen from the above formula that the temperature-independent bandgap reference voltage V _BG is obtained by adjusting the correlation coefficients α ₁ , α ₂ , α ₃ , α ₄ , the proportionality coefficient K, and the size of the fifth current source I _const1 .

FIG. 5 is a temperature curve of a bandgap reference voltage in an embodiment of the present application. It can be seen from the figure that the variation of the bandgap reference voltage V _BG can be neglected within the temperature range from -40°C to 150°C.

Embodiment two

In this embodiment, the current square circuit 61 includes a third current source I _plat2 , a fourth current source I _const1 , a fifth current source I ₅ , a first NMOS transistor NM ₁ , and first and second PMOS transistors PM ₁ to PM ₂ , and the second to fifth bipolar transistors Q ₂ ˜Q ₅ .

The third current source I _plat2 is linearly related to temperature, and its correlation coefficient is α ₂ . The fourth current source I _const1 is independent of temperature.

The collector of the third bipolar transistor Q ₃ is connected to the third current source I _plat2 , the emitter is connected to the collector of the second bipolar transistor Q ₂ , and the base is connected to the base of the fourth bipolar transistor Q ₄ . The collector of the fourth bipolar transistor _Q4 is connected to the power supply terminal, and the emitter is connected to the _fifth current source I5 and the base of the fifth bipolar transistor _Q5 . The collector of the fifth bipolar transistor _Q5 is connected to the drain of the _first PMOS transistor PM1, and the emitter is connected to the ground terminal. The gate and drain of the first NMOS transistor NM ₁ are connected to the fifth current source I ₅ , and the source is connected to the ground terminal.

The sources of the first PMOS transistor PM ₁ and the second PMOS transistor PM ₂ are connected to the power terminal, and the gates of the first PMOS transistor PM ₁ and the second PMOS transistor PM ₂ are connected, wherein the second PMOS transistor PM ₂ and the first PMOS _The ratio coefficient between the transistors PM1 is K, that is, the ratio of the width to length ratio between the _second PMOS transistor PM2 and the _first PMOS transistor PM1 is K. The drain current of the second PMOS transistor PM ₂ is the second-order temperature dependent current term I _sqT in the second current source.

The bandgap reference voltage generation circuit in the present embodiment is basically the same as that of Embodiment 1, and its main difference is that: in the current square circuit of Fig. 4, the correlation coefficient is α ₂ and the correlation coefficient is α ₃ values are not the same, and the present embodiment Make the correlation coefficient α ₂ and the correlation coefficient α ₃ take the same value, that is, the third current source I _plat2 and the fourth current source I _plat3 are equal, then the current square circuit in Figure 4 can be simplified as shown in Figure 6 The current square circuit 61.

It can be seen from the above description that the second current source is:

The bandgap reference voltage V _BG can be obtained by superimposing the V _BE1 of the high-order temperature compensation and the first voltage I _plat1 R ₁ , as shown in the following formula:

Wherein, the temperature-independent bandgap reference voltage V _BG is obtained by adjusting the correlation coefficients α ₁ , α ₂ , α ₄ , the proportionality coefficient K, and the magnitude of the fourth current source I _const1 .

Embodiment Three

In this embodiment, the current square circuit 71 includes a third current source I _plat2 , a fourth current source I _plat3 , a fifth current source I _const1 , a sixth current source I ₆ , a seventh current source I ₇ , first to eighth NMOS transistors NM ₁ -NM ₈ , first and second PMOS transistors PM ₁ -PM ₂ , and second to fifth bipolar transistors Q ₂ -Q ₅ . The collector of the fourth bipolar transistor _Q4 is connected to the fifth power supply terminal I _const1 and the gate of the _sixth NMOS transistor NM6, and the emitter is connected to the drain of the _seventh NMOS transistor NM7 and the fifth bipolar transistor _Q5 base. The drain of the _sixth NMOS transistor NM6 is connected to the power supply terminal, the source is connected to the gate of the _seventh NMOS transistor NM7 and the drain of the _eighth NMOS transistor NM8, and the source of the _eighth NMOS transistor NM8 is connected to the ground terminal.

When the temperature is high, the base-emitter voltage V _BE5 of the _fifth bipolar transistor Q5 in the current squaring circuit of FIG. 4 is small, so that the fifth current source I _const1 enters the linear region, which is difficult to control accurately. In order to solve this problem, in this embodiment, the fifth current source I _const1 is set at the collector of the fourth bipolar transistor Q ₄ , and sixth to eighth NMOS transistors NM ₆ -NM ₈ are added to form a feedback loop, Refer to the dotted box 72 in FIG. 7 . It should be noted that, except for the feedback loop part, other parts of the current square circuit in the third embodiment are basically the same as those in the first embodiment, and will not be repeated here.

Embodiment Four

The bandgap voltage reference in this embodiment is suitable for low voltage applications. Referring to FIG. 8 , the generation circuit of the bandgap reference voltage in this embodiment includes a first current source I _plat1 , a second current source I _C1 , a current square circuit 81 and an adder 82 .

The current square circuit 82 includes a third current source I _plat2 , a fourth current source I _plat3 , a fifth current source I _const1 , a sixth current source I ₆ , a seventh current source I ₇ , a first NMOS transistor NM ₁ , a second NMOS Transistor NM ₂ , fourth NMOS transistor NM ₄ , fifth NMOS transistor NM ₅ , sixth NMOS transistor NM ₆ , eighth NMOS transistor NM ₆ , first and second PMOS transistors PM ₁ to PM ₂ , second to second Seven bipolar transistors Q ₂ -Q ₇ , and second and third resistors R ₂ -R ₃ .

The third current source I _plat2 is linearly related to temperature, and its correlation coefficient is α ₂ . The fourth current source I _plat3 is linearly related to temperature, and its correlation coefficient is α ₃ . The fifth current source I _const1 is independent of temperature.

The collector of the second bipolar transistor _Q2 is connected to the gate of the third current source I _plat2 and the _first NMOS transistor NM1, the emitter is connected to the ground terminal, and the base is connected to the collector of the _sixth bipolar transistor Q6 and The emitter of the third bipolar transistor _Q3 .

The collector of the third bipolar transistor _Q3 is connected to the gate of the _fourth current source I _plat3 and the _second NMOS transistor NM2, and the base is connected to the base of the fourth bipolar transistor Q4 and the _first NMOS transistor NM1 source.

The collector of the fourth bipolar transistor _Q4 is connected to the power supply terminal, and the emitter is connected to the fifth current source I _const1 and the base of the _fifth bipolar transistor Q5.

The collector of the fifth bipolar transistor _Q5 is connected to the drain of the _first PMOS transistor NM1, and the emitter is connected to the ground terminal.

The emitter of the _sixth bipolar transistor Q6 is connected to the ground terminal, and the base is connected to the drain of the _fourth NMOS transistor NM4 and one end of the _second resistor R2.

The emitter of the _seventh bipolar transistor Q7 is connected to the ground terminal, and the base is connected to the drain of the _eighth NMOS transistor NM8 and one end of the third resistor _R3 .

The _sixth current source I6 is connected to the bases of the third bipolar transistor _Q3 and the _fourth bipolar transistor Q4, and the source of the _first NMOS transistor NM1.

The drain of the _first NMOS transistor NM1 is connected to the power terminal. The drain of the _second NMOS transistor NM2 is connected to the power supply terminal, and the source is connected to the other end of the _second resistor R2. The gate of the _fourth NMOS transistor NM4 is connected to the gate and drain of the _fifth NMOS transistor NM5, and the source is connected to the ground terminal. The drain of the fifth NMOS transistor NM ₅ is connected to the seventh current source I ₇ , and the source is connected to the ground terminal. The drain of the _sixth NMOS transistor NM6 is connected to the power supply terminal, the source is connected to the other end of the third resistor _R3 , and the source of the _eighth NMOS transistor NM8 is connected to the ground terminal.

The sources of the first PMOS transistor PM ₁ and the second PMOS transistor PM ₂ are connected to the power terminal, and the gates of the first PMOS transistor PM ₁ and the second PMOS transistor PM ₂ are connected, wherein the second PMOS transistor PM ₂ and the first PMOS _The ratio coefficient between the transistors PM1 is K, that is, the ratio of the width to length ratio between the _second PMOS transistor PM2 and the _first PMOS transistor PM1 is K. The drain current of the second PMOS transistor PM ₂ is the second-order temperature dependent current term I _sqT in the second current source.

_In this embodiment, the current square circuit ₈₁ is _basically the same as the current square circuit in FIG. VT) transistors, the _third NMOS transistor NM3 is replaced by a sixth bipolar transistor _Q6 , and the _seventh NMOS transistor NM7 is replaced by a _seventh bipolar transistor Q7. In addition, the current square circuit 81 further includes a second resistor R ₂ and a third resistor R ₃ .

In this embodiment, the adder 81 includes: ninth to tenth NMOS transistors NM ₉ ˜NM ₁₀ , an eighth bipolar transistor Q ₈ , an eighth current source I _const3 and a fourth resistor R ₄ . Wherein, the ninth to tenth NMOS transistors NM ₉ -NM ₁₀ are natural threshold (natural VT) transistors. The eighth current source I _const3 is independent of temperature.

The gate of the _ninth NMOS transistor NM9 is connected to the second current source I _C1 and the collector of the _first bipolar transistor Q1, the drain is connected to the first current source I _plat1 and the gate of the _tenth NMOS transistor NM10, and the source pole to _one end of the first resistor R1. The emitter of the _first bipolar transistor Q1 is connected to the ground terminal, and the base is connected to the other end of the _first resistor R1 and the collector of the _eighth bipolar transistor Q8. The drain of the _tenth NMOS transistor NM10 is connected to the power supply terminal, the source is connected to one end of the _fourth resistor R4, and the other end of the _fourth resistor R4 is connected to the first current source I _plat1 , the eighth current source I _const3 and the eighth dual base of polar transistor _Q8 . The source of the ninth NMOS transistor NM ₉ outputs a temperature-independent bandgap reference voltage V _BG .

In this embodiment, due to the use of intrinsic threshold transistors, the following relationship can be obtained:

V _P ≈ V _Q

V _S ≈ V _BG

V _Q ＝V _BE8 +(I _ptat5 +I _const3 )R ₄

＝V _BE8 +I _ptat5 R ₄ +I _const3 R ₄

≈V _BG +I _const3 R ₄

Therefore, by adjusting the eighth current source I _const3 , V _P can be made insensitive to temperature to obtain a fixed Vds of the ninth NMOS transistor NM ₉ , which is suitable for low voltage (eg, VCC<1.8V) applications.

Similarly, in this embodiment, _VR and _VO can be made insensitive to temperature, so as to obtain a fixed Vds of the second NMOS transistor NM ₂ and the sixth NMOS transistor NM ₆ , which is suitable for low voltage applications.

Embodiment five

The adder 92 in this embodiment includes an amplifier 93 and a ninth NMOS transistor NM ₉ . The _ninth NMOS transistor NM9 is an intrinsic threshold transistor. The bandgap reference voltage in this embodiment can drive the load current.

The non-inverting input terminal of the amplifier 93 is connected to the second current source I _C1 , the collector and the base of the first bipolar transistor Q ₁ , the inverting input terminal is connected to one end of the first resistor R ₁ of the first current source I _plat1 , and the second The emitter of _a bipolar transistor Q1 is connected to the ground terminal, and the output terminal of the amplifier 93 is connected to the gate of the _ninth NMOS transistor NM9. The drain of the _ninth NMOS transistor NM9 is connected to the power supply terminal, and the source is connected to the other end of the _first resistor R1. The source of the ninth NMOS transistor NM ₉ outputs a temperature-independent bandgap reference voltage V _BG , and is connected to the load current I _load .

In an embodiment of the present application, a current source or current term I _plat (for example, I _plat1 , I _plat2 , I _platt3 , I _platt4 and I _plat5 ) that is linearly dependent on temperature and a current source or current term that is independent of temperature (for example, I The generating circuits of _const1 , I _const2 and I _const3 ) are shown in FIG. 10 . The generating circuit includes third to eighth PMOS transistors MP ₃ to MP ₈ , a first amplifier 101, a second amplifier 102, fifth to seventh resistors R ₅ to R ₇ , first to third diodes D ₁ to D ₃ and the thirteenth NMOS transistor MN ₁₃ . The gates of the third to sixth PMOS transistors MP ₃ to MP ₆ are connected and connected to the output terminal of the second amplifier 102, the non-inverting input terminal of the second amplifier 102 is connected to one end of the _fifth resistor R5, and the _fifth resistor R5 The other end is connected to the anode of the _first diode D1, and the inverting input end of the second amplifier 102 is connected to the anode of the _second diode D2. The drain of the _fifth PMOS transistor MP5 is connected to the non-inverting input terminal of the first amplifier 101 and one end of the _sixth resistor R6, and the other end of the _sixth resistor R6 is connected to the anode of the third diode _D3 . The first amplifier 101 The inverting input end of the first amplifier 101 is connected to the source of the _thirteenth NMOS transistor MN13 and one end of the seventh resistor _R7 , the other end of the seventh resistor _R7 is connected to the ground, and the output end of the first amplifier 101 is connected to the thirteenth NMOS transistor Gate of NM ₁₃ . The drain of the _thirteenth NMOS transistor NM13, the drain and gate of the _seventh PMOS transistor MP7, and the gate of the _eighth PMOS transistor MP8 are connected. The drain current of the sixth PMOS transistor MP ₆ is a current source or term I _plat linearly dependent on temperature, and the drain current of the eighth PMOS transistor MP ₈ is a current source or current term I _const that is independent of temperature.

It should be noted that in the application documents of this patent, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these No such actual relationship or order exists between entities or operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element. In the application documents of this patent, if it is mentioned that an action is performed according to a certain element, it means that the action is performed based on at least the element, which includes two situations: the action is only performed based on the element, and the action is performed based on the element and Other elements perform the behavior. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 types, and 2 or more, 2 or more times, or 2 or more types.

All documents mentioned in this specification are considered to be included in the disclosure content of this specification as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above descriptions are only preferred embodiments of this specification, and are not intended to limit the protection scope of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included in the protection scope of one or more embodiments of this specification.

Claims (9)

1. A bandgap reference voltage generation circuit with high-order temperature compensation, characterized in that it includes:

   a first current source, the first current source is linearly related to temperature, and its correlation coefficient is α ₁ , and the first current source generates a first voltage through a first resistance;

   a second current source comprising a second-order temperature dependent current term with a correlation coefficient β, the second current source generating a second voltage through the first bipolar transistor; and

   An adder that generates a temperature-independent bandgap reference voltage based on the first voltage and the second voltage.
2. The bandgap reference voltage generating circuit according to claim 1, wherein the second current source further includes a current item linearly related to temperature and a current item independent of temperature, and the current item linearly related to temperature is The correlation coefficient is α ₄ , the current item linearly related to temperature and the current item independent of temperature are respectively connected in parallel with the current item related to the second order related to temperature, and the current item linearly related to temperature is independent of temperature The current item and the current item related to the second order temperature are superimposed to form the second current source.
3. The bandgap reference voltage generating circuit according to claim 2, further comprising: a current square circuit for generating the current item related to the second-order temperature, and the current square circuit includes: the third to the second Seven current sources, first to fifth NMOS transistors, first and second PMOS transistors, and second to fifth bipolar transistors, wherein,

   The third current source is linearly related to temperature, and its correlation coefficient is α ₂ ;

   The fourth current source is linearly related to temperature, and its correlation coefficient is α ₃ ;

   The fifth current source is independent of temperature;

   The collector of the second bipolar transistor is connected to the third current source and the gate of the first NMOS transistor, the emitter is connected to the ground terminal, and the base is connected to the drain of the third NMOS transistor and the gate of the first NMOS transistor. the emitter of the third bipolar transistor;

   The collector of the third bipolar transistor is connected to the fourth current source and the gate of the second NMOS transistor, and the base is connected to the base of the fourth bipolar transistor and the first NMOS transistor source of

   The collector of the fourth bipolar transistor is connected to the power supply terminal, and the emitter is connected to the fifth current source and the base of the fifth bipolar transistor;

   The collector of the fifth bipolar transistor is connected to the drain of the first PMOS transistor, and the emitter is connected to the ground terminal;

   The sixth current source is connected to the bases of the third and fourth bipolar transistors, and the source of the first NMOS transistor;

   The drain of the first NMOS transistor is connected to the power supply terminal;

   The drain of the second NMOS transistor is connected to the power supply terminal, and the source is connected to the gate of the third NMOS transistor and the drain of the fourth NMOS transistor;

   The source of the third NMOS transistor is connected to the ground terminal;

   The gate of the fourth NMOS transistor is connected to the gate and drain of the fifth NMOS transistor, and the source is connected to the ground terminal;

   The drain of the fifth NMOS transistor is connected to the seventh current source, and the source is connected to the ground terminal;

   The sources of the first and second PMOS transistors are connected to the power supply terminal, and the gates of the first and second PMOS transistors are connected, wherein, the connection between the second PMOS transistor and the first PMOS transistor The proportionality coefficient is K, and the drain current of the second PMOS transistor is the current item related to the second-order temperature;

   Wherein, the temperature-independent bandgap reference voltage is obtained by adjusting the correlation coefficients to be α ₁ , α ₂ , α ₃ , α ₄ , the proportionality coefficient K, and the size of the fifth current source.
4. The bandgap reference voltage generating circuit according to claim 2, further comprising: a current square circuit for generating the current item related to the second-order temperature, and the current square circuit includes: the third to the second five current sources, a first NMOS transistor, first and second PMOS transistors, and second to fifth bipolar transistors, wherein,

   The third current source is linearly related to temperature, and its correlation coefficient is α ₂ ;

   The fourth current source is independent of temperature;

   The collector of the third bipolar transistor is connected to the third current source, the emitter is connected to the collector of the second bipolar transistor, and the base is connected to the base of the fourth bipolar transistor;

   The collector of the fourth bipolar transistor is connected to the power supply terminal, and the emitter is connected to the fifth current source and the base of the fifth bipolar transistor;

   The collector of the fifth bipolar transistor is connected to the drain of the first PMOS transistor, and the emitter is connected to the ground terminal;

   The gate and drain of the first NMOS transistor are connected to a fifth current source, and the source is connected to a ground terminal;

   The sources of the first and second PMOS transistors are connected to the power supply terminal, and the gates of the first and second PMOS transistors are connected, wherein, the connection between the second PMOS transistor and the first PMOS transistor The proportionality coefficient is K, and the drain current of the second PMOS transistor is the current item related to the second-order temperature;

   Wherein, the temperature-independent bandgap reference voltage is obtained by adjusting the correlation coefficients to be α ₁ , α ₂ , α ₄ , the proportionality coefficient K, and the size of the fourth current source.
5. The bandgap reference voltage generating circuit according to claim 2, further comprising: a current square circuit for generating the current item related to the second-order temperature, and the current square circuit includes: the third to the second Seven current sources, first to eighth NMOS transistors, first and second PMOS transistors, and second to fifth bipolar transistors, wherein,

   The third current source is linearly related to temperature, and its correlation coefficient is α ₂ ;

   The fourth current source is linearly related to temperature, and its correlation coefficient is α ₃ ;

   The fifth current source is independent of temperature;

   The collector of the second bipolar transistor is connected to the third current source and the gate of the first NMOS transistor, the emitter is connected to the ground terminal, and the base is connected to the drain of the third NMOS transistor and the gate of the first NMOS transistor. the emitter of the third bipolar transistor;

   The collector of the third bipolar transistor is connected to the fourth current source and the gate of the second NMOS transistor, and the base is connected to the base of the fourth bipolar transistor and the first NMOS transistor source of

   The collector of the fourth bipolar transistor is connected to the fifth power supply terminal and the gate of the sixth NMOS transistor, and the emitter is connected to the drain of the seventh NMOS transistor and the fifth bipolar transistor. the base;

   The collector of the fifth bipolar transistor is connected to the drain of the first PMOS transistor, and the emitter is connected to the ground terminal;

   The sixth current source is connected to the bases of the third and fourth bipolar transistors, and the source of the first NMOS transistor;

   The drain of the first NMOS transistor is connected to the power supply terminal;

   The drain of the second NMOS transistor is connected to the power supply terminal, and the source is connected to the gate of the third NMOS transistor and the drain of the fourth NMOS transistor;

   The source of the third NMOS transistor is connected to the ground terminal;

   The gate of the fourth NMOS transistor is connected to the gate and drain of the fifth NMOS transistor, and the source is connected to the ground terminal;

   The source of the fifth NMOS transistor is connected to the sixth current source, and the drain is connected to the ground terminal;

   The drain of the sixth NMOS transistor is connected to the power supply terminal, the source is connected to the gate of the seventh NMOS transistor and the drain of the eighth NMOS transistor, and the source of the eighth NMOS transistor is connected to the ground terminal ;

   The sources of the first and second PMOS transistors are connected to the power supply terminal, and the gates of the first and second PMOS transistors are connected, wherein, the connection between the second PMOS transistor and the first PMOS transistor The proportionality coefficient is K, and the drain current of the second PMOS transistor is the current item related to the second-order temperature;

   Wherein, the temperature-independent bandgap reference voltage is obtained by adjusting the correlation coefficients to be α ₁ , α ₂ , α ₃ , α ₄ , the proportionality coefficient K, and the size of the fifth current source.
6. The bandgap reference voltage generating circuit according to any one of claims 2 to 5, wherein the adder comprises: ninth to twelfth NMOS transistors, wherein,

   The gate of the ninth NMOS transistor is connected to the second current source and the collector of the first bipolar transistor, and the drain is connected to the first current source and the gate of the tenth NMOS transistor, source one end of the first resistor;

   The emitter of the first bipolar transistor is connected to the ground terminal, and the base is connected to the other end of the first resistor and the drain of the twelfth NMOS transistor;

   The drain of the tenth NMOS transistor is connected to the power supply terminal, the source is connected to the drain of the eleventh NMOS transistor and the gate of the twelfth NMOS transistor, and the eleventh and twelfth NMOS transistors The source is connected to the ground terminal;

   Wherein, the source of the ninth NMOS transistor outputs the temperature-independent bandgap reference voltage.
7. The bandgap reference voltage generating circuit according to claim 2, further comprising: a current square circuit for generating the current item related to the second-order temperature, and the current square circuit includes: the third to the second seven current sources, first, second, fourth, fifth, sixth and eighth NMOS transistors, first and second PMOS transistors, second to seventh bipolar transistors and second and third resistors, wherein , the first NMOS transistor, the second NMOS transistor and the sixth NMOS transistor are intrinsic threshold transistors, wherein,

   The third current source is linearly related to temperature, and its correlation coefficient is α ₂ ;

   The fourth current source is linearly related to temperature, and its correlation coefficient is α ₃ ;

   The fifth current source is independent of temperature;

   The collector of the second bipolar transistor is connected to the third current source and the gate of the first NMOS transistor, the emitter is connected to the ground terminal, and the base is connected to the collector of the sixth bipolar transistor and an emitter of the third bipolar transistor;

   The collector of the third bipolar transistor is connected to the fourth current source and the gate of the second NMOS transistor, and the base is connected to the base of the fourth bipolar transistor and the first NMOS transistor source of

   The collector of the fourth bipolar transistor is connected to the fifth power supply terminal and the gate of the sixth NMOS transistor, and the emitter is connected to the collector of the seventh bipolar transistor and the fifth bipolar transistor. type transistor base;

   The collector of the fifth bipolar transistor is connected to the drain of the first PMOS transistor, and the emitter is connected to the ground terminal;

   The emitter of the sixth bipolar transistor is connected to the ground terminal, and the base is connected to the drain of the fourth NMOS transistor and one end of the second resistor;

   The emitter of the seventh bipolar transistor is connected to the ground terminal, and the base is connected to the drain of the eighth NMOS transistor and one end of the third resistor;

   The sixth current source is connected to the bases of the third and fourth bipolar transistors, and the source of the first NMOS transistor;

   The drain of the first NMOS transistor is connected to the power supply terminal;

   The drain of the second NMOS transistor is connected to the power supply terminal, and the source is connected to the other end of the second resistor;

   The gate of the fourth NMOS transistor is connected to the gate and drain of the fifth NMOS transistor, and the source is connected to the ground terminal;

   The source of the fifth NMOS transistor is connected to the sixth current source, and the drain is connected to the ground terminal;

   The drain of the sixth NMOS transistor is connected to the power supply terminal, and the source is connected to the other end of the third resistor;

   The source of the eighth NMOS transistor is connected to the ground terminal;

   The sources of the first and second PMOS transistors are connected to the power supply terminal, and the gates of the first and second PMOS transistors are connected, wherein, the connection between the second PMOS transistor and the first PMOS transistor The proportionality coefficient is K, and the drain current of the second PMOS transistor is the current item related to the second-order temperature;

   Wherein, the temperature-independent bandgap reference voltage is obtained by adjusting the correlation coefficients to be α ₁ , α ₂ , α ₃ , α ₄ , the proportionality coefficient K, and the size of the fifth current source.
8. The bandgap reference voltage generation circuit according to claim 7, wherein the adder comprises: ninth to tenth NMOS transistors, an eighth bipolar transistor, an eighth current source and a fourth resistor, wherein, The ninth to tenth NMOS transistors are intrinsic threshold transistors, wherein,

   The gate of the ninth NMOS transistor is connected to the second current source and the collector of the first bipolar transistor, and the drain is connected to the first current source and the gate of the tenth NMOS transistor, source one end of the first resistor;

   The emitter of the first bipolar transistor is connected to the ground terminal, and the base is connected to the other end of the first resistor and the collector of the eighth bipolar transistor;

   The drain of the tenth NMOS transistor is connected to the power supply terminal, the source is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the first current source, the eighth current source and the first current source. bases of eight bipolar transistors, said eighth current source being temperature independent;

   Wherein, the source of the ninth NMOS transistor outputs the temperature-independent bandgap reference voltage.
9. The bandgap reference voltage generation circuit according to claim 7, wherein the adder comprises: an amplifier and a ninth NMOS transistor, wherein the ninth NMOS transistor is an intrinsic threshold transistor, wherein,

   The non-inverting input terminal of the amplifier is connected to the second current source, the collector and the base of the first bipolar transistor, the inverting input terminal is connected to one end of the first resistor of the first current source, and the The emitter of the first bipolar transistor is connected to the ground terminal, and the output terminal of the amplifier is connected to the gate of the ninth NMOS transistor;

   The drain of the ninth NMOS transistor is connected to the power supply terminal, and the source is connected to the other end of the first resistor;

   Wherein, the source of the ninth NMOS transistor outputs the temperature-independent bandgap reference voltage and is connected to a load current.

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