CN115657781A - Band-gap reference source circuit of self-buffering loop control technology - Google Patents
Band-gap reference source circuit of self-buffering loop control technology Download PDFInfo
- Publication number
- CN115657781A CN115657781A CN202211381675.6A CN202211381675A CN115657781A CN 115657781 A CN115657781 A CN 115657781A CN 202211381675 A CN202211381675 A CN 202211381675A CN 115657781 A CN115657781 A CN 115657781A
- Authority
- CN
- China
- Prior art keywords
- resistor
- transistor
- circuit
- npn
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Control Of Electrical Variables (AREA)
Abstract
The invention discloses a band-gap reference source circuit of a self-buffering loop control technology, which comprises a starting circuit, a biasing circuit and a band-gap reference core circuit. The band-gap reference source circuit utilizes related circuits such as a PNP triode Q5 and a PNP triode Q6 to generate positive temperature coefficient voltage and weight the positive temperature coefficient voltage with the base electrode-emitter voltage of an NPN triode Q4 to generate low-temperature floating band-gap reference output voltage, utilizes a negative feedback loop technology controlled by a self-buffering loop to inhibit the voltage change of the output end of the band-gap reference source circuit, improves the adjustment speed of the band-gap reference source circuit loop, utilizes a current compensation circuit to increase the current flowing through a resistor R13 and a resistor R14, effectively inhibits the influence of mismatch on the band-gap reference output voltage caused by different current amplification factors of the PNP triodes at different process angles and temperatures, and further obtains high-performance band-gap reference voltage, thereby realizing the band-gap reference source circuit of the self-buffering loop control technology.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a band-gap reference source circuit of a self-buffering loop control technology.
Background
The band gap reference voltage source (BGR) has a low temperature coefficient characteristic, and is widely used in analog-to-digital converters (ADCs), low dropout linear regulators (LDOs), DC-DC circuits, and the like. With the increasing complexity of integrated circuit functions and applications, the conventional bandgap reference voltage source is difficult to meet the requirements of modern high-precision systems.
FIG. 1 is a drawingIn the traditional band-gap reference circuit structure, all resistors are made of the same material, the resistor R3 and the resistor R4 are completely the same, the area of an emitting electrode of an NPN triode Q1 is N times that of an emitting electrode of an NPN triode Q2, and the low-frequency gain A of an amplifier A1 is increased d Has A d >>1, the output voltage V of the band-gap reference circuit bg Is composed of
Wherein, V BE2 Is the base-emitter voltage, R, of an NPN transistor Q2 1 Is the resistance of a resistor R1, R 2 Is the impedance of the resistor R2, q is the amount of electronic charge, k is the boltzmann constant, and T is the absolute temperature. By optimizing the resistance values of the resistor R1 and the resistor R2, the parameter N and the like, the temperature T is measured r Can obtain
Because the output voltage of the traditional first-order band-gap reference circuit has the problem of high temperature drift coefficient, the application of the traditional first-order band-gap reference circuit in a high-precision system is limited.
Disclosure of Invention
The present invention is directed to solving the above problems of the prior art. A bandgap reference source circuit for self-buffering loop control is provided. The technical scheme of the invention is as follows:
a bandgap reference source circuit of a self-buffering loop control technique, comprising: the circuit comprises a starting circuit, a bias circuit and a band-gap reference core circuit, wherein the signal output end of the starting circuit is connected with the signal input end of the bias circuit, and the signal output end of the bias circuit is respectively connected with the signal input ends of the starting circuit and the band-gap reference core circuit; the starting circuit enables the band gap reference source circuit to normally work and generate band gap reference voltage output mainly through a PMOS (P-channel metal oxide semiconductor) transistor MP1, a PMOS transistor MP2 and a resistor R1, the bias circuit provides bias voltage signals for the band gap reference core circuit mainly through an NPN (negative-positive-negative) transistor Q1, an NPN transistor Q2, a resistor R5, an NMOS (N-channel metal oxide semiconductor) transistor MN1, an NMOS transistor MN2 and the PMOS transistor MP5, and the band gap reference core circuit generates band gap reference voltage mainly through a PNP transistor Q5, a PNP transistor Q6, a resistor R15, a resistor R11, a resistor R9, an NPN transistor Q4, a resistor R8 and a resistor R16.
Further, the start-up circuit includes: the transistor comprises a PMOS tube MP1, a PMOS tube MP2 and a resistor R1, wherein the source electrode of the PMOS tube MP2 is respectively connected with the source electrode of the PMOS tube MP1 and an external power supply VDD, the grid electrode of the PMOS tube MP2 is respectively connected with the grid electrode of the PMOS tube MP3, the grid electrode of the PMOS tube MP4, the drain electrode of the PMOS tube MP4 and the collector electrode of an NPN triode Q2, the drain electrode of the PMOS tube MP2 is respectively connected with the grid electrode of the PMOS tube MP1 and one end of the resistor R1, and the other end of the resistor R1 is connected with an external ground GND.
Further, the bias circuit includes: a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, an NMOS tube MN1, an NMOS tube MN2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, an NPN triode Q1, an NPN triode Q2 and an NPN triode Q3, wherein one end of the resistor R2 is respectively connected with one end of the resistor R6, one end of the resistor R7 and an external power supply VDD, the other end of the resistor R2 is connected with a source electrode of the PMOS tube MP3, a drain electrode of the PMOS tube MP3 is respectively connected with a drain electrode of the PMOS tube MP1, a collector electrode of the NPN triode Q1, a base electrode of the NPN triode Q1 and a base electrode of the NPN triode Q2, the other end of the resistor R6 is connected with a source electrode of the PMOS tube MP4, an emitter electrode of the NPN triode Q2 is connected with one end of the resistor R5, the other end of the resistor R5 is connected with the emitting electrode of the NPN triode Q1, the drain electrode of the NMOS tube MN1, the grid electrode of the NMOS tube MN1 and the grid electrode of the NMOS tube MN2 respectively, the source electrode of the NMOS tube MN1 is connected with one end of the resistor R3, the other end of the resistor R7 is connected with the source electrode of the PMOS tube MP5, the grid electrode of the PMOS tube MP5 is connected with the grid electrode of the PMOS tube MP6, the grid electrode of the PMOS tube MP7, the drain electrode of the PMOS tube MP5, the collector electrode of the NPN triode Q3 and the base electrode of the NPN triode Q3 respectively, the emitting electrode of the NPN triode Q3 is connected with the drain electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN2 is connected with one end of the resistor R4, and the other end of the resistor R4 is connected with the other end of the resistor R3 and the external ground GND respectively.
Further, the bandgap reference core circuit includes: operational amplifier A1, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, NPN transistor Q4, PNP transistor Q5, PNP transistor Q6, PNP transistor Q7, PNP transistor Q8, NPN transistor Q9, PMOS transistor MP6, PMOS transistor MP7 and PMOS transistor MP8, wherein the source of PMOS transistor MP8 is connected with one end of resistor R19, one end of resistor R20 and external power supply NPN VDD respectively, the grid of PMOS transistor MP8 is connected with the output end of operational amplifier A1, the drain of PMOS transistor MP8 is connected with the output end VREF of band gap reference, one end of resistor R16, the collector of NPN transistor Q4, the base of NPN transistor Q9 and the collector of NPN transistor Q9 respectively, the other end of resistor R16 is connected with one end of resistor R8 and the base of transistor Q4 respectively, an emitter of the NPN transistor Q4 is connected to one end of the resistor R11 and one end of the resistor R15, respectively, the other end of the resistor R15 is connected to a base of the PNP transistor Q5, the other end of the resistor R11 is connected to one end of the resistor R9 and a base of the PNP transistor Q6, an emitter of the NPN transistor Q9 is connected to a base of the PNP transistor Q7, a base of the PNP transistor Q8, and one end of the resistor R12, respectively, the other end of the resistor R19 is connected to a source of the PMOS transistor MP6, a drain of the PMOS transistor MP6 is connected to an emitter of the PNP transistor Q5 and an emitter of the PNP transistor Q6, respectively, a collector of the PNP transistor Q5 is connected to a collector of the PNP transistor Q7, one end of the resistor R13, and a reverse input end of the operational amplifier A1, respectively, a collector of the PNP transistor Q6 is connected to one end of the resistor R14, a collector of the PNP transistor Q8, and a non-inverting input end of the operational amplifier A1, respectively, and the other end of the resistor R13 is connected to one end of the resistor R10 and the other end of the resistor R14, the other end of the resistor R10 is connected with the other end of the resistor R8, the other end of the resistor R9, the other end of the resistor R12 and the external ground GND respectively, the other end of the resistor R20 is connected with the source electrode of the PMOS tube MP7, the drain electrode of the PMOS tube MP7 is connected with one end of the resistor R17 and one end of the resistor R18 respectively, the other end of the resistor R17 is connected with the emitting electrode of the PNP triode Q7, and the other end of the resistor R18 is connected with the emitting electrode of the PNP triode Q8.
Furthermore, in the bias circuit, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, and the resistor R7 are made of the same material, the emitter area of the NPN transistor Q2 is m times of that of the NPN transistor Q1, and the PMOS transistor MP3 and the PMOS transistor MP4 have the same channel width-length ratio, so that three NPN transistors are providedThe polar tube Q1 and the NPN polar tube Q2 have the same collector current, the current I flowing through the resistor R5 R5 Is I R5 ＝(V T lnm)/R 5 Wherein R is 5 Is the resistance value of the resistor R5, V T Is a thermal voltage; the NMOS transistor MN1 and the NMOS transistor MN2 have the same channel width-length ratio, the resistor R3 and the resistor R4 are completely the same, and the drain current I of the PMOS transistor MP5 P5 Has I P5 ＝2I R5 Providing a bias for the bandgap reference core circuit.
Further, in the band gap reference core circuit, all the resistors R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, and R20 are made of the same material, and the operational amplifier A1, the PMOS transistor MP8, R16, R8, NPN transistor Q4, R11, R9, R15, PNP transistor Q5, and PNP transistor Q6 form a self-buffering loop control structure, and when the VREF voltage at the output end of the band gap reference circuit rises, the base voltage of the NPN transistor Q4 rises, the base voltage of the PNP transistor Q5 rises, the collector voltage of the PNP transistor Q5 decreases, the reverse input terminal voltage of the operational amplifier A1 decreases, the gate voltage of the PMOS transistor MP8 rises, the VREF voltage at the output end of the band gap reference circuit decreases, and the rise of the voltage at the output end of the band gap reference circuit is suppressed, thereby implementing a negative feedback loop function of self-buffering loop control.
Further, in the band gap reference core circuit, the NPN triode Q9, the PNP triode Q7, the PNP triode Q8, the resistor R17, the resistor R18, the resistor R12, the resistor R19, the resistor R20, the PMOS transistor MP6, and the PMOS transistor MP7 form a current compensation circuit, wherein the NPN triode Q9 and the resistor R12 provide bias voltage for the PNP triode Q7 and the PNP triode Q8, and further increase current flowing through the resistor R13 and the resistor R14, thereby effectively suppressing influence of mismatch on band gap reference output voltage caused by different current amplification factors of the PNP triode at different process angles and temperatures.
Furthermore, in the band gap reference core circuit, the low-frequency gain of the amplifier A1 is far greater than 1, the area of the emitting electrode of the PNP triode Q5 is n times of that of the PNP triode Q6, and the resistor R13 and the resistor R14 are completedThe PNP triode Q6 and the PNP triode Q5 have the same current amplification factor, the NPN triode Q4 has the current amplification factor far larger than 1, the PNP triode Q5, the PNP triode Q6, the resistor R15 and the resistor R11 form a base current compensation circuit, and the resistance values of the resistor R9, the resistor R11 and the resistor R15 are optimized to enable the resistor R9, the resistor R11 and the resistor R15 to be enabled to be R 9 -R 15 -(R 9 R 15 )/R 11 If =0, the circuit outputs the output voltage V of VREF REF Is a V REF ＝(R 8 +R 16 )[(1+R 9 /R 11 )V T lnn+V BE4 ]/R 8 Wherein R is 8 Is the resistance value of the resistor R8, R 9 Is the resistance value of R9, R 11 Is the resistance of R1, R 15 Is the resistance of R15, R 16 Is the resistance value of the resistor R16, V BE4 Base-emitter voltage, V, of NPN transistor Q4 T Is a thermal voltage, a thermal voltage V T Having positive temperature characteristics, voltage V BE4 Has negative temperature characteristic, and can be used for optimizing the resistance value of the resistor R9, the resistance value of the resistor R11 and the parameter n at room temperature T r Can obtain
Therefore, the high-performance band-gap reference voltage with low-temperature characteristics is realized, wherein T is absolute temperature.
The invention has the following advantages and beneficial effects:
the band-gap reference source circuit of the self-buffering loop control technology is provided, positive temperature coefficient voltage is generated by utilizing related circuits such as a PNP triode Q5 and a PNP triode Q6 and is weighted with base electrode-emitter voltage of an NPN triode Q4 to generate low-temperature drift band-gap reference output voltage, VREF voltage change at the output end of the band-gap reference circuit is restrained by adopting a negative feedback loop controlled by an operational amplifier A1, a PMOS tube MP8, a resistor R16, a resistor R8, an NPN triode Q4, a resistor R11, a resistor R9, a resistor R15, the PNP triode Q5, the PNP triode Q6 and the like, the adjustment speed of the band-gap reference circuit loop is improved, currents flowing through the resistor R13 and the resistor R14 are increased by adopting a current compensation circuit formed by the NPN triode Q9, the PNP triode Q7, the PNP triode Q8, the resistor R17, the resistor R18, the resistor R12, the resistor R19, the resistor R20, the PMOS tube MP6, the PMOS tube MP7 and the like, so that high band-gap reference voltage mismatch caused by different current amplification multiples of different process angles and temperatures is restrained, and the band-gap output voltage is effectively, and the high-gap reference voltage is obtained.
Drawings
FIG. 1 is a schematic diagram of a conventional first order bandgap reference circuit;
FIG. 2 is a schematic diagram of a bandgap reference source circuit for a self-buffering loop control technique according to a preferred embodiment of the present invention;
fig. 3 is a simulation diagram of the output voltage temperature characteristic of the bandgap reference source circuit of the self-buffering loop control technique according to the preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail and clearly with reference to the accompanying drawings. The described embodiments are only some of the embodiments of the present invention.
The technical scheme for solving the technical problems is as follows:
in the embodiment of the application, a positive temperature coefficient voltage is generated by using related circuits such as a PNP triode Q5 and a PNP triode Q6, and is weighted with a base-emitter voltage of an NPN triode Q4 to generate a low-temperature drift bandgap reference output voltage, a negative feedback loop controlled by a self-buffering loop is adopted by an operational amplifier A1, a PMOS tube MP8, a resistor R16, a resistor R8, an NPN triode Q4, a resistor R11, a resistor R9, a resistor R15, a PNP triode Q5, a PNP triode Q6, and the like to suppress voltage variation of a bandgap reference circuit output terminal VREF, and the adjustment speed of the bandgap reference circuit loop is increased, a current compensation circuit is formed by the NPN triode Q9, the PNP triode Q7, the PNP triode Q8, the resistor R17, the resistor R18, the resistor R12, the resistor R19, the resistor R20, the PMOS tube MP6, the PMOS tube MP7, and the like to increase a current flowing through the resistor R13 and the resistor R14, and further effectively suppress the influence of the PNP triode current amplification factor on the bandgap output voltage caused by mismatch of the band gap due to different process angles and temperature, so as to obtain a high-performance bandgap reference voltage.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and specific embodiments.
Examples
A bandgap reference source circuit of self-buffering loop control technology is disclosed, as shown in FIG. 2, and includes a start circuit 1, a bias circuit 2 and a bandgap reference core circuit 3;
the signal output end of the starting circuit 1 is connected with the signal input end of the bias circuit 2, and the signal output end of the bias circuit 2 is respectively connected with the signal input ends of the starting circuit 1 and the band-gap reference core circuit 3; the starting circuit 1 enables the band gap reference circuit to normally work and generate band gap reference voltage output, the bias circuit 2 provides bias voltage signals for the band gap reference core circuit 3, and the band gap reference core circuit 3 obtains the high-performance band gap reference voltage with low temperature drift coefficient by adopting the technology of forming a self-buffering loop control structure by an operational amplifier A1, a PMOS (P-channel metal oxide semiconductor) transistor MP8, a resistor R16, a resistor R8, an NPN (negative-positive-negative) triode Q4, a resistor R11, a resistor R9, a resistor R15, a PNP triode Q5, a PNP triode Q6 and the like.
The starting circuit 1 only plays a role when the band gap reference circuit is electrified, and stops working after the band gap reference circuit is started, so that the influence of the starting circuit on a following circuit is avoided.
As a preferred technical solution, as shown in fig. 2, the starting circuit 1 includes: the transistor comprises a PMOS tube MP1, a PMOS tube MP2 and a resistor R1, wherein the source electrode of the PMOS tube MP2 is respectively connected with the source electrode of the PMOS tube MP1 and an external power supply VDD, the grid electrode of the PMOS tube MP2 is respectively connected with the grid electrode of the PMOS tube MP3, the grid electrode of the PMOS tube MP4, the drain electrode of the PMOS tube MP4 and the collector electrode of an NPN triode Q2, the drain electrode of the PMOS tube MP2 is respectively connected with the grid electrode of the PMOS tube MP1 and one end of the resistor R1, and the other end of the resistor R1 is connected with an external ground GND.
The bias circuit 2 includes: a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, an NMOS tube MN1, an NMOS tube MN2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, an NPN triode Q1, an NPN triode Q2 and an NPN triode Q3, wherein one end of the resistor R2 is respectively connected with one end of the resistor R6, one end of the resistor R7 and an external power supply VDD, the other end of the resistor R2 is connected with a source electrode of the PMOS tube MP3, a drain electrode of the PMOS tube MP3 is respectively connected with a drain electrode of the PMOS tube MP1, a collector electrode of the NPN triode Q1, a base electrode of the NPN triode Q1 and a base electrode of the NPN triode Q2, the other end of the resistor R6 is connected with a source electrode of the PMOS tube MP4, an emitter electrode of the NPN triode Q2 is connected with one end of the resistor R5, the other end of the resistor R5 is connected with the emitting electrode of the NPN triode Q1, the drain electrode of the NMOS tube MN1, the grid electrode of the NMOS tube MN1 and the grid electrode of the NMOS tube MN2 respectively, the source electrode of the NMOS tube MN1 is connected with one end of the resistor R3, the other end of the resistor R7 is connected with the source electrode of the PMOS tube MP5, the grid electrode of the PMOS tube MP5 is connected with the grid electrode of the PMOS tube MP6, the grid electrode of the PMOS tube MP7, the drain electrode of the PMOS tube MP5, the collector electrode of the NPN triode Q3 and the base electrode of the NPN triode Q3 respectively, the emitting electrode of the NPN triode Q3 is connected with the drain electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN2 is connected with one end of the resistor R4, and the other end of the resistor R4 is connected with the other end of the resistor R3 and the external ground GND respectively.
The band gap reference core circuit 3 includes: operational amplifier A1, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, NPN transistor Q4, PNP transistor Q5, PNP transistor Q6, PNP transistor Q7, PNP transistor Q8, NPN transistor Q9, PMOS transistor MP6, PMOS transistor MP7 and PMOS transistor MP8, wherein the source of PMOS transistor MP8 is connected with one end of resistor R19, one end of resistor R20 and external power supply NPN VDD respectively, the grid of PMOS transistor MP8 is connected with the output end of operational amplifier A1, the drain of PMOS transistor MP8 is connected with the output end VREF of band gap reference, one end of resistor R16, the collector of NPN transistor Q4, the base of NPN transistor Q9 and the collector of NPN transistor Q9 respectively, the other end of resistor R16 is connected with one end of resistor R8 and the base of transistor Q4 respectively, an emitter of the NPN transistor Q4 is connected to one end of the resistor R11 and one end of the resistor R15, respectively, the other end of the resistor R15 is connected to a base of the PNP transistor Q5, the other end of the resistor R11 is connected to one end of the resistor R9 and a base of the PNP transistor Q6, an emitter of the NPN transistor Q9 is connected to a base of the PNP transistor Q7, a base of the PNP transistor Q8, and one end of the resistor R12, respectively, the other end of the resistor R19 is connected to a source of the PMOS transistor MP6, a drain of the PMOS transistor MP6 is connected to an emitter of the PNP transistor Q5 and an emitter of the PNP transistor Q6, respectively, a collector of the PNP transistor Q5 is connected to a collector of the PNP transistor Q7, one end of the resistor R13, and a reverse input end of the operational amplifier A1, respectively, a collector of the PNP transistor Q6 is connected to one end of the resistor R14, a collector of the PNP transistor Q8, and a non-inverting input end of the operational amplifier A1, respectively, and the other end of the resistor R13 is connected to one end of the resistor R10 and the other end of the resistor R14, the other end of the resistor R10 is connected with the other end of the resistor R8, the other end of the resistor R9, the other end of the resistor R12 and the external ground GND respectively, the other end of the resistor R20 is connected with the source electrode of the PMOS tube MP7, the drain electrode of the PMOS tube MP7 is connected with one end of the resistor R17 and one end of the resistor R18 respectively, the other end of the resistor R17 is connected with the emitting electrode of the PNP triode Q7, and the other end of the resistor R18 is connected with the emitting electrode of the PNP triode Q8.
The operational amplifier A1 in the bandgap reference core circuit 3 is prior art.
In the bias circuit 2, all resistors are made of the same material, the emitter area of the NPN triode Q2 is m times that of the NPN triode Q1, and the PMOS transistor MP3 and the PMOS transistor MP4 have the same channel width-length ratio, so that the NPN triode Q1 and the NPN triode Q2 have the same collector current. Then, a current I flows through the resistor R5 R5 Is composed of
Wherein R is 5 Is the resistance value of the resistor R5, V T Is a thermal voltage. The NMOS transistor MN1 and the NMOS transistor MN2 have the same channel width-length ratio, the resistor R3 and the resistor R4 are completely the same, and the drain current I of the PMOS transistor MP5 P5 Has I P5 ＝2I R5 Which provides bias for the bandgap reference core circuit 3.
In the band-gap reference core circuit 3, all resistors adoptThe same material, an operational amplifier A1, a PMOS pipe MP8, a resistor R16, a resistor R8, an NPN triode Q4, a resistor R11, a resistor R9, a resistor R15, a PNP triode Q5, a PNP triode Q6 and the like form a self-buffering loop control structure, when the VREF voltage of the output end of the band-gap reference circuit rises, the base voltage of the NPN triode Q4 rises, the base voltage of the PNP triode Q5 rises, the collector voltage of the PNP triode Q5 decreases, the voltage of the reverse input end of the operational amplifier A1 decreases, the gate voltage of the PMOS pipe MP8 rises, the VREF voltage of the output end of the band-gap reference circuit decreases, and further the VREF voltage rise of the output end of the band-gap reference circuit is restrained, so that the negative feedback loop function of self-buffering loop control is realized, and the adjustment speed of a circuit loop is improved; the PNP transistor Q9, the PNP transistor Q7, the PNP transistor Q8, the resistor R17, the resistor R18, the resistor R12, the resistor R19, the resistor R20, the PMOS tube MP6 and the PMOS tube MP7 form a current compensation circuit, wherein the NPN transistor Q9 and the resistor R12 provide bias voltage for the PNP transistor Q7 and the PNP transistor Q8, and further increase the current flowing through the resistor R13 and the resistor R14, so that the influence of mismatch on the gap reference output voltage caused by different current amplification factors of the PNP transistor at different process angles and temperatures is effectively inhibited; the area of the emitting electrode of the PNP triode Q5 is n times of that of the PNP triode Q6, the resistor R13 is completely the same as the resistor R14, the amplifier A1 is the prior art, the low-frequency gain is far larger than 1, the PNP triode Q5, the PNP triode Q6, the resistor R15 and the resistor R11 form a base current compensation circuit, and then the base voltage V of the PNP transistor Q5 B5 And base voltage V of PNP tube Q6 B6 Is provided with
V B5 -V B6 ＝V T lnn (2)
Wherein, V T Is a thermal voltage; emitter voltage V of NPN triode Q4 E4 Is provided with
Wherein R is 9 Is the resistance value of the resistor R9, I B6 Is the base current, I, of a PNP triode Q6 B5 Is the base current, R, of a PNP triode Q5 11 Is a resistorResistance value of R11, R 15 Is the resistance value of the resistor R15; the resistor R17 is completely the same as the resistor R18, the PNP triode Q7 is completely the same as the PNP triode Q8, the PNP triode Q6 and the PNP triode Q5 have the same current amplification factor, and the PNP triode Q6 and the PNP triode Q5 have the same base current (i.e. I) B6 ＝I B5 ) By optimizing the resistance values of the resistor R9, the resistor R11 and the resistor R15, R is enabled 9 -R 15 -(R 9 R 15 )/R 11 =0, emitter voltage V of NPN triode Q4 E4 Is approximated to
The current amplification factor of the NPN triode Q4 is far greater than 1, and then the output voltage V of the circuit output end VREF REF Is composed of
Wherein R is 8 Is the resistance of a resistor R8, R 16 Is the resistance value of the resistor R16, V BE4 The base-emitter voltage of NPN transistor Q4. In the formula (5), a thermal voltage V T Base-emitter voltage V of NPN triode Q4 with positive temperature characteristic BE4 The band gap reference voltage has negative temperature characteristics, so that the band gap reference voltage with low temperature characteristics can be obtained by optimizing the resistance value of the resistor R9, the resistance value of the resistor R11 and the parameter n.
FIG. 3 shows the output voltage V of the bandgap reference source circuit of the self-buffering loop control technique of the present invention ref The abscissa is the temperature T, and the ordinate is the output voltage of the bandgap reference source circuit. Simulation results show that the output voltage V of the band-gap reference source circuit of the self-buffering loop control technology is within the temperature range of-45 ℃ to 125 DEG C REF The temperature coefficient of (a) is only 1.807 ppm/DEG C.
In the embodiments of the present application, a bandgap reference source circuit based on a self-buffering loop control technology includes, for example, a start-up circuit, a bias circuit, and a bandgap reference core circuit. According to the embodiment of the application, the PNP triode Q5, the PNP triode Q6 and other related circuits generate positive temperature coefficient voltage and are weighted with the base electrode-emitter voltage of the NPN triode Q4 to generate low-temperature drift band gap reference output voltage, a negative feedback loop controlled by a self-buffering loop is adopted by the operational amplifier A1, the PMOS pipe MP8, the resistor R16, the resistor R8, the NPN triode Q4, the resistor R11, the resistor R9, the resistor R15, the PNP triode Q5, the PNP triode Q6 and the like to suppress the voltage change of the output end VREF of the band gap reference circuit, the adjustment speed of the band gap reference circuit loop is improved, the NPN triode Q9, the PNP triode Q7, the PNP triode Q8, the resistor R17, the resistor R18, the resistor R12, the resistor R19, the resistor R20, the PMOS pipe MP6, the PMOS pipe MP7 and the like are adopted to form a current compensation circuit to increase the current flowing through the resistor R13 and the resistor R14, and further effectively suppress the influence on the band gap output voltage caused by different current amplification multiples under different process angles and temperatures, and further obtain the band gap reference voltage with high reference performance.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The above examples are to be construed as merely illustrative and not limitative of the remainder of the disclosure. After reading the description of the invention, the skilled person can make various changes or modifications to the invention, and these equivalent changes and modifications also fall into the scope of the invention defined by the claims.
Claims (8)
1. A bandgap reference source circuit based on self-buffering loop control technology, comprising: the circuit comprises a starting circuit (1), a bias circuit (2) and a band-gap reference core circuit (3), wherein a signal output end of the starting circuit (1) is connected with a signal input end of the bias circuit (2), and a signal output end of the bias circuit (2) is respectively connected with signal input ends of the starting circuit (1) and the band-gap reference core circuit (3); the band-gap reference source circuit comprises a starting circuit (1), a band-gap reference source circuit, a bias circuit (2) and a band-gap reference core circuit, wherein the starting circuit (1) enables the band-gap reference source circuit to normally work and generate band-gap reference voltage output mainly through a PMOS (P-channel metal oxide semiconductor) tube MP1, a PMOS tube MP2 and a resistor R1, the bias circuit (2) mainly provides bias voltage signals for the band-gap reference core circuit (3) through an NPN (negative-positive-negative) triode Q1, an NPN triode Q2, a resistor R5, an NMOS (N-channel metal oxide semiconductor) tube MN1, an NMOS tube MN2 and the PMOS tube MP5, and the band-gap reference core circuit (3) generates band-gap reference voltage mainly through a PNP triode Q5, a PNP triode Q6, a resistor R15, a resistor R11, a resistor R9, an NPN triode Q4, a resistor R8 and a resistor R16.
2. A bandgap reference source circuit according to self-snubber loop control technology, characterized in that the start-up circuit (1) comprises: the transistor circuit comprises a PMOS (P-channel metal oxide semiconductor) transistor MP1, a PMOS transistor MP2 and a resistor R1, wherein the source electrode of the PMOS transistor MP2 is respectively connected with the source electrode of the PMOS transistor MP1 and an external power supply VDD, the grid electrode of the PMOS transistor MP2 is respectively connected with the grid electrode of the PMOS transistor MP3, the grid electrode of the PMOS transistor MP4, the drain electrode of the PMOS transistor MP4 and the collector electrode of an NPN (negative-positive-negative) triode Q2, the drain electrode of the PMOS transistor MP2 is respectively connected with the grid electrode of the PMOS transistor MP1 and one end of the resistor R1, and the other end of the resistor R1 is connected with an external ground GND.
3. A bandgap reference source circuit according to claim 1, wherein the bias circuit (2) comprises: a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, an NMOS tube MN1, an NMOS tube MN2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, an NPN triode Q1, an NPN triode Q2 and an NPN triode Q3, wherein one end of the resistor R2 is respectively connected with one end of the resistor R6, one end of the resistor R7 and an external power supply VDD, the other end of the resistor R2 is connected with a source electrode of the PMOS tube MP3, a drain electrode of the PMOS tube MP3 is respectively connected with a drain electrode of the PMOS tube MP1, a collector electrode of the NPN triode Q1, a base electrode of the NPN triode Q1 and a base electrode of the NPN triode Q2, the other end of the resistor R6 is connected with a source electrode of the PMOS tube MP4, an emitter electrode of the NPN triode Q2 is connected with one end of the resistor R5, the other end of the resistor R5 is connected with the emitting electrode of the NPN triode Q1, the drain electrode of the NMOS tube MN1, the grid electrode of the NMOS tube MN1 and the grid electrode of the NMOS tube MN2 respectively, the source electrode of the NMOS tube MN1 is connected with one end of the resistor R3, the other end of the resistor R7 is connected with the source electrode of the PMOS tube MP5, the grid electrode of the PMOS tube MP5 is connected with the grid electrode of the PMOS tube MP6, the grid electrode of the PMOS tube MP7, the drain electrode of the PMOS tube MP5, the collector electrode of the NPN triode Q3 and the base electrode of the NPN triode Q3 respectively, the emitting electrode of the NPN triode Q3 is connected with the drain electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN2 is connected with one end of the resistor R4, and the other end of the resistor R4 is connected with the other end of the resistor R3 and the external ground GND respectively.
4. The bandgap reference source circuit of self-snubber loop control technology according to claim 1, wherein the bandgap reference core circuit (3) comprises: an operational amplifier A1, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an NPN transistor Q4, an NPN transistor Q5, an PNP transistor Q6, an NPN transistor Q7, an NPN transistor Q8, an NPN transistor Q9, a PMOS transistor MP6, a PMOS transistor MP7, and a PMOS transistor MP8, wherein a source of the PMOS transistor MP8 is respectively connected with one end of the resistor R19, one end of the resistor R20, and an external power supply NPN VDD, a gate of the PMOS transistor MP8 is connected with an output end of the operational amplifier A1, a drain of the PMOS transistor MP8 is respectively connected with an output end VREF of a band gap reference, one end of the resistor R16, a collector of the NPN transistor Q4, a base of the NPN transistor Q9, and a collector of the NPN transistor Q9, the other end of the resistor R16 is respectively connected with one end of the resistor R8 and a base of the triode Q4, an emitter of the NPN transistor Q4 is connected to one end of the resistor R11 and one end of the resistor R15, respectively, the other end of the resistor R15 is connected to a base of the PNP transistor Q5, the other end of the resistor R11 is connected to one end of the resistor R9 and a base of the PNP transistor Q6, an emitter of the NPN transistor Q9 is connected to a base of the PNP transistor Q7, a base of the PNP transistor Q8, and one end of the resistor R12, respectively, the other end of the resistor R19 is connected to a source of the PMOS transistor MP6, a drain of the PMOS transistor MP6 is connected to an emitter of the PNP transistor Q5 and an emitter of the PNP transistor Q6, respectively, a collector of the PNP transistor Q5 is connected to a collector of the PNP transistor Q7, one end of the resistor R13, and a reverse input end of the operational amplifier A1, respectively, a collector of the PNP transistor Q6 is connected to one end of the resistor R14, a collector of the PNP transistor Q8, and a non-inverting input end of the operational amplifier A1, respectively, and the other end of the resistor R13 is connected to one end of the resistor R10 and the other end of the resistor R14, the other end of the resistor R10 is connected with the other end of the resistor R8, the other end of the resistor R9, the other end of the resistor R12 and the external ground GND respectively, the other end of the resistor R20 is connected with the source electrode of the PMOS tube MP7, the drain electrode of the PMOS tube MP7 is connected with one end of the resistor R17 and one end of the resistor R18 respectively, the other end of the resistor R17 is connected with the emitting electrode of the PNP triode Q7, and the other end of the resistor R18 is connected with the emitting electrode of the PNP triode Q8.
5. The bandgap reference source circuit according to claim 3, wherein in the bias circuit (2), the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, and the resistor R7 are made of the same material, an emitter area of the NPN transistor Q2 is m times that of the NPN transistor Q1, and the PMOS transistor MP3 and the PMOS transistor MP4 have the same channel width-to-length ratio, so that the NPN transistor Q1 and the NPN transistor Q2 have the same collector current, and a current I flowing through the resistor R5 is equal to a current I flowing through the resistor R5 R5 Is I R5 ＝(V T lnm)/R 5 Wherein R is 5 Is the resistance value of the resistor R5, V T Is a thermal voltage; the NMOS transistor MN1 and the NMOS transistor MN2 have the same channel width-length ratio, the resistor R3 and the resistor R4 are completely the same, and the drain current I of the PMOS transistor MP5 P5 Has I P5 ＝2I R5 Providing a bias for the bandgap reference core circuit (3).
6. The bandgap reference source circuit according to claim 4, wherein in the bandgap reference core circuit (3), all of the resistors R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19 and R20 are made of the same material, and the operational amplifier A1, the PMOS transistor MP8, R16, R8, the NPN transistor Q4, R11, R9, R15, PNP transistor Q5 and PNP transistor Q6 form a self-buffering loop control structure, and when the voltage at the output end of the bandgap reference circuit increases, the base voltage of the NPN transistor Q4 increases, the base voltage of the PNP transistor Q5 increases, the collector voltage of the PNP transistor Q5 decreases, the voltage at the inverting input end of the operational amplifier A1 decreases, the gate voltage of the PMOS transistor MP8 increases, the VREF voltage at the output end of the bandgap reference circuit decreases, and further the bandgap reference circuit is inhibited from increasing, thereby realizing the function of the self-buffering loop control.
7. The band gap reference source circuit of the self-snubber loop control technology according to claim 6, wherein in the band gap reference core circuit (3), the NPN transistor Q9, the PNP transistor Q7, the PNP transistor Q8, the resistor R17, the resistor R18, the resistor R12, the resistor R19, the resistor R20, the PMOS transistor MP6, and the PMOS transistor MP7 form a current compensation circuit, wherein the NPN transistor Q9 and the resistor R12 provide bias voltages for the PNP transistor Q7 and the PNP transistor Q8, thereby increasing currents flowing through the resistor R13 and the resistor R14, and effectively suppressing an influence of mismatch on the band gap reference output voltage caused by different current amplification factors of the PNP transistor at different process angles and temperatures.
8. The bandgap reference source circuit according to claim 6 or 7, wherein in the bandgap reference core circuit (3), the low-frequency gain of the amplifier A1 is much greater than 1, the emitter area of the PNP transistor Q5 is n times that of the PNP transistor Q6, the resistor R13 is identical to the resistor R14, the resistor R17 is identical to the resistor R18, the PNP transistor Q7 is identical to the PNP transistor Q8, the PNP transistor Q6 and the PNP transistor Q5 have the same current amplification factor, the current amplification factor of the NPN transistor Q4 is much greater than 1, the PNP transistor Q5, the PNP transistor Q6, the resistor R15 and the resistor R11 form a base current compensation circuit, and the base current compensation circuit is formed by optimizing the resistor R9. The resistances of the resistor R11 and the resistor R15 are such that R 9 -R 15 -(R 9 R 15 )/R 11 If =0, the circuit outputs the output voltage V of VREF REF Is a V REF ＝(R 8 +R 16 )[(1+R 9 /R 11 )V T lnn+V BE4 ]/R 8 Wherein R is 8 Is the resistance value of the resistor R8, R 9 Is the resistance of R9, R 11 Is the resistance of R1, R 15 Is the resistance value of R15, R 16 Is the resistance value of the resistor R16, V BE4 Base-emitter voltage, V, of NPN transistor Q4 T Is a thermal voltage, a thermal voltage V T Having positive temperature characteristics, voltage V BE4 Has negative temperature characteristic, and can be used for optimizing the resistance value of the resistor R9, the resistance value of the resistor R11 and the parameter n at room temperature T r Can obtain
Therefore, the high-performance band-gap reference voltage with low-temperature characteristics is realized, wherein T is absolute temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211381675.6A CN115657781A (en) | 2022-11-04 | 2022-11-04 | Band-gap reference source circuit of self-buffering loop control technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211381675.6A CN115657781A (en) | 2022-11-04 | 2022-11-04 | Band-gap reference source circuit of self-buffering loop control technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115657781A true CN115657781A (en) | 2023-01-31 |
Family
ID=85015357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211381675.6A Pending CN115657781A (en) | 2022-11-04 | 2022-11-04 | Band-gap reference source circuit of self-buffering loop control technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115657781A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117270621A (en) * | 2023-11-23 | 2023-12-22 | 上海芯炽科技集团有限公司 | Single temperature calibration structure of low temperature drift band gap reference circuit |
-
2022
- 2022-11-04 CN CN202211381675.6A patent/CN115657781A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117270621A (en) * | 2023-11-23 | 2023-12-22 | 上海芯炽科技集团有限公司 | Single temperature calibration structure of low temperature drift band gap reference circuit |
| CN117270621B (en) * | 2023-11-23 | 2024-02-13 | 上海芯炽科技集团有限公司 | Single temperature calibration structure of low temperature drift band gap reference circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111190454B (en) | Curvature compensation low-temperature drift band gap reference voltage source circuit | |
| CN108052154B (en) | High-order low-temperature drift band gap reference circuit without operational amplifier | |
| Huang et al. | A sub-200nW all-in-one bandgap voltage and current reference without amplifiers | |
| KR100981732B1 (en) | The Band-gap reference voltage generator | |
| CN110362144B (en) | Low-temperature drift high-power-supply rejection-ratio band-gap reference circuit based on exponential compensation | |
| CN104122918A (en) | Band-gap reference circuit | |
| CN111930169B (en) | Negative feedback subsection curvature compensation band gap reference circuit | |
| CN108536210B (en) | Smooth temperature compensation band gap reference source circuit | |
| CN115437446B (en) | High-precision curvature compensation band gap reference circuit | |
| CN111045470B (en) | Band-gap reference circuit with low offset voltage and high power supply rejection ratio | |
| CN115657781A (en) | Band-gap reference source circuit of self-buffering loop control technology | |
| CN109491439B (en) | Reference voltage source and working method thereof | |
| CN113467562A (en) | High-end operational amplifier-free band gap reference source | |
| CN116880644A (en) | High-order curvature temperature compensation band gap reference circuit | |
| CN116301178B (en) | Band gap reference circuit and chip | |
| CN115857608B (en) | Band-gap reference source for realizing high-order temperature compensation in wide range by using depletion tube | |
| CN114265466B (en) | Low-temperature drift band gap reference voltage source based on high-order temperature curvature compensation | |
| CN215340874U (en) | Zero temperature coefficient current generating circuit with band gap reference | |
| Bagundol et al. | Design Methodology of a Voltage Bandgap Reference with High PSRR in Advanced Technology Nodes for LDO Application | |
| WO2022236890A1 (en) | Bandgap reference voltage generating circuit having high-order temperature compensation | |
| Peng et al. | Implementation of a low TC high PSRR CMOS bandgap voltage reference circuit | |
| CN114489223A (en) | High PSRR band-gap voltage source circuit for DC-DC switching power supply chip | |
| Zhou et al. | A high-order temperature-compensated CMOS bandgap voltage reference | |
| CN113655841A (en) | Band gap reference voltage circuit | |
| US10642304B1 (en) | Low voltage ultra-low power continuous time reverse bandgap reference circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |