CN116301178B - Band gap reference circuit and chip - Google Patents

Band gap reference circuit and chip Download PDF

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Publication number
CN116301178B
CN116301178B CN202310272301.9A CN202310272301A CN116301178B CN 116301178 B CN116301178 B CN 116301178B CN 202310272301 A CN202310272301 A CN 202310272301A CN 116301178 B CN116301178 B CN 116301178B
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circuit
field effect
effect transistor
transistor
temperature coefficient
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CN116301178A (en
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张钒睿
尚宇
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Longxin Zhongke Nanjing Technology Co ltd
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Longxin Zhongke Nanjing Technology Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The invention provides a band gap reference circuit and a chip, wherein a first negative temperature coefficient circuit comprises a first field effect transistor and a first BJT transistor which are connected in series, and can generate a first negative temperature coefficient voltage. The second negative temperature coefficient circuit comprises a second field effect transistor and a second BJT transistor which are connected in series, and can generate a second negative temperature coefficient voltage. The second field effect tube is also connected with a first resistor, and the superposition circuit is connected between the positive electrode of the power supply and the first resistor and between the positive electrode of the power supply and the first field effect tube. The superposition circuit can obtain positive temperature coefficient voltage based on the first negative temperature coefficient voltage and the second negative temperature coefficient voltage, and output band gap reference voltage after superposition. The invention can obtain the band-gap reference voltage with lower temperature coefficient, thereby improving the stability of the band-gap reference voltage.

Description

Band gap reference circuit and chip
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a bandgap reference circuit and a chip.
Background
As some integrated circuit chips are used under severe temperature conditions such as high temperature and low temperature, in order to ensure that the circuit can still work normally under the high temperature and low temperature, a bandgap reference circuit is often used to provide a relatively stable reference voltage or reference current for the circuit. For example, bandgap reference circuits are commonly used in digital-to-analog converters, analog-to-digital converters, low dropout linear regulators, and the like.
In order to output a required band gap reference voltage, the conventional band gap reference circuit adopts the mode that a negative temperature coefficient voltage and a positive temperature coefficient voltage are overlapped to construct a zero temperature coefficient voltage, namely the band gap reference voltage. Wherein the negative temperature coefficient voltage is derived from the base-emitter voltage V BE of the BJT transistor (Bipolar Junction Transistor, bipolar transistor), and the positive temperature coefficient voltage is derived from the base-emitter voltage difference V BE of the two BJT transistors.
However, in practical applications, such bandgap reference circuits are limited by the self temperature characteristics of the BJT transistors, and the temperature coefficient corresponding to the bandgap reference voltage is still high, so that the bandgap reference voltage has poor stability when used in environments with complex temperature changes.
Disclosure of Invention
The invention provides a band-gap reference circuit and a chip, which are used for solving the problem that the stability of the band-gap reference voltage is poor when the band-gap reference circuit is used in an environment with complex temperature change because the temperature coefficient corresponding to the existing band-gap reference voltage is still higher.
The embodiment of the invention provides a band gap reference circuit, which comprises: the first negative temperature coefficient circuit, the second negative temperature coefficient circuit, the first resistor and the superposition circuit;
The first negative temperature coefficient circuit comprises a first field effect transistor and a first BJT transistor which are connected in series, the second negative temperature coefficient circuit comprises a second field effect transistor and a second BJT transistor which are connected in series, the first resistor is connected in series with the second field effect transistor, the grid electrode and the drain electrode of the first field effect transistor are connected, and the grid electrode and the drain electrode of the second field effect transistor are connected; wherein the first and second BJT transistors have different current magnitudes;
The superposition circuit is connected between the positive electrode of the power supply and the first resistor and between the positive electrode of the power supply and the drain electrode of the first field effect transistor, and the collector electrodes and the base electrodes of the first BJT transistor and the second BJT transistor are grounded;
The first node between the superposition circuit and the first field effect transistor is used for generating a first negative temperature coefficient voltage, the second node between the first resistor and the second field effect transistor is used for generating a second negative temperature coefficient voltage, and the superposition circuit is used for obtaining a positive temperature coefficient voltage according to the first negative temperature coefficient voltage and the second negative temperature coefficient voltage and superposing and outputting a band gap reference voltage.
Optionally, the superimposing circuit includes a first adjusting circuit, a second adjusting circuit, and an operational amplifier;
the first regulating circuit is connected between the positive electrode of the power supply and the first field effect transistor, and the second regulating circuit is connected between the positive electrode of the power supply and the first resistor;
the negative phase input end of the operational amplifier is connected to the first node, the positive phase input end of the operational amplifier is connected to a third node between the second regulating circuit and the first resistor, and the output end of the operational amplifier is connected with the control ends of the first regulating circuit and the second regulating circuit at the same time;
And the operational amplifier controls the voltages of the first node and the third node to be the same through the first regulating circuit and the second regulating circuit, and outputs the band gap reference voltage through superposition of the second regulating circuit.
Optionally, the first adjusting circuit comprises a third field effect transistor and a second resistor which are connected in series;
The first field effect tube is connected with the second resistor in series, and the third field effect tube is also connected with the positive electrode of the power supply.
Optionally, the second adjusting circuit comprises a fourth field effect transistor and a third resistor which are connected in series;
The first resistor is connected with the third resistor in series, and the fourth field effect transistor is also connected with the positive electrode of the power supply; and a node between the fourth field effect transistor and the third resistor is used for outputting the band gap reference voltage.
Optionally, the operational amplifier includes a first current mirror circuit, a second current mirror circuit, and an operational amplifier control circuit;
The first current mirror circuit is connected between the positive electrode of the power supply and the grounding end, is connected with the first node and is used for mirroring the current of the first negative temperature coefficient circuit; the second current mirror circuit is connected between the positive electrode of the power supply and the grounding end and is connected with the third node, and the second current mirror circuit is used for mirror-image copying of the current of the second negative temperature coefficient circuit; the first current mirror circuit is also connected with the second current mirror circuit;
the operational amplifier control circuit is connected between the positive electrode of the power supply and the grounding end, and is connected between the second current mirror circuit and the first regulating circuit and between the second regulating circuit, and the operational amplifier control circuit is used for controlling the first regulating circuit and the second regulating circuit according to the electric signal feedback of the first current mirror circuit and the second current mirror circuit so that the voltage of the first node is the same as the voltage of the third node.
Optionally, the first current mirror circuit includes a fifth field effect transistor, a sixth field effect transistor and a third BJT transistor;
the fifth field effect transistor, the sixth field effect transistor and the third BJT transistor are sequentially connected in series, the fifth field effect transistor is connected with the positive electrode of the power supply, the collector electrode and the base electrode of the third BJT transistor are grounded, and the grid electrode of the sixth field effect transistor is connected to the first node.
Optionally, the second current mirror circuit includes a ninth field effect transistor, a tenth field effect transistor, and a fourth BJT transistor;
The ninth field effect transistor, the tenth field effect transistor and the fourth BJT transistor are sequentially connected in series, the ninth field effect transistor is connected with the positive electrode of the power supply, the collector electrode and the base electrode of the fourth BJT transistor are grounded, and the grid electrode of the tenth field effect transistor is connected to the third node;
And the grid electrode of the fifth field effect transistor is connected with the grid electrode of the ninth field effect transistor.
Optionally, the operational amplifier control circuit comprises a seventh field effect transistor and an eighth field effect transistor which are connected in series;
The seventh field effect transistor is also connected with the positive electrode of the power supply, the eighth field effect transistor is grounded, and the drain electrode and the grid electrode of the seventh field effect transistor are simultaneously connected with the control ends of the first regulating circuit and the second regulating circuit.
Optionally, N second BJT transistors are connected in parallel, and N second field effect transistors are connected in parallel; wherein N is more than or equal to 2, the width-to-length ratio of the first field effect transistor is the same as that of the second field effect transistor, and the area of the second BJT transistor is the same as that of the first BJT transistor.
The embodiment of the invention also provides a chip, which comprises any band gap reference circuit.
Compared with the prior art, the invention has the following advantages:
the band gap reference circuit and the chip provided by the embodiment of the invention have the advantages that the first negative temperature coefficient circuit comprises the first field effect transistor and the first BJT transistor which are connected in series, and the first negative temperature coefficient voltage can be generated. The second negative temperature coefficient circuit comprises a second field effect transistor and a second BJT transistor which are connected in series, and can generate a second negative temperature coefficient voltage. The second field effect tube is also connected with a first resistor, and the superposition circuit is connected between the positive electrode of the power supply and the first resistor and between the positive electrode of the power supply and the first field effect tube. The superposition circuit can obtain positive temperature coefficient voltage based on the first negative temperature coefficient voltage and the second negative temperature coefficient voltage, and output band gap reference voltage after superposition. According to the invention, the temperature characteristic of the field effect transistor is utilized, the field effect transistor is serially connected with the BJT diode to reconstruct and generate negative temperature coefficient voltage, and then the negative temperature coefficient voltage is overlapped with positive temperature coefficient voltage, so that band gap reference voltage with lower temperature coefficient can be obtained, and the stability of the band gap reference voltage can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a graph showing the base-emitter voltage V BE of a BJT transistor according to the prior art as a function of temperature T;
FIG. 2 is a graph of bandgap reference voltage V ref as a function of temperature T in the prior art;
Fig. 3 is a graph showing a voltage V GS of a gate-source electrode of a MOS transistor according to the prior art, which varies with a temperature T;
FIG. 4 is a graph showing the variation of V GS+VBE with temperature T in an example of the present invention;
FIG. 5 bandgap reference voltages in an embodiment of the invention A curve varying with temperature T;
FIG. 6 is a schematic diagram of a bandgap reference circuit according to an embodiment of the invention;
FIG. 7 is a diagram of simulation results of the bandgap reference circuit illustrated in FIG. 6 in accordance with an embodiment of the present invention;
FIG. 8 is a circuit diagram of a first bandgap reference circuit in accordance with an embodiment of the invention;
fig. 9 is a circuit diagram of a second bandgap reference circuit in accordance with an embodiment of the invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 6, an embodiment of the present invention provides a bandgap reference circuit including: a first negative temperature coefficient circuit 10, a second negative temperature coefficient circuit 11, a first resistor R1, and a superimposing circuit 12;
The first negative temperature coefficient circuit 10 comprises a first field effect transistor M1 and a first BJT transistor Q1 which are connected in series, the second negative temperature coefficient circuit 11 comprises a second field effect transistor M2 and a second BJT transistor Q2 which are connected in series, the first resistor R1 is connected in series with the second field effect transistor M2, the gate and the drain of the first field effect transistor M1 are connected, and the gate and the drain of the second field effect transistor M2 are connected; wherein the current magnitudes of the first and second BJT transistors Q1 and Q2 are different;
The superimposing circuit 12 is connected between the power supply positive electrode VDD and the first resistor R1, and between the power supply positive electrode VDD and the drain electrode of the first field effect transistor M1, and the collector and the base of the first BJT transistor Q1 and the second BJT transistor Q2 are grounded;
The first node a between the superimposing circuit 12 and the first fet M1 is configured to generate a first negative temperature coefficient voltage, the second node b between the first resistor R1 and the second fet M2 is configured to generate a second negative temperature coefficient voltage, and the superimposing circuit 12 is configured to obtain a positive temperature coefficient voltage according to the first negative temperature coefficient voltage and the second negative temperature coefficient voltage, and superimpose and output a bandgap reference voltage.
Specifically, it is known to those skilled in the art that in order to obtain the bandgap reference voltage, it is necessary to obtain a voltage having a negative temperature coefficient and a voltage having a positive temperature coefficient by constructing a circuit, and then superposing the two voltages, so as to obtain a voltage having a zero temperature coefficient, that is, a desired bandgap reference voltage.
Fig. 1 shows the base-emitter voltage V BE of the BJT transistor as a function of temperature T, and it can be seen from fig. 1 that V BE gradually decreases with increasing temperature, and the absolute value of the rate of change of V BE gradually increases with increasing temperature. Thus, in a conventional bandgap reference circuit, V BE is used as the negative temperature coefficient voltage. Since the slope of the temperature change of the difference Δv BE between V BE in the two BJT transistors is approximately constant, using Δv BE as the positive temperature coefficient voltage, the curve of the bandgap reference voltage V ref with temperature T can be obtained after superposition is shown in fig. 2. It will be readily appreciated, in conjunction with the schematic of fig. 2, that the reference voltage output by the bandgap reference circuit will have a zero slope at intermediate temperatures, and will be positive below that temperature and negative above that temperature. For the temperature coefficient TCF of the bandgap reference circuit, the calculation formula is tcf=Δv/(V ref ×δt), where Δv represents the difference in voltage change between the measured temperatures T1 and T2, V ref represents the reference voltage value, and δt represents the difference between the temperatures T1 and T2. As shown in fig. 1 to 2, the analysis shows that the temperature coefficient TCF is larger due to the larger Δv corresponding to the interval from T1 to T2 in fig. 2, which is limited by the characteristic of V BE that varies with temperature, and therefore the reference voltage output by the conventional bandgap reference circuit is greatly affected by temperature.
In the bandgap reference circuit of the embodiment of the invention, the voltage with negative temperature coefficient can be obtained by connecting the BJT transistor and the MOS transistor in series by utilizing the temperature characteristic of the voltage V BE of the base-emitter of the BJT transistor and the temperature characteristic of the voltage V GS of the gate-source of the field effect transistor (also called MOS transistor). Fig. 3 shows a variation curve of V GS with temperature T in the MOS transistor, and it can be seen from fig. 3 that V GS is a voltage with negative temperature coefficient, and the absolute value of the variation rate of V GS gradually decreases with increasing temperature. Therefore, by using the MOS transistor and the BJT transistor in series, the V GS+VBE shown in fig. 4 can be obtained by adjusting the width-to-length ratio of the MOS transistor, the area of the BJT transistor, or the current of the MOS transistor, and the absolute value of the change rate increases with the increase of temperature.
According to the above features, V GS+VBE can be used as the negative temperature coefficient voltage instead of V BE in the conventional bandgap reference circuit. Meanwhile, the difference DeltaV GS+BE between the two groups of V GS+VBE can replace DeltaV BE to be used as positive temperature coefficient voltage, and then the voltages are overlapped to obtain a new voltage。
It will be readily appreciated that in conventional bandgap reference circuits V ref=VBE+αΔVBE, a is a coefficient related to the resistance of the resistor in the circuit. Whereas in the bandgap reference circuit of the embodiment of the invention,= (V GS+VBE）+α´ΔVGS+BE, α' is a coefficient related to the resistance of the resistor in the circuit. In the embodiment of the invention, bandgap reference voltage/>The curve as a function of temperature T is shown in fig. 5. As is readily understood from the illustration of fig. 5, the reference voltage output from the bandgap reference circuit has two points with zero slope between the same temperature intervals T1 and T2, and the corresponding Δv' is smaller than Δv, so that a bandgap reference voltage with a lower temperature coefficient can be obtained.
Fig. 6 shows a schematic diagram of a bandgap reference circuit according to an embodiment of the invention, where fig. 6 includes a first negative temperature coefficient circuit 10 for generating a first negative temperature coefficient voltage, a second negative temperature coefficient circuit 11 for generating a second negative temperature coefficient voltage, a first resistor R1, and a superposition circuit 12.
In connection with the foregoing description, it is readily understood that the first negative temperature coefficient circuit 10 and the second negative temperature coefficient circuit 11 each include a field effect transistor and a BJT transistor connected in series with each other. Specifically, the first negative temperature coefficient circuit 10 includes a first field effect transistor M1 and a first BJT transistor Q1 connected in series, and the second negative temperature coefficient circuit 11 includes a second field effect transistor M2 and a second BJT transistor Q2 connected in series. In the embodiment of the present invention, the gate and the drain of the first field effect transistor M1 are further connected, and the gate and the drain of the second field effect transistor M2 are connected, so that the two MOS transistors form a "diode connection", and the voltage V GS with a desired negative temperature coefficient can be obtained.
For example, the first field effect transistor M1 and the second field effect transistor M2 used in the embodiment of the present invention may be NMOS transistors, and the first BJT transistor Q1 and the second BJT transistor Q2 may be PNP transistors, and the following connection relationship and description of the circuit principle are also described by taking this as an example.
The superimposing circuit 12 is connected between the power supply positive electrode VDD and the first resistor R1, and between the power supply positive electrode VDD and the drain electrode of the first field effect transistor M1, and the collector and the base of the first BJT transistor Q1 and the second BJT transistor Q2 are grounded;
The first node a between the superimposing circuit 12 and the first fet M1 is configured to generate a first negative temperature coefficient voltage V a,Va=VGS1+VBE1, where V GS1 represents a voltage across the first fet M1 and V BE1 represents a voltage across the first BJT transistor Q1. The second node b between the first resistor R1 and the second fet M2 is configured to generate a second negative temperature coefficient voltage V b,Vb=VGS2+VBE2, where V GS2 represents a voltage across the second fet M2 and V BE2 represents a voltage across the second BJT transistor Q2. V a and V b are both negative temperature coefficient voltages having the temperature characteristics illustrated in fig. 4.
The superimposing circuit 12 is connected to the first negative temperature coefficient circuit 10 and the second negative temperature coefficient circuit 11 at the same time, so that a positive temperature coefficient voltage Δv GS+BE,ΔVGS+BE=Va-Vb =i×r1 can be obtained based on the first negative temperature coefficient voltage V a and the second negative temperature coefficient voltage V b, I is the magnitude of the current flowing through the first resistor R1, and then Δv GS+BE and V GS+VBE are superimposed to obtain= (V GS1+VBE1）+α´ΔVGS+BE=（VGS2+VBE2+I*R1）+α´ΔVGS+BE. Thus, the superimposing circuit 12 can output the required bandgap reference voltage/>Band gap reference voltage/>The curve as a function of temperature T is shown in fig. 5.
In addition, by simulation verification of the bandgap reference circuit shown in FIG. 6, a simulation result diagram as shown in FIG. 7, in which the ordinate represents the bandgap reference voltage, can be obtainedThe abscissa represents the temperature T, and the simulation result graph shows the same trend as in fig. 5. Setting the power supply voltage VDD to 3.3V in the simulation condition, carrying out direct current scanning at the temperature of-10 ℃ to 90 ℃ on the circuit, and within the range of-10 ℃ to 90 ℃, obtaining the band gap reference voltage/>The error is 0.4mV at maximum due to fluctuation between 2.61497V and 2.61537V, and the temperature coefficient of the working temperature in the range of-10 ℃ to 90 ℃ is 1.530 ppm/DEG C. When the voltage of the power supply VDD is set to be 3.3V in the simulation condition, the traditional band gap reference circuit is subjected to direct current scanning at the temperature of-10 ℃ to 90 ℃, and the calculated temperature coefficient is usually 25 ppm/DEG C to 30 ppm/DEG C. Obviously, the temperature coefficient of the bandgap reference circuit in the embodiment of the invention is lower than that of the traditional bandgap reference circuit in the same temperature range.
In the embodiment of the invention, the temperature characteristic of the field effect transistor is utilized, the field effect transistor is serially connected with the BJT diode to reconstruct and generate the negative temperature coefficient voltage, and then the negative temperature coefficient voltage is overlapped with the positive temperature coefficient voltage, so that the band gap reference voltage with a lower temperature coefficient can be obtained, and the stability of the band gap reference voltage can be improved.
Alternatively, referring to fig. 6, the superimposing circuit 12 includes a first adjusting circuit 121, a second adjusting circuit 122, and an operational amplifier 123;
the first regulating circuit 121 is connected between the power supply positive electrode VDD and the first fet M1, and the second regulating circuit 122 is connected between the power supply positive electrode VDD and the first resistor R1;
The negative phase input end of the operational amplifier 123 is connected to the first node a, the positive phase input end of the operational amplifier 123 is connected to a third node c between the second regulating circuit 122 and the first resistor R1, and the output end of the operational amplifier 123 is simultaneously connected to the control ends of the first regulating circuit 121 and the second regulating circuit 122;
the operational amplifier 123 controls the voltages of the first node a and the third node c to be the same through the first regulating circuit 121 and the second regulating circuit 122, and outputs the bandgap reference voltage through superposition of the second regulating circuit 122 。
Specifically, as illustrated in fig. 6, in one embodiment, the superimposing circuit 12 may include a first adjusting circuit 121 for adjusting the current magnitude of the first negative temperature coefficient 10, a second adjusting circuit 122 for adjusting the current magnitude of the second negative temperature coefficient 11, and an operational amplifier 123 for controlling the first adjusting circuit 121 and the second adjusting circuit 122.
Specifically, the first field effect transistor M1 is still taken as an NMOS transistor for illustration. The first adjusting circuit 121 is connected between the power supply positive electrode VDD and the drain electrode of the first field effect transistor M1, and the second adjusting circuit 122 is connected between the power supply positive electrode VDD and the first resistor R1.
The negative phase input end of the operational amplifier 123 is connected to the first node a, the positive phase input end of the operational amplifier 123 is connected to the third node c between the second regulating circuit 122 and the first resistor R1, and the output end of the operational amplifier 123 is connected to the control ends of the first regulating circuit 121 and the second regulating circuit 122. The two input terminals of the operational amplifier 123 respectively collect the voltage V a at the first node a and the voltage V c at the third node c, and from the foregoing description, V c=Vb+I*R1=VGS2+VBE2 +i×r1 can be known. V a and V c are compared by an operational amplifier 123, the current levels of the corresponding circuits can be respectively adjusted by a first adjusting circuit 121 and a second adjusting circuit 122 according to the comparison result, thereby the V a and V c are controlled in a feedback manner so that V a and V c are the same, and the second adjusting circuit 122 can superimpose the positive temperature coefficient voltage and the negative temperature coefficient voltage and output a band gap reference voltage。
Optionally, referring to fig. 8, the first adjusting circuit 121 includes a third fet M3 and a second resistor R2 connected in series;
The first field effect tube M1 is connected with the second resistor R2 in series, and the third field effect tube M3 is also connected with the positive electrode VDD of the power supply;
the output end of the operational amplifier 123 is connected to the gate of the third fet M3.
Specifically, as illustrated in fig. 8, the first adjusting circuit 121 in the embodiment of the present invention may include a third fet M3 and a second resistor R2 connected in series. For example, when the third fet M3 is a PMOS transistor, the drain of the first fet M1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the drain of the third fet M3, the source of the third fet M3 is connected to the positive electrode of the power supply, and the output end of the operational amplifier 123 is connected to the gate of the third fet M3. The output end of the operational amplifier 123 controls the working state of the third fet M3 according to the comparison result to adjust the current level on the branch, so as to change the voltage V a of the first node a.
Optionally, referring to fig. 8, the second adjusting circuit 122 includes a fourth fet M4 and a third resistor R3 connected in series;
The first resistor R1 is connected in series with the third resistor R3, the fourth field effect transistor M4 is also connected with the positive electrode VDD of the power supply, and the output end of the operational amplifier 123 is connected with the grid electrode of the fourth field effect transistor M4; the node between the fourth fet M4 and the third resistor R3 is configured to output the bandgap reference voltage.
Specifically, as illustrated in fig. 8, the second adjusting circuit 122 in the embodiment of the present invention may include a fourth fet M4 and a third resistor R3 connected in series. For example, when the fourth fet M4 is a PMOS transistor, one end of the first resistor R1 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to the drain of the fourth fet M4, the source of the fourth fet M4 is connected to the positive power supply, and the output of the operational amplifier 123 is connected to the gate of the fourth fet M4. The output end of the operational amplifier 123 controls the working state of the fourth fet M4 according to the comparison result to adjust the current level on the branch, so as to change the voltage V c of the third node c. And, the node between the fourth FET M4 and the third resistor R3 is used for outputting the band gap reference voltageWith reference to the figures, it will be readily appreciated that/(=V c+ α´ΔVGS+BE=Vc+I*R3=（VGS2+VBE2+I*R1）+R3*ΔVGS+BE/R1, i.e. α″=r3/R1.
Optionally, referring to fig. 9, the operational amplifier 123 includes a first current mirror circuit 1231, a second current mirror circuit 1232, and an operational amplifier control circuit 1233;
The first current mirror circuit 1231 is connected between the power supply positive electrode VDD and the ground terminal GND and is connected to the first node a, and the first current mirror circuit 1231 is configured to mirror the current of the first negative temperature coefficient circuit 10; the second current mirror circuit 1232 is connected between the power supply positive electrode VDD and the ground terminal GND and is connected to the third node c, and the second current mirror circuit 1232 is configured to mirror the current of the second negative temperature coefficient circuit 11; the first current mirror circuit 1231 is further connected to the second current mirror circuit 1232;
the op-amp control circuit 1233 is connected between the power supply positive electrode VDD and the ground terminal GND, and between the second current mirror circuit 1232 and the first and second adjusting circuits 121 and 122, and the op-amp control circuit 1233 is configured to feedback control the first and second adjusting circuits 121 and 122 according to the electrical signals of the first and second current mirror circuits 1231 and 1232, so that the voltages of the first and third nodes a and c are the same.
Specifically, as illustrated in fig. 9, the operational amplifier 123 in the embodiment of the present invention includes a first current mirror circuit 1231, a second current mirror circuit 1232, and an operational amplifier control circuit 1233. The first current mirror circuit 1231 is connected between the power supply positive electrode VDD and the ground terminal GND, and is connected to the first node a, the first current mirror circuit 1231 copies the current mirror of the first negative temperature coefficient circuit 10 into the first current mirror circuit 1231 through the first node a, the second current mirror circuit 1232 copies the current mirror of the first negative temperature coefficient circuit 10 into the second current mirror circuit 1232 through the third node c, and the first current mirror circuit 1231 is also connected to the second current mirror circuit 1232, both of which have the same current portion. The operational amplifier control circuit 1233 is connected between the second current mirror circuit 1232 and the first regulation circuit 121, and is also connected between the second current mirror circuit 1232 and the second regulation circuit 122, and the magnitudes of currents mirrored by the two current mirror circuits can be input into the operational amplifier control circuit 1233, and the operational amplifier control circuit 1233 feedback-controls the first regulation circuit 121 and the second regulation circuit 122 so that the voltages of the first node a and the third node c are the same.
Optionally, referring to fig. 9, the first current mirror circuit 1231 includes a fifth field effect transistor M5, a sixth field effect transistor M6, and a third BJT transistor Q3;
The fifth field effect transistor M5, the sixth field effect transistor M6 and the third BJT transistor Q3 are sequentially connected in series, the fifth field effect transistor M5 is connected with the positive electrode of the power supply, the collector and the base of the third BJT transistor Q3 are grounded, and the gate of the sixth field effect transistor M6 is connected to the first node a.
Specifically, as illustrated in fig. 9, the first current mirror circuit 1231 in the embodiment of the present invention includes a fifth field effect transistor M5, a sixth field effect transistor M6, and a third BJT transistor Q3. The fifth field effect transistor M5 may be a PMOS transistor, and the sixth field effect transistor M6 may be an NMOS transistor. The sixth field effect transistor M6 and the first field effect transistor M1 have the same width to length ratio, and the third BJT transistor Q3 and the first BJT transistor Q1 have the same area.
The source electrode of the fifth field effect transistor M5 is connected with the positive electrode of the power supply, the drain electrode of the fifth field effect transistor M5 is connected with the drain electrode of the sixth field effect transistor M6, the drain electrode of the fifth field effect transistor M5 is connected with the grid electrode of the fifth field effect transistor M5, the source electrode of the sixth field effect transistor M6 is connected with the emitter electrode of the third BJT transistor Q3, the collector electrode and the base electrode of the third BJT transistor Q3 are grounded, and the grid electrode of the sixth field effect transistor M6 is connected to the first node a. Under the mirror image structure of the fifth fet M5, the sixth fet M6 and the third BJT Q3, the currents flowing through the first current mirror circuit 1231 and the first negative temperature coefficient circuit 10 are the same.
Optionally, referring to fig. 9, the second current mirror circuit 1232 includes a ninth field effect transistor M9, a tenth field effect transistor M10, and a fourth BJT transistor Q4;
The ninth field effect transistor M9, the tenth field effect transistor M10 and the fourth BJT transistor Q4 are sequentially connected in series, the ninth field effect transistor M9 is connected with the positive electrode of the power supply, the collector and the base of the fourth BJT transistor Q4 are grounded, and the gate of the tenth field effect transistor M10 is connected to the third node c;
The gate of the fifth fet M5 is connected to the gate of the ninth fet M9.
Specifically, as illustrated in fig. 9, the second current mirror circuit 1232 in the embodiment of the present invention includes a ninth field effect transistor M9, a tenth field effect transistor M10, and a fourth BJT transistor Q4. The ninth field effect transistor M9 may be a PMOS transistor, and the tenth field effect transistor M10 may be an NMOS transistor. The tenth field effect transistor M10 and the first field effect transistor M1 have the same width to length ratio, and the fourth BJT transistor Q4 and the first BJT transistor Q1 have the same area.
The source electrode of the ninth field effect transistor M9 is connected with the positive electrode of the power supply, the drain electrode of the ninth field effect transistor M9 is connected with the drain electrode of the tenth field effect transistor M10, the source electrode of the tenth field effect transistor M10 is connected with the emitter electrode of the fourth BJT transistor Q4, the collector electrode and the base electrode of the fourth BJT transistor Q4 are grounded, and the grid electrode of the tenth field effect transistor M10 is connected to the third node c. The gate of the fifth fet M5 is connected to the gate of the ninth fet M9. Under the mirror image structure of the ninth fet M9, the tenth fet M10, and the fourth BJT Q4, the currents flowing through the second current mirror circuit 1232 and the first negative temperature coefficient circuit 10 are the same.
Optionally, referring to fig. 9, the op-amp control circuit 1233 includes a seventh fet M7 and an eighth fet M8 connected in series;
The seventh fet M7 is further connected to the positive electrode of the power supply, the eighth fet M8 is grounded, and the drain and the gate of the seventh fet M7 are simultaneously connected to the control ends of the first adjusting circuit 121 and the second adjusting circuit 122.
Specifically, as shown in fig. 9, the operational amplifier control circuit 1233 in the embodiment of the present invention includes a seventh fet M7 and an eighth fet M8 connected in series. Illustratively, the seventh field effect transistor M7 may be a PMOS transistor, and the eighth field effect transistor M8 may be an NMOS transistor. The source electrode of the seventh field effect tube M7 is connected with the positive electrode of the power supply, the drain electrode of the seventh field effect tube M7 is connected with the drain electrode of the eighth field effect tube M8, the source electrode of the eighth field effect tube M8 is grounded, and the drain electrode and the grid electrode of the seventh field effect tube M7 are simultaneously connected with the control ends of the first regulating circuit 121 and the second regulating circuit 122. For example, the gates of the third fet M3 and the fourth fet M4 may be connected.
In combination with the illustration, the current flowing through the ninth fet M9 is the same as the current flowing through the first current mirror circuit 1231, and the current flowing through the tenth fet M10 is controlled by the third node c. Therefore, when the currents of the ninth fet M9 and the tenth fet M10 have a difference, the operating states of the eighth fet M8 and the seventh fet M7 can be affected by the gate of the eighth fet M8, and the first adjusting circuit 121 and the second adjusting circuit 122 can be feedback controlled.
Optionally, N second BJT transistors Q2 are connected in parallel, and N second field effect transistors M2 are connected in parallel; wherein N is more than or equal to 2, the width-to-length ratio of the first field effect transistor M1 and the second field effect transistor M2 is the same, and the area of the second BJT transistor Q2 is the same as the area of the first BJT transistor Q1.
Specifically, according to the generation principle of the bandgap reference voltage, when two identical BJT transistors operate under unequal currents, their respective V BE can be used as a negative temperature coefficient voltage, and the difference Δv BE between the V BE corresponding to the two BJT transistors is a positive temperature coefficient voltage. Thus, in one embodiment, two or more second BJT transistors Q2 may be connected in parallel, and two or more second field effect transistors M2 may be connected in parallel, with each second BJT transistor Q2 being connected in series with one second field effect transistor M2, based on the bandgap reference circuit. And the width-to-length ratio of the first field effect transistor M1 and the second field effect transistor M2 is the same, and the area of the second BJT transistor Q2 is the same as the area of the first BJT transistor Q1. Therefore, the current I1 flowing through the first field effect transistor M1 and the first BJT transistor Q1 and the current I2 flowing through the second field effect transistor M2 and the second BJT transistor Q2 are different, and have a N-time relationship, so that the negative temperature coefficient voltages V a and V b can be obtained. Of course, in practice, the positive temperature coefficient voltage can also be constructed by directly selecting field effect transistors with different width-to-length ratios and BJT transistors with different areas.
The embodiment of the invention also provides a chip, which comprises the band gap reference circuit in any embodiment.
Specifically, any of the bandgap reference circuits described above may be applied to various types of chips requiring a reference voltage, such as a/D converter chip, D/a converter chip, or processor chip, and the bandgap reference circuit has a lower temperature coefficient, is more suitable for a wider range of high and low temperature environments, and has higher operational reliability.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
It should be noted that modifications and adaptations to the invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The above describes in detail a bandgap reference circuit and a chip provided by the present invention, and specific examples are applied herein to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the structure and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims (9)

1. A bandgap reference circuit, the bandgap reference circuit comprising: a first negative temperature coefficient circuit (10), a second negative temperature coefficient circuit (11), a first resistor (R1), and a superimposing circuit (12);
The first negative temperature coefficient circuit (10) comprises a first field effect transistor (M1) and a first BJT transistor (Q1) which are connected in series, the second negative temperature coefficient circuit (11) comprises a second field effect transistor (M2) and a second BJT transistor (Q2) which are connected in series, the first resistor (R1) is connected in series with the second field effect transistor (M2), the grid electrode and the drain electrode of the first field effect transistor (M1) are connected, and the grid electrode and the drain electrode of the second field effect transistor (M2) are connected; wherein the first BJT transistor (Q1) and the second BJT transistor (Q2) have different current magnitudes;
The superposition circuit (12) is connected between a power supply positive electrode (VDD) and the first resistor (R1) and between the power supply positive electrode (VDD) and the drain electrode of the first field effect transistor (M1), and the collector electrodes and the base electrodes of the first BJT transistor (Q1) and the second BJT transistor (Q2) are grounded;
A first node (a) between the superimposing circuit (12) and the first field effect transistor (M1) is used for generating a first negative temperature coefficient voltage, a second node (b) between the first resistor (R1) and the second field effect transistor (M2) is used for generating a second negative temperature coefficient voltage, and the superimposing circuit is used for obtaining a positive temperature coefficient voltage according to the first negative temperature coefficient voltage and the second negative temperature coefficient voltage and superimposing and outputting a band gap reference voltage;
the superposition circuit (12) comprises a first regulating circuit (121), a second regulating circuit (122) and an operational amplifier (123);
The first regulating circuit (121) is connected between a power supply positive electrode (VDD) and the first field effect transistor (M1), and the second regulating circuit (122) is connected between the power supply positive electrode (VDD) and the first resistor (R1);
the negative phase input end of the operational amplifier (123) is connected to the first node (a), the positive phase input end of the operational amplifier (123) is connected to a third node (c) between the second regulating circuit (122) and the first resistor (R1), and the output end of the operational amplifier (123) is simultaneously connected to the control ends of the first regulating circuit (121) and the second regulating circuit (122);
The operational amplifier (123) controls the voltages of the first node (a) and the third node (c) to be the same through the first regulating circuit (121) and the second regulating circuit (122), and outputs the band gap reference voltage through superposition of the second regulating circuit (122) ）。
2. The bandgap reference circuit according to claim 1, characterized in that the first regulation circuit (121) comprises a third field effect transistor (M3) and a second resistor (R2) connected in series;
The first field effect tube (M1) is connected with the second resistor (R2) in series, and the third field effect tube (M3) is also connected with a power supply positive electrode (VDD);
The output end of the operational amplifier (123) is connected with the grid electrode of the third field effect transistor (M3).
3. The bandgap reference circuit according to claim 1, characterized in that the second regulation circuit (122) comprises a fourth field effect transistor (M4) and a third resistor (R3) connected in series;
The first resistor (R1) is connected in series with the third resistor (R3), the fourth field effect transistor (M4) is also connected with a power supply positive electrode (VDD), and the output end of the operational amplifier (123) is connected with the grid electrode of the fourth field effect transistor (M4); wherein a node between the fourth field effect transistor (M4) and the third resistor (R3) is configured to output the bandgap reference voltage.
4. The bandgap reference circuit according to claim 1, characterized in that the operational amplifier (123) comprises a first current mirror circuit (1231), a second current mirror circuit (1232) and an operational amplifier control circuit (1233);
the first current mirror circuit (1231) is connected between a power supply positive electrode (VDD) and a ground terminal (GND) and is connected to the first node (a), and the first current mirror circuit (1231) is configured to mirror the current of the first negative temperature coefficient circuit (10); the second current mirror circuit (1232) is connected between the positive electrode (VDD) of the power supply and the ground terminal (GND), and is connected to the third node (c), and the second current mirror circuit (1232) is configured to mirror the current of the second negative temperature coefficient circuit (11); the first current mirror circuit (1231) is also connected to the second current mirror circuit (1232);
The operational amplifier control circuit (1233) is connected between a power supply positive electrode (VDD) and a ground end (GND), and between the second current mirror circuit (1232) and the first adjusting circuit (121) and the second adjusting circuit (122), and the operational amplifier control circuit (1233) is configured to feedback-control the first adjusting circuit (121) and the second adjusting circuit (122) according to an electric signal of the first current mirror circuit (1231) and the second current mirror circuit (1232), so that voltages of the first node (a) and the third node (c) are the same.
5. The bandgap reference circuit according to claim 4, characterized in that the first current mirror circuit (1231) comprises a fifth field effect transistor (M5), a sixth field effect transistor (M6) and a third BJT transistor (Q3);
The fifth field effect transistor (M5), the sixth field effect transistor (M6) and the third BJT transistor (Q3) are sequentially connected in series, the fifth field effect transistor (M5) is connected with the positive electrode of a power supply, the collector and the base of the third BJT transistor (Q3) are grounded, and the grid electrode of the sixth field effect transistor (M6) is connected to the first node (a).
6. The bandgap reference circuit according to claim 5, characterized in that the second current mirror circuit (1232) comprises a ninth field effect transistor (M9), a tenth field effect transistor (M10) and a fourth BJT transistor (Q4);
The ninth field effect transistor (M9), the tenth field effect transistor (M10) and the fourth BJT transistor (Q4) are sequentially connected in series, the ninth field effect transistor (M9) is connected with the positive electrode of a power supply, the collector and the base of the fourth BJT transistor (Q4) are grounded, and the grid electrode of the tenth field effect transistor (M10) is connected to the third node (c);
The grid electrode of the fifth field effect transistor (M5) is connected with the grid electrode of the ninth field effect transistor (M9).
7. The bandgap reference circuit according to claim 6, wherein the op-amp control circuit (1233) comprises a seventh field effect transistor (M7) and an eighth field effect transistor (M8) in series;
The seventh field effect transistor (M7) is also connected with the positive electrode of the power supply, the eighth field effect transistor (M8) is grounded, and the drain electrode and the grid electrode of the seventh field effect transistor (M7) are simultaneously connected with the control ends of the first regulating circuit and the second regulating circuit.
8. The bandgap reference circuit according to claim 1, characterized in that N of said second BJT transistors (Q2) are connected in parallel and N of said second field effect transistors (M2) are connected in parallel; wherein N is more than or equal to 2, the width-to-length ratio of the first field effect transistor (M1) and the second field effect transistor (M2) is the same, and the area of the second BJT transistor (Q2) is the same as the area of the first BJT transistor (Q1).
9. A chip comprising the bandgap reference circuit of any one of claims 1 to 8.
CN202310272301.9A 2023-03-20 2023-03-20 Band gap reference circuit and chip Active CN116301178B (en)

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