TWI592786B - Bandgap reference circuit - Google Patents

Description

Bandgap reference circuit

The present invention relates to a bandgap reference circuit.

The bandgap reference circuit is used to generate accurate output voltage and output current. The output voltage and current generated by the bandgap reference circuit are immune to process, supply, and temperature variations. Therefore, the bandgap reference circuit can be widely used in various analog circuits and digital circuits, which require an accurate reference voltage during operation.

Figure 1 illustrates a conventional bandgap reference circuit 100. Referring to FIG. 1, the bandgap reference circuit 100 includes PMOS transistors M1, M2 and M3, an operational amplifier OP, resistors R1 and R2, and bipolar transistors Q1, Q2 and Q3. When the base current is ignored, the output voltage VOUT of the bandgap reference circuit 100 can be expressed as:

Among them, VEB3 is the emitter-base voltage difference of bipolar transistor Q3, VT is the thermal voltage at room temperature, N is the current density of bipolar transistor Q2 and the current of bipolar transistor Q1. The ratio of density.

As shown in equation (1), adjust the resistance ratio of resistors R2 and R1 Thereafter, the bandgap reference circuit 100 can provide a stable output voltage VOUT having a zero temperature coefficient. The voltage level of the voltage VOUT is about 1.25V, which is close to the electron volt of the energy gap, that is, the 矽 energy gap reference voltage.

However, in order to be widely used in different applications, the bandgap reference circuit may need to output different voltage levels.

One of the objects of the present invention is to provide a bandgap reference circuit for providing a reference current and a reference voltage.

According to an embodiment of the invention, the gap reference circuit includes a first operational amplifier, a second operational amplifier, a first current source, a second current source, a third current source, and a first bipolar transistor. a second bipolar transistor, a first feedback transistor, a first resistor, and a second resistor. The first operational amplifier has a first input, a second input, and a first output. The second operational amplifier has a third input, a fourth input and a second output. The first current source is coupled between a supply power node and the first input of the first operational amplifier. The second current source is coupled between the supply power node and the second input of the first operational amplifier. The third current source is coupled between the supply power node and the third input of the second operational amplifier. The first bipolar transistor has a base having an emitter coupled to the first current source and a collector coupled to a ground node. The second bipolar transistor has a base coupled to the second current source An emitter, and having a collector coupled to the ground node. The first resistor is coupled between the third input of the second operational amplifier and the base of the first bipolar transistor. The first feedback element is coupled between the third current source and the base of the second bipolar transistor, and the first feedback element is controlled by the second output of the second operational amplifier. The second resistor is coupled between the base of the first bipolar transistor and the base of the second bipolar transistor. The fourth input of the second operational amplifier is coupled to one of the first input of the first operational amplifier and the second input of the first operational amplifier.

100‧‧‧Gap reference circuit

200‧‧‧Gap reference circuit

22‧‧‧current source unit

300‧‧‧Gap reference circuit

32‧‧‧current source unit

400‧‧‧Gap reference circuit

42‧‧‧current source unit

500‧‧‧Gap reference circuit

M1, M2, M3, M4‧‧‧ PMOS transistors

MA, MB, MC‧‧‧ feedback transistor

OP‧‧‧Operational Amplifier

OP1, OP2, OP3‧‧‧Operational Amplifier

Q1, Q2, Q3‧‧‧ bipolar transistor

R1, R2, R3, R4‧‧‧ resistance

Figure 1 illustrates a common bandgap reference circuit.

Figure 2 is a circuit diagram showing a bandgap reference circuit incorporating an embodiment of the present invention.

Figure 3 is a circuit diagram showing a bandgap reference circuit incorporating another embodiment of the present invention.

Figure 4 is a circuit diagram showing a bandgap reference circuit incorporating yet another embodiment of the present invention.

Fig. 5 is a circuit diagram showing a bandgap reference circuit in accordance with still another embodiment of the present invention.

Figure 2 shows a bandgap reference in accordance with an embodiment of the present invention. Circuit diagram of the road 200. As shown in FIG. 2, the bandgap reference circuit 200 includes a current source unit 22, an operational amplifier OP1, an operational amplifier OP2, a bipolar transistor Q1, a bipolar transistor Q2, and a feedback transistor MA. , a resistor R1, and a resistor R2.

The current source unit 22 provides a plurality of stable bias currents I1, I2, and I3. In the present embodiment, the current source unit 22 is a current mirror configuration consisting of three PMOS transistors M1, M2 and M3. Referring to FIG. 2, the PMOS transistor M1 has a source coupled to a supply voltage source VDD, has a gate coupled to an output of the operational amplifier OP1, and has a coupling coupled to the operational amplifier OP1. A bungee of an inverting input. The PMOS transistor M2 has a source coupled to the supply voltage source VDD, has a gate coupled to the output of the operational amplifier OP1, and has a non-inverting input coupled to the operational amplifier OP1. And a drain coupled to an inverting input of the operational amplifier OP2. The PMOS transistor M3 has a source coupled to the supply voltage source VDD, has a gate coupled to the output of the operational amplifier OP1, and has a non-inverting input coupled to the operational amplifier OP2. One end of the pole.

The bipolar transistor Q1 has a base coupled to an emitter of the inverting input of the operational amplifier OP1 and a collector coupled to a ground terminal. The bipolar transistor Q2 has a base coupled to the non-inverting input of the operational amplifier OP1 and an emitter coupled to the inverting input of the operational amplifier OP2, and coupled to the ground terminal The episode of the episode.

Referring to FIG. 2, the feedback transistor MA is an NMOS transistor having a drain coupled to the non-inverting input of the operational amplifier OP2 and coupled to a gate of an output of the operational amplifier OP2. And a source coupled to the base of the bipolar transistor Q2. The resistor R1 is coupled between the non-inverting input terminal of the operational amplifier OP2 and the base of the bipolar transistor Q1. The resistor R2 is coupled between the base of the bipolar transistor Q1 and the base of the bipolar transistor Q2.

Referring to FIG. 2, the operational amplifier OP1 and the current source unit 22 constitute a first negative feedback loop such that the input terminal voltages VD1 and VD2 are substantially the same; and the operational amplifier OP2, the feedback transistor MA, and the The current source unit 22 constitutes a second negative feedback loop such that the input voltages VD2 and VD3 are substantially identical.

The gates of the transistors M1, M2, and M3 are coupled to the supply voltage source VDD, and the drains of the transistors M1, M2, and M3 are connected to each other. The voltages are substantially the same, so the current values of the currents I1, I2, and I3 flowing through the PMOS transistors M1, M2, and M3 are proportional to the aspect ratio of the transistor.

Referring to Figure 2, voltages VD1 and VD3 can be expressed as: VD1 = VREF + VEB1 = VD3 = VREF + I3A × R1 (2)

Where VREF is the voltage across the summing node N1, VEB1 is the emitter-base voltage difference of the bipolar transistor Q1, and I3A is the current flowing through the resistor R1.

According to this, the formula (2) can be rearranged into the formula (3):

Since the emitter-base voltage difference of the bipolar transistor Q1 is complementary to the absolute temperature (Complementary To Absolute Temperature Voltage) (ie, the CTAT voltage), the current I3A is the CTAT current.

The base currents of the bipolar transistors Q1 and Q2 are ignored. The voltages VD1 and VD2 can be expressed as: VD1 = VREF + VEB1 = VD2 = VREF + I3B × R2 + VEB2 (4)

Wherein, VEB2 is the emitter-base voltage difference of the bipolar transistor Q2, and I3B is the current flowing through the resistor R2.

Accordingly, equation (4) can be rearranged to equation (5):

Since the voltage difference ΔVBE is proportional to the absolute temperature (ie, the PTAT voltage), the current I3B is the PTAT current.

Referring to Fig. 2, the CTAT current I3A flowing through the resistor R1 and the PTAT current I3B flowing through the resistor R2 are summed over the summing node N1 (ignoring the base currents of the bipolar transistors Q1 and Q2). Therefore, by adjusting the resistance of the resistor R1 and the resistor R2, the bandgap reference circuit 200 can provide a stable output current IREF having a zero temperature coefficient. In addition, the gap reference circuit 200 can also provide a positive temperature by adjusting the resistance of the resistor R1 and the resistor R2. A stable output current IREF with a degree coefficient or a negative temperature coefficient. For example, by reducing the resistance of the resistor R2, the bandgap reference circuit 200 can provide a stable output current IREF having a positive temperature coefficient; by reducing the resistance of the resistor R1, the bandgap reference circuit 200 can A stable output current IREF having a negative temperature coefficient is provided.

In order to replicate the current IREF, a PMOS transistor M4 is added to the current source unit 22. Since the current value of the output current IREF is substantially the same as the current value flowing through the PMOS transistor M3 (when the base current of the bipolar transistor Q1, Q2 and the input current of the operational amplifier OP2 are ignored), the PMOS Transistor M4 provides an output current I4 that is proportional to the aspect ratio of the transistor.

Referring to FIG. 3, a resistor R3 is coupled between the summing node N1 and the ground terminal. Therefore, the stable output voltage VREF is generated on the summing node N1. A resistor R4 is coupled between the drain terminal of the PMOS transistor M4 and the ground terminal, thereby generating another stable output voltage VREF1. In order to make the current I4 more accurate, an operational amplifier OP3 and a return transistor MB are added to FIG. The operational amplifier OP3, the feedback transistor MB and the current source unit 42 form a third negative feedback loop such that the input voltages VD3 and VD4 are substantially identical.

Referring to FIG. 1, the voltage level of the stable output voltage VOUT having a zero temperature coefficient provided by the conventional bandgap reference circuit is about 1.25V. However, the bandgap reference circuit disclosed herein can provide an output voltage having a lower voltage level (e.g., less than 0.6V) because the resistor R4 is directly connected to The ground terminal, and the resistor R2 in FIG. 1 is connected to the ground terminal through the bipolar transistor Q3. In addition, since the voltages VD1, VD2 and VD3 are substantially the same and the gates of the PMOS transistors M1, M2, M3 and M4 are connected to each other, the PMOS transistors M1, M2, M3 and M4 can operate in a saturation region (saturation) The region or linear region provides a proportional current proportional to the aspect ratio of the transistor. Therefore, the bandgap reference circuit 300 can provide an output voltage VREF1 having a wide voltage range. The output voltage VREF1 is between 0V and VDD-VSD, M4 according to the resistance of the resistor R4, wherein VSD, M4 is the source-drain voltage difference of the PMOS transistor M4. That is, the output voltage VREF1 can be very close to the voltage level of the supply voltage source VDD.

Refer to Figure 3. The operational amplifier OP1, the operational amplifier OP2, and the feedback transistor MA are substantially identical by a negative feedback loop such voltages VD1, VD2, and VD3. However, the invention should not be limited thereto. For example, the inverting input of the operational amplifier OP2 can be changed to the received voltage VD1 by receiving the voltage VD2 in FIG. In another embodiment of the invention, the feedback transistor MC can be selected as a PMOS transistor, as shown in FIG. The non-inverting input of the operational amplifier OP2 receives the voltage VD2, and the inverting input of the operational amplifier OP2 receives the voltage VD3. In still another embodiment of the present invention, the non-inverting input of the operational amplifier OP2 receives the voltage VD1 instead of the voltage VD2 shown in FIG. According to a configuration of yet another embodiment, the voltages VD1, VD2, and VD3 will be substantially the same.

The technical content and technical features of the present invention have been disclosed as above, It will be apparent to those skilled in the art that the present invention may be substituted and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

200‧‧‧Gap reference circuit

22‧‧‧current source unit

M1, M2, M3, M4‧‧‧ PMOS transistors

MA‧‧‧Returning transistor

OP1, OP2‧‧‧Operational Amplifier

Q1, Q2‧‧‧ bipolar transistor

R1, R2‧‧‧ resistance

Claims (10)

A gap reference circuit includes: a first operational amplifier having a first input, a second input, and a first output; a second operational amplifier having a third input, a fourth input, and a second a second current source coupled between a supply power node and the first input of the first operational amplifier; a second current source coupled to the supply power node and the first operational amplifier Between the second input; a third current source coupled between the supply power node and the third input of the second operational amplifier; a first bipolar transistor having a base having An emitter coupled to the first current source and having a collector coupled to a ground node; a second bipolar transistor having a base coupled to the second current source An emitter, and a collector coupled to the ground node; a first resistor coupled between the third input of the second operational amplifier and the base of the first bipolar transistor; a first feedback component coupled to the third current source and Between the base of the second bipolar transistor, the first feedback element is controlled by the second output of the second operational amplifier; and a second resistor coupled between the base of the first bipolar transistor and the base of the second bipolar transistor; wherein the fourth input of the second operational amplifier is coupled to the One of the first input of the first operational amplifier and the second input of the first operational amplifier. The gap reference circuit of claim 1 further includes: a third resistor coupled between the base of the first bipolar transistor and the ground node. The energy gap reference circuit of claim 1, further comprising: a fourth current source coupled to the power supply node; wherein the fourth current source is configured to replicate a current flowing through the third current source Current. According to the gap reference circuit of claim 3, the method further includes: a fourth resistor directly connected between the fourth current source and the ground node. The energy gap reference circuit of claim 2, further comprising: a fifth current source coupled to the supply power node; a third operational amplifier having a first coupled to the third current source An input coupled to a second input of the fifth current source, and a first output; a second feedback component coupled to the fifth current source, the second feedback component being coupled to the third operational amplifier Controlled by the first output; and a fifth resistor coupled between the second feedback element and the ground node; Wherein the fifth current source is configured to replicate a current flowing through the third current source. The energy gap reference circuit of claim 3, further comprising: a third operational amplifier having a fifth input coupled to the third current source and coupled to a sixth of the fourth current source An input, and a third output; a second feedback component coupled to the fourth current source, the second feedback component being controlled by the third output of the third operational amplifier; and a fifth resistor, The second feedback component is coupled between the ground node and the ground node. A gap reference circuit according to claim 1, wherein a current flowing through the first feedback element and a current flowing through the first resistor are summed to generate a current flowing through the third current source, And the positive temperature coefficient of the current flowing through the third current source is obtained by reducing the resistance of the second resistor. A gap reference circuit according to claim 1, wherein a current flowing through the first feedback element and a current flowing through the first resistor are summed to generate a current flowing through the third current source, And the negative temperature coefficient of the current flowing through the third current source is obtained by reducing the resistance of the first resistor. A gap reference circuit according to claim 2, wherein a current flowing through the first feedback element and a current flowing through the first resistor are summed to one of the second resistor and the third resistor The crossover point generates a reference voltage, and the positive temperature coefficient of the reference voltage is obtained by reducing the resistance of the second resistor. A gap reference circuit according to claim 2, wherein a current flowing through the first feedback element and a current flowing through the first resistor are summed to one of the second resistor and the third resistor The crossover point generates a reference voltage, and the negative temperature coefficient of the reference voltage is obtained by reducing the resistance of the first resistor.