JP2018165940A - Regulator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify circuit configuration by deleting an error amplifier and further simplify phase compensation.SOLUTION: There are provided: a transistor M3 which is connected between an input terminal 1 and an output terminal 2; a transistor M1 whose gate is connected to a grounding terminal 3 via a reference voltage source 6; a transistor M2 whose gate is connected to the output terminal 2; a resistor R1 which is connected between the gate of the transistor M1 and a source of the transistor M2; a resistor R2 which is connected between a source of the transistor M1 and the gate of the transistor M2; current mirror circuits 7 and 8 which apply a voltage proportional to a drain current of the transistor M1 to a gate of the transistor M3; a current source 4 which is connected between a drain of the transistor M2 and the input terminal 1; and a current source 5 which is connected between the gate of the transistor M3 and the grounding terminal 3.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a series type regulator circuit that controls an output voltage to a constant value without using an error amplifier.

  Conventionally, most series-type regulator circuits for generating an internal power supply of an LSI are circuits using an error amplifier as described in Patent Documents 1 to 3. FIG. 9 shows a conventional regulator circuit. 31 is an input terminal to which the voltage VIN is input, 32 is an output terminal from which the voltage VREG is output, 33 is a ground terminal, 34 is a current source having an I31 current, and 35 is a reference voltage source having a voltage VREF.

  The error amplifier includes differentially connected NMOS transistors M31 and M32, current mirror-connected PMOS transistors M33 and M34 as active loads of the transistors M31 and M32, and a current source connected to a common source of the transistors M31 and M32. NMOS transistor M35. A feedback voltage VFB obtained by dividing the output voltage VREG by the resistors R31 and R32 is input to the gate of the transistor M31, and VREF of the reference voltage source 35 is input to the gate of the transistor M32, so that the feedback voltage VFB and the reference voltage VFB The voltage VREF is compared.

  The NMOS transistor M36 is a transistor that forms a current mirror circuit with the transistor M35 and the NMOS transistor M37, and the current I31 of the current source 34 is mirrored to the transistors M35 and M37. The voltage resulting from the comparison of the feedback voltage VFB and the reference voltage VREF appears at the common drain of the transistors M32 and M34, and controls the gate of the PMOS transistor M38 to determine the amount of current flowing from the input voltage VIN to the load. C31 is a phase compensation capacitor.

となる。 In this regulator circuit, since the gate of the transistor M38 is controlled by the error amplifier (M31 to M35) so that VFB = VREF, the output voltage VREG is

It becomes.

JP 2007-264776 A JP 2007-233657 A JP 2006-318327 A

  However, in the regulator circuit of FIG. 9, when the capacity of the load to which the output voltage VREG is applied is large, as shown in FIG. 10, the amplification part becomes two poles of the error amplifier by the transistors M31 to M35 and the output circuit by the transistor M38. There is a possibility that the phase margin is reduced and oscillation occurs. In addition, since many elements are required in the error amplifier, the circuit scale increases, and the error amplifier cannot easily perform phase compensation when the load increases.

  An object of the present invention is to provide a regulator circuit that can simplify the circuit configuration without using an error amplifier, and can further simplify phase compensation.

In order to achieve the above object, according to a first aspect of the present invention, an output transistor of a first conductivity type connected between an input terminal and an output terminal, and a gate are connected to a ground terminal through a reference voltage source. A first transistor of a first conductivity type, a second transistor of a second conductivity type whose gate is connected to the output terminal, and a connection between the gate of the first transistor and the source of the second transistor. And a voltage proportional to the drain current of the first transistor is applied to the gate of the output transistor. The second resistor is connected between the source of the first transistor and the gate of the second transistor. A current mirror circuit to be applied; a first current source connected between a drain of the second transistor and the input terminal; a gate of the output transistor; and the ground terminal. Characterized in that it comprises a second current source connected between the.
According to a second aspect of the present invention, in the regulator circuit according to the first aspect, the reference voltage source includes a third resistor and a fourth resistor connected in series between the gate of the first transistor and the ground terminal. A second conductivity type fourth transistor having a base connected to a common connection point of the third resistor and the fourth resistor, a collector connected to the gate of the first transistor, and an emitter connected to the ground terminal; It is configured.
According to a third aspect of the present invention, in the regulator circuit according to the first or second aspect, the first transistor is replaced with a first conductivity type bipolar transistor, and the reference voltage is applied to a base of the first conductivity type bipolar transistor. Applied, the collector is connected to the current mirror circuit, the emitter is connected to the output terminal via the second resistor, the second transistor is replaced with a bipolar transistor of the second conductivity type, and the second The base of the conductive bipolar transistor is connected to the output terminal, the emitter is connected to the reference voltage source via the first resistor, and the collector is connected to the input terminal via the first current source. It is characterized by that.
According to a fourth aspect of the present invention, the reference voltage source is one of one or more diodes connected in series, one or more Zener diodes connected in series, and one or more diode connected transistors connected in series. It is characterized by comprising.

  According to the present invention, since an error amplifier is not required, the circuit configuration can be simplified. Further, since the circuit system has one pole, the circuit for phase compensation can be simplified.

1 is a circuit diagram of a regulator circuit according to a first embodiment of the present invention. FIG. 2 is an operation characteristic diagram of the regulator circuit of FIG. 1. It is a circuit diagram of the regulator circuit of 2nd Example of this invention. It is a circuit diagram of the regulator circuit of 3rd Example of this invention. It is a circuit diagram of the regulator circuit of 4th Example of this invention. It is a circuit diagram of the regulator circuit of 5th Example of this invention. It is a circuit diagram of the regulator circuit of 6th Example of this invention. It is a circuit diagram of the regulator circuit of 7th Example of this invention. It is a circuit diagram of the conventional regulator circuit. FIG. 10 is a frequency characteristic diagram around the gain and phase of the conventional regulator circuit of FIG. 9.

<First embodiment>
FIG. 1 shows a regulator circuit of the first embodiment. 1 is an input terminal for inputting voltage VIN, 2 is an output terminal for outputting voltage VREG, 3 is a ground terminal, 4 is a current source having current I1, 5 is a current source having current I2, and 6 is a reference having voltage VREF. Voltage sources 7 and 8 are current mirror circuits.

  M1 is a PMOS transistor, a resistor R2 is connected between the source and the output terminal 2, and a gate is connected to a common connection point of the reference voltage source 6 and the resistor R1. The source of the NMOS transistor M2 is connected to the other end of the resistor R1. The transistor M2 has a gate connected to the output terminal 2 and a drain connected to the input terminal 1 via the current source 4. The current flowing through the drain of the transistor M1 is mirrored by the current mirror circuit 7 and flows into another current mirror circuit 8. M3 is an output PMOS transistor whose source is connected to the input terminal 1 and whose drain is connected to the output terminal 2. The voltage corresponding to the current obtained by subtracting the current I2 of the current source 5 from the output current of the current mirror circuit 8 is M3. Applied to the gate to control the output voltage VREG. C1 is a phase compensation capacitor connected between the gate and drain of the transistor M3.

  In the initial state, when the input voltage VIN is applied, the gate of the transistor M3 is set to the GND potential by the current source 5, but the transistor M3 remains in the OFF state because the input voltage VIN is insufficient. For this reason, the output voltage VREG becomes the GND potential. The transistor M2 is in an OFF state because the output voltage VREG input to the gate is the GND potential.

  In this initial state, since the transistor M2 is OFF, no voltage exceeding the threshold voltage Vth1 of the transistor M1 is applied between the source and gate of the transistor M1, and the transistor M1 also maintains the OFF state. As a result, the current mirror circuits 7 and 8 do not operate.

  Next, when the input power source VIN gradually rises and the source-gate voltage of the transistor M3 approaches the threshold voltage Vth3 of the transistor M3, the transistor M3 gradually shifts to the ON state. As a result, the output voltage VREG becomes substantially equal to the input voltage VIN and continues to rise.

トランジスタＭ１のソース・ゲート間にもそのトランジスタＭ１の閾値電圧Ｖｔｈ１を超える電圧が印加し、そのトランジスタＭ１がＯＮ動作を開始し、これによりカレントミラー回路７、８が動作を開始する。式（２）において、ＶＲ１は電流源４の電流Ｉ１によって抵抗Ｒ１に発生する電圧、Ｖｔｈ２はトランジスタＭ２の閾値電圧である。 When the output voltage VREG reaches the voltage shown in Equation (2),

A voltage exceeding the threshold voltage Vth1 of the transistor M1 is also applied between the source and gate of the transistor M1, and the transistor M1 starts an ON operation, whereby the current mirror circuits 7 and 8 start operating. In Expression (2), VR1 is a voltage generated in the resistor R1 by the current I1 of the current source 4, and Vth2 is a threshold voltage of the transistor M2.

  When the current mirror circuits 7 and 8 operate, the output terminal 2 passes through the gate of the transistor M2, the resistor R1, the gate of the transistor M1, the drain of the transistor M1, the current mirror circuit 7, the current mirror circuit 8, and the gate of the transistor M3. A feedback loop is formed. As a result, the output voltage VREG is controlled to maintain the voltage value shown in the equation (2) corresponding to the reference voltage VREF, and a stable state is obtained. Thereafter, it is maintained as shown in FIG.

  For example, when the output voltage VREG rises because the load is temporarily reduced from a stable output state, the voltage at the upper end of the resistor R2 rises, and accordingly, the source and gate of the transistor M1 rises. The voltage between them increases, and the drain current of the transistor M1 increases. As a result, the current of the current mirror circuits 7 and 8 is increased, the gate voltage of the transistor M3 is increased, and the output voltage VREG is controlled to decrease.

  In parallel, since the gate voltage of the transistor M2 increases, the gate-source voltage of the transistor M2 increases. For this reason, the current flowing through the resistor R1 increases, the voltage drop generated there increases, the source-gate voltage of the transistor M1 further increases, and the current of the transistor M1 increases. As a result, the currents of the current mirror circuits 7 and 8 are further increased, the gate voltage of the transistor M3 is further increased, and the output voltage VREG is further lowered.

  Conversely, when the output voltage VREG drops from a stable output due to a temporary heavy load, the voltage at the upper end of the resistor R2 drops. The voltage between the gates decreases, and the drain current decreases. As a result, the current of the current mirror circuits 7 and 8 is decreased, the gate voltage of the transistor M3 is decreased, and the output voltage VREG is increased.

  In parallel, since the gate voltage of the transistor M2 decreases, the gate-source voltage of the transistor M2 decreases. For this reason, the current flowing through the resistor R1 is reduced, the voltage drop generated there is reduced, the source-gate voltage of the transistor M1 is further reduced, and the current of the transistor M1 is reduced. As a result, the current in the current mirror circuits 7 and 8 is further reduced, the gate voltage of the transistor M3 is further lowered, and the output voltage VREG is further increased.

  In the above, the part performing the amplification operation in the feedback loop is only the path from the gate to the drain of the transistor M3. Therefore, this circuit system has a phase characteristic having only one pole. Thereby, phase compensation can be simplified. That is, phase compensation can be performed only by using a small capacitance for the capacitor C1.

<Second embodiment>
FIG. 3 shows a regulator circuit according to the second embodiment. In this embodiment, the PMOS transistor M1 in the regulator circuit of FIG. 1 is replaced with a PNP transistor Q1, and the NMOS transistor M2 is replaced with an NPN transistor Q2. The operation is the same as that of the regulator circuit of the first embodiment, but there is an advantage that the temperature characteristic of the output voltage VREG can be improved.

となる。一般的に電圧ＶＢＥ２は約０．７Ｖで約−２ｍＶ／℃の温度特性を持つことから、正の温度係数をもつ抵抗Ｒ１に発生する電圧ＶＲ１の温度特性をキャンセルすることができる。トランジスタＱ１においても、抵抗Ｒ２の温度特性をトランジスタＱ１のベース・エミッタ間電圧でキャンセルすることができる。このようにして、ＰＭＯＳトランジスタＭ１やＮＭＯＳトランジスタＭ２を使用する場合よりも、出力電圧ＶＲＥＧの温度変動を抑えることが可能となる。 When the base-emitter voltage of the transistor Q2 is VBE2, the output voltage VREG is

It becomes. Generally, the voltage VBE2 is about 0.7V and has a temperature characteristic of about −2 mV / ° C., so that the temperature characteristic of the voltage VR1 generated in the resistor R1 having a positive temperature coefficient can be canceled. Also in the transistor Q1, the temperature characteristic of the resistor R2 can be canceled by the base-emitter voltage of the transistor Q1. In this way, it is possible to suppress the temperature fluctuation of the output voltage VREG, compared to the case where the PMOS transistor M1 and the NMOS transistor M2 are used.

<Third embodiment>
FIG. 4 shows a regulator circuit of the third embodiment. In the first embodiment, two independent current sources 7 and 8 are used, but when this is difficult, two constant current sources are made from one current source. Here, the current I3 output from one current source 9 is generated using the current mirror circuit composed of NMOS transistors MN4 and M5 and the current mirror circuit composed of PMOS transistors M6 and M7 to generate the current I1 of the current source 4 in FIG. doing. Further, the current I3 output from the current source 9 is generated using the current mirror circuit including the NMOS transistors MN4 and M12 to generate the current I2 of the current source 5 shown in FIG. Here, the current mirror circuit 7 is composed of NMOS transistors M8 and M9, and the current mirror circuit 8 is composed of PMOS transistors M10 and M11.

<Fourth embodiment>
FIG. 5 shows a regulator circuit according to a fourth embodiment. Here, a Zener diode DZ1 is employed as the reference voltage source 6 in the third embodiment shown in FIG. If such a Zener diode DZ1 is used, the circuit scale and the exclusive area can be greatly reduced. Note that a Zener diode may not be able to freely generate a necessary voltage due to the problem of thermal history in an optimal wafer process step. Therefore, a plurality of Zener diodes may be used in series.

ＶＢＥ４はトランジスタＱ４のベース・エミッタ間電圧で、約−２ｍＶ／℃の温度係数を有しているため、正の温度係数を有する抵抗Ｒ１，Ｒ３，Ｒ４の値を適宜設定することで、温度特性をキャンセルした基準電圧ＶＲＥＦを生成することができる。 <Fifth embodiment>
FIG. 6 shows a regulator circuit of the fifth embodiment. Here, as the reference voltage source 6 in the third embodiment shown in FIG. 4, the NPN transistor Q4, resistors R3 and R4, and the current I1 supplied from the constant current source transistor M7 are used to generate the reference voltage VREF. Yes. The reference voltage VREF does not depend on the current I1 of the current source transistor M7 and is expressed by the following equation.

VBE4 is a voltage between the base and emitter of the transistor Q4 and has a temperature coefficient of about −2 mV / ° C. Therefore, by appropriately setting the values of the resistors R1, R3, R4 having positive temperature coefficients, the temperature characteristics Can be generated.

の基準電圧ＶＲＥＦを生成できる。また、正の温度係数を有する抵抗Ｒ１の値を適宜設定することで、温度特性をキャンセルした基準電圧ＶＲＥＦを生成することができる。 <Sixth embodiment>
FIG. 7 shows a regulator circuit of the sixth embodiment. Here, as the reference voltage source 6 in the third embodiment shown in FIG. 4, n (n is an integer of 1 or more) diodes D1 to Dn are connected in series, and the diodes D1 to Dn If the forward voltage is 0.7V,

The reference voltage VREF can be generated. Further, by appropriately setting the value of the resistor R1 having a positive temperature coefficient, it is possible to generate the reference voltage VREF in which the temperature characteristic is canceled.

の基準電圧ＶＲＥＦを生成することができる。なお、ＮＭＯＳトランジスタに替えてＰＭＯＳトランジスタを用いたり、ＰＮＰトランジスタ、ＮＰＮトランジスタを用いても、同様に構成できることは言うまでもない。 <Seventh embodiment>
FIG. 8 shows a regulator circuit according to a seventh embodiment. Here, m (m is an integer of 1 or more) diode-connected NMOS transistors M21 to M2m are used in series connection as the reference voltage source 6 in the third embodiment shown in FIG. When the threshold voltage of the transistors M21 to M2m is Vth,

The reference voltage VREF can be generated. Needless to say, a PMOS transistor may be used instead of the NMOS transistor, or a PNP transistor or an NPN transistor may be used.

<Others>
In the above description, the case where the positive input voltage VIN is input to the input terminal 1 has been described. However, when a negative input voltage is input, each transistor may be replaced with a transistor of the opposite conductivity type. In the claims, the polarity of the transistor is expressed by the first conductivity type or the second conductivity type. The first conductivity type corresponds to one of the PMOS transistor, the PNP transistor, the NMOS transistor, and the NPN transistor, and the second conductivity type. Corresponds to the other. Furthermore, the current mirror circuit described in the claims corresponds to the current mirror circuits 7 and 8.

1: input terminal, 2: output terminal, 3: ground terminal, 4, 5: current source, 6: reference voltage source, 7, 8: current mirror circuit, 9: current source 31: input terminal, 32: output terminal, 33: Ground terminal, 34: Current source

Claims (4)

  A first conductivity type output transistor connected between the input terminal and the output terminal, a first conductivity type first transistor whose gate is connected to the ground terminal via a reference voltage source, and a gate which is the output A second transistor of a second conductivity type connected to a terminal; a first resistor connected between a gate of the first transistor and a source of the second transistor; a source of the first transistor; A second resistor connected between the gates of the two transistors, a current mirror circuit for applying a voltage proportional to the drain current of the first transistor to the gate of the output transistor, the drain of the second transistor, and the input A first current source connected between the terminal and a second current source connected between the gate of the output transistor and the ground terminal. Regulator circuit to be. The regulator circuit according to claim 1,
The reference voltage source includes a third resistor and a fourth resistor connected in series between the gate of the first transistor and the ground terminal, and a base connected to a common connection point of the third resistor and the fourth resistor. And a second conductivity type fourth transistor having a collector connected to the gate of the first transistor and an emitter connected to the ground terminal. The regulator circuit according to claim 1 or 2,
The first transistor is replaced with a first conductivity type bipolar transistor, the reference voltage is applied to a base of the first conductivity type bipolar transistor, the current mirror circuit is connected to a collector, and an emitter is connected to the second resistor. To be connected to the output terminal via
The second transistor is replaced with a second conductivity type bipolar transistor, the base of the second conductivity type bipolar transistor is connected to the output terminal, and the emitter is connected to the reference voltage source via the first resistor, A regulator circuit characterized in that a collector is connected to the input terminal via the first current source.   The reference voltage source is composed of one or more diodes connected in series, one or more Zener diodes connected in series, and one or more diode-connected transistors connected in series. Regulator circuit.

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