JP6864516B2 - Regulator circuit - Google Patents

Description

The present invention relates to a series type regulator circuit that controls an output voltage to a constant value without using an error amplifier.

Conventionally, most of the series type regulator circuits for generating an internal power supply of an LSI are circuits using an error amplifier as described in Patent Documents 1 to 3. FIG. 9 shows a conventional regulator circuit. 31 is an input terminal for input of voltage VIN, 32 is an output terminal for output of voltage VREG, 33 is a ground terminal, 34 is a current source with a current of I31, and 35 is a reference voltage source with a voltage of VREF.

The error amplifier serves as a current source connected to the differentially connected NMOS transistors M31 and M32, the current mirror-connected ProLiant transistors M33 and M34 as active loads of the transistors M31 and M32, and the common source of the transistors M31 and M32. It is composed of the NMOS transistor M35 of the above. The feedback voltage VFB obtained by dividing the output voltage VREG by the resistors R31 and R32 is input to the gate of the transistor M31, and the feedback voltage VFB and the reference voltage VFB are input to the gate of the transistor M32 by the VREF of the reference voltage source 35. The voltage VREF is compared.

The NMOS transistor M36 is a transistor that constitutes a current mirror circuit with the transistors M35 and the NMOS transistors M37, and the current I31 of the current source 34 is mirrored by the transistors M35 and M37. The voltage of the comparison result of the feedback voltage VFB and the reference voltage VREF appears in the common drain of the transistors M32 and M34, controls the gate of the epitaxial transistor M38, and determines the amount of current flowing from the input voltage VIN to the load. C31 is a capacitor for phase compensation.

となる。 Since the gate of the transistor M38 is controlled by the error amplifiers (M31 to M35) so that this regulator circuit has VFB = VREF, the output voltage VREG is set.

Will be.

JP-A-2007-264767 Japanese Unexamined Patent Publication No. 2007-23657 Japanese Unexamined Patent Publication No. 2006-318327

However, in the regulator circuit of FIG. 9, when the capacitance of the load to which the output voltage VREG is applied is large, the amplification points become two poles of the error amplifier by the transistors M31 to M35 and the output circuit by the transistor M38 as shown in FIG. , The phase margin is reduced and there is a risk of oscillation. In addition, many elements are required for the error amplifier, and the circuit scale is increased. Moreover, the error amplifier cannot easily perform phase compensation when the load is increased.

An object of the present invention is to provide a regulator circuit that eliminates the need for an error amplifier, simplifies the circuit configuration, and also simplifies phase compensation.

In order to achieve the above object, the invention according to claim 1 is a first conductive type output transistor connected between an input terminal and an output terminal, and a gate is connected to a ground terminal via a reference voltage source. First conductive type first transistor, second conductive type second transistor whose gate is connected to the output terminal, and connection between the gate of the first transistor and the source of the second transistor. The voltage generated by the generated first resistor, the second resistor connected between the source of the first transistor and the gate of the second transistor, and the output current proportional to the drain current of the first transistor is described. A current mirror circuit applied to the gate of the output transistor, a first current source connected between the drain of the second transistor and the input terminal, and a connection between the gate of the output transistor and the ground terminal. It is characterized by including a second current source.
According to the second aspect of the present invention, in the regulator circuit according to the first aspect, the reference voltage source includes a third resistor and a fourth resistor connected in series between the gate of the first transistor and the ground terminal. A second conductive type fourth transistor in which the base is connected to the common connection point of the third resistor and the fourth resistor, the collector is connected to the gate of the first transistor, and the emitter is connected to the ground terminal. It is characterized by being configured.
According to the third aspect of the present invention, in the regulator circuit according to the first or second aspect, the first transistor is replaced with a first conductive type bipolar transistor, and the reference voltage source is used as a base of the first conductive type bipolar transistor. The current mirror circuit is connected to the collector, the emitter is connected to the output terminal via the second resistor, and the second transistor is replaced with a second conductive bipolar transistor. The base of the second conductive bipolar transistor is connected to the output terminal, the emitter is connected to the reference voltage source via the first resistor, and the collector is connected to the input terminal via the first current source. It is characterized by being made to be done.
According to a fourth aspect of the present invention, in the regulator circuit according to the first aspect, the reference voltage source is one or two or more series-connected diodes, one or two or more series-connected Zener diodes, or one or two or more series. It is characterized in that it is composed of any of the connected diode connection transistors.

According to the present invention, the circuit configuration can be simplified because an error amplifier is not required. Further, since the circuit system has one pole, the circuit for phase compensation can be simplified.

It is a circuit diagram of the regulator circuit of the 1st Example of this invention. It is an operation characteristic diagram of the regulator circuit of FIG. It is a circuit diagram of the regulator circuit of the 2nd Example of this invention. It is a circuit diagram of the regulator circuit of the 3rd Example of this invention. It is a circuit diagram of the regulator circuit of the 4th Example of this invention. It is a circuit diagram of the regulator circuit of the 5th Example of this invention. It is a circuit diagram of the regulator circuit of the 6th Example of this invention. It is a circuit diagram of the regulator circuit of the 7th Example of this invention. It is a circuit diagram of a conventional regulator circuit. 9 is a frequency characteristic diagram of the gain and phase of the conventional regulator circuit of FIG.

<First Example>
FIG. 1 shows the regulator circuit of the first embodiment. 1 is an input terminal for voltage VIN input, 2 is an output terminal for voltage VREG output, 3 is a ground terminal, 4 is a current source with a current of I1, 5 is a current source with a current of I2, and 6 is a reference for voltage with VREF. The voltage sources 7 and 8 are current mirror circuits.

M1 is a epitaxial transistor, a resistor R2 is connected between the source and the output terminal 2, and the gate is connected to a common connection point between the reference voltage source 6 and the resistor R1. The source of the NMOS transistor M2 is connected to the other end of the resistor R1. The gate of the transistor M2 is connected to the output terminal 2, and the drain is connected to the input terminal 1 via the current source 4. The current flowing through the drain of the transistor M1 is mirrored by the current mirror circuit 7 and flows through another current mirror circuit 8. M3 is an output epitaxial transistor in which the source is connected to the input terminal 1 and the drain is connected to the output terminal 2, and the voltage corresponding to the current obtained by subtracting the current I2 of the current source 5 from the output current of the current mirror circuit 8 is obtained. It is applied to the gate to control the output voltage VREG. C1 is a capacitor for phase compensation connected between the gate and drain of the transistor M3.

By the way, in the initial state, when the input voltage VIN is applied, the gate of the transistor M3 becomes the GND potential by the current source 5, but it remains in the OFF state because the input voltage VIN is insufficient. Therefore, the output voltage VREG becomes the GND potential. Further, the transistor M2 is in the OFF state because the output voltage VREG input to the gate is the GND potential.

Since the transistor M2 is OFF in this initial state, a voltage exceeding the threshold voltage Vth1 of the transistor M1 is not applied between the source and gate of the transistor M1, and the transistor M1 also maintains the OFF state. As a result, the current mirror circuits 7 and 8 also do not operate.

Next, when the input power supply VIN gradually rises and the source-gate voltage of the transistor M3 approaches the threshold voltage Vth3 of the transistor M3, the transistor M3 gradually shifts to the ON state. As a result, the output voltage VREG becomes substantially equal to the input voltage VIN and continues to rise.

トランジスタＭ１のソース・ゲート間にもそのトランジスタＭ１の閾値電圧Ｖｔｈ１を超える電圧が印加し、そのトランジスタＭ１がＯＮ動作を開始し、これによりカレントミラー回路７、８が動作を開始する。式（２）において、ＶＲ１は電流源４の電流Ｉ１によって抵抗Ｒ１に発生する電圧、Ｖｔｈ２はトランジスタＭ２の閾値電圧である。 When the output voltage VREG reaches the voltage represented by the equation (2),

A voltage exceeding the threshold voltage Vth1 of the transistor M1 is also applied between the source and gate of the transistor M1, and the transistor M1 starts an ON operation, whereby the current mirror circuits 7 and 8 start an operation. In the formula (2), VR1 is the voltage generated in the resistor R1 by the current I1 of the current source 4, and Vth2 is the threshold voltage of the transistor M2.

When the current mirror circuits 7 and 8 operate, the output terminal 2 passes through the gate of the transistor M2 → the resistor R1 → the gate of the transistor M1 → the drain of the transistor M1 → the current mirror circuit 7 → the current mirror circuit 8 → the gate of the transistor M3. A feedback loop is formed. As a result, the output voltage VREG is controlled to maintain the voltage value represented by the equation (2) corresponding to the reference voltage VREF, and is in a stable state. After that, it is maintained as shown in FIG.

For example, when the output voltage VREG rises from a stable output state when the load temporarily becomes lighter, the voltage at the upper end of the resistor R2 rises, and the source gate of the transistor M1 accompanies this. The voltage between them increases, and the drain current of the transistor M1 increases. As a result, the currents of the current mirror circuits 7 and 8 increase, the gate voltage of the transistor M3 rises, and the output voltage VREG is controlled to decrease.

At the same time, the gate voltage of the transistor M2 rises, so that the gate-source voltage of the transistor M2 increases. Therefore, the current flowing through the resistor R1 increases, the voltage drop generated there increases, the source-gate voltage of the transistor M1 further increases, and the current of the transistor M1 increases. As a result, the currents of the current mirror circuits 7 and 8 are further increased, the gate voltage of the transistor M3 is further increased, and the output voltage VREG is controlled to be further decreased.

On the contrary, when the output voltage VREG temporarily becomes heavier and drops from the state of stable output, the voltage at the upper end of the resistor R2 drops, and the source of the transistor M1 is accompanied by this. The voltage between the gates becomes smaller and the drain current decreases. As a result, the currents of the current mirror circuits 7 and 8 are reduced, the gate voltage of the transistor M3 is lowered, and the output voltage VREG is controlled to be higher.

At the same time, the gate voltage of the transistor M2 drops, so that the gate-source voltage of the transistor M2 becomes smaller. Therefore, the current flowing through the resistor R1 is reduced, the voltage drop generated there is reduced, the source-gate voltage of the transistor M1 is further reduced, and the current of the transistor M1 is reduced. As a result, the currents of the current mirror circuits 7 and 8 are further reduced, the gate voltage of the transistor M3 is further lowered, and the output voltage VREG is controlled to be further higher.

In the above, the portion of the feedback loop that performs the amplification operation is only the path from the gate to the drain of the transistor M3. Therefore, this circuit system has a phase characteristic having only one pole. This makes it possible to simplify the phase compensation. That is, it is possible to perform phase compensation only by using a small capacitance for the capacitor C1.

<Second Example>
FIG. 3 shows the regulator circuit of the second embodiment. In this embodiment, the MIMO transistor M1 in the regulator circuit of FIG. 1 is replaced with the PNP transistor Q1, and the NMOS transistor M2 is replaced with the NPN transistor Q2. The operation is the same as that of the regulator circuit of the first embodiment, but there is an advantage that the temperature characteristic of the output voltage VREG can be improved.

となる。一般的に電圧ＶＢＥ２は約０．７Ｖで約−２ｍＶ／℃の温度特性を持つことから、正の温度係数をもつ抵抗Ｒ１に発生する電圧ＶＲ１の温度特性をキャンセルすることができる。トランジスタＱ１においても、抵抗Ｒ２の温度特性をトランジスタＱ１のベース・エミッタ間電圧でキャンセルすることができる。このようにして、ＰＭＯＳトランジスタＭ１やＮＭＯＳトランジスタＭ２を使用する場合よりも、出力電圧ＶＲＥＧの温度変動を抑えることが可能となる。 Assuming that the base-emitter voltage of transistor Q2 is VBE2, the output voltage VREG is

Will be. Generally, since the voltage VBE2 has a temperature characteristic of about -2 mV / ° C. at about 0.7 V, the temperature characteristic of the voltage VR1 generated in the resistor R1 having a positive temperature coefficient can be canceled. Also in the transistor Q1, the temperature characteristic of the resistor R2 can be canceled by the base-emitter voltage of the transistor Q1. In this way, it is possible to suppress the temperature fluctuation of the output voltage VREG as compared with the case of using the epitaxial transistor M1 and the NMOS transistor M2.

<Third Example>
FIG. 4 shows the regulator circuit of the third embodiment. In the first embodiment, two independent current sources 7 and 8 are used, but when this is difficult, two constant current sources are created from one current source. Here, the current I3 output from one current source 9 is generated from the current I1 of the current source 4 of FIG. 1 by using the current mirror circuit composed of the NMOS transistors MN4 and M5 and the current mirror circuit composed of the MPa transistors M6 and M7. doing. Further, the current I3 output from the current source 9 is generated by the current mirror circuit including the NMOS transistors MN4 and M12 to generate the current I2 of the current source 5 of FIG. Here, the current mirror circuit 7 is composed of the NMOS transistors M8 and M9, and the current mirror circuit 8 is composed of the epitaxial transistors M10 and M11.

<Fourth Example>
FIG. 5 shows the regulator circuit of the fourth embodiment. Here, the Zener diode DZ1 is adopted as the reference voltage source 6 in the third embodiment shown in FIG. If such a Zener diode DZ1 is used, the circuit scale and the occupied area can be significantly reduced. Since the Zener diode may not be able to freely generate the required voltage due to the problem of heat history in the optimum wafer process process, a plurality of Zener diodes may be connected in series and used.

ＶＢＥ４はトランジスタＱ４のベース・エミッタ間電圧で、約−２ｍＶ／℃の温度係数を有しているため、正の温度係数を有する抵抗Ｒ１，Ｒ３，Ｒ４の値を適宜設定することで、温度特性をキャンセルした基準電圧ＶＲＥＦを生成することができる。 <Fifth Example>
FIG. 6 shows the regulator circuit of the fifth embodiment. Here, as the reference voltage source 6 in the third embodiment shown in FIG. 4, the NPN transistor Q4, the resistors R3, R4, and the current I1 supplied from the constant current source transistor M7 are used to generate the reference voltage VREF. There is. The reference voltage VREF does not depend on the current I1 of the current source transistor M7 and is expressed by the following equation.

VBE4 is the base-emitter voltage of transistor Q4 and has a temperature coefficient of about -2 mV / ° C. Therefore, by appropriately setting the values of resistors R1, R3, and R4 having a positive temperature coefficient, the temperature characteristics It is possible to generate a reference voltage VREF that cancels.

の基準電圧ＶＲＥＦを生成できる。また、正の温度係数を有する抵抗Ｒ１の値を適宜設定することで、温度特性をキャンセルした基準電圧ＶＲＥＦを生成することができる。 <Sixth Example>
FIG. 7 shows the regulator circuit of the sixth embodiment. Here, as the reference voltage source 6 in the third embodiment shown in FIG. 4, n diodes D1 to Dn (n is an integer of 1 or more) are connected in series and used, and the diodes D1 to Dn are used. Assuming that the forward voltage is 0.7V,

Can generate a reference voltage VREF. Further, by appropriately setting the value of the resistor R1 having a positive temperature coefficient, it is possible to generate a reference voltage VREF in which the temperature characteristics are canceled.

の基準電圧ＶＲＥＦを生成することができる。なお、ＮＭＯＳトランジスタに替えてＰＭＯＳトランジスタを用いたり、ＰＮＰトランジスタ、ＮＰＮトランジスタを用いても、同様に構成できることは言うまでもない。 <7th Example>
FIG. 8 shows the regulator circuit of the seventh embodiment. Here, as the reference voltage source 6 in the third embodiment shown in FIG. 4, m (m is an integer of 1 or more) diode-connected NMOS transistors M21 to M2m are used by being connected in series. Assuming that the threshold voltage of the transistors M21 to M2m is Vth,

The reference voltage VREF can be generated. Needless to say, the same configuration can be achieved by using a epitaxial transistor instead of an NMOS transistor, or by using a PNP transistor or an NPN transistor.

<Others>
In the above description, the case where the positive input voltage VIN is input to the input terminal 1 has been described, but when the negative input voltage is input, each transistor may be replaced with the opposite conductive type transistor. Further, in the claim, the polarity of the transistor is represented by the first conductive type or the second conductive type, but the first conductive type corresponds to one of the epitaxial transistor and the PNP transistor and the NMOS transistor and the NPN transistor, and the second conductive type. Corresponds to the other. Further, the current mirror circuits according to the claims correspond to the current mirror circuits 7 and 8.

1: Input terminal, 2: Output terminal, 3: Ground terminal, 4, 5: Current source, 6: Reference voltage source, 7, 8: Current mirror circuit, 9: Current source 31: Input terminal, 32: Output terminal, 33: Ground terminal, 34: Current source

Claims (4)

The first conductive type output transistor connected between the input terminal and the output terminal, the first conductive type first transistor in which the gate is connected to the ground terminal via the reference voltage source, and the gate is the output. A second conductive type second transistor connected to a terminal, a first resistor connected between the gate of the first transistor and the source of the second transistor, the source of the first transistor, and the first. A second resistor connected between the gates of the two transistors, a current mirror circuit that applies a voltage generated by an output current proportional to the drain current of the first transistor to the gate of the output transistor, and the second transistor. A regulator circuit including a first current source connected between the drain of the output transistor and the input terminal, and a second current source connected between the gate of the output transistor and the ground terminal. .. In the regulator circuit according to claim 1,
The reference voltage source is connected to a third resistor and a fourth resistor connected in series between the gate of the first transistor and the ground terminal, and a base connected to a common connection point between the third resistor and the fourth resistor. A regulator circuit comprising a second conductive type fourth transistor in which a collector is connected to the gate of the first transistor and an emitter is connected to the ground terminal. In the regulator circuit according to claim 1 or 2.
The first transistor is replaced with a first conductive type bipolar transistor, the voltage of the reference voltage source is applied to the base of the first conductive type bipolar transistor, the current mirror circuit is connected to the collector, and the emitter is the first. It is connected to the output terminal via two resistors.
The second transistor is replaced with a second conductive bipolar transistor, the base of the second conductive bipolar transistor is connected to the output terminal, and the emitter is connected to the reference voltage source via the first resistor. A regulator circuit characterized in that a collector is connected to the input terminal via the first current source. In the regulator circuit according to claim 1,
The reference voltage source is characterized by being composed of either one or two or more series-connected diodes, one or two or more series-connected Zener diodes, or one or two or more series-connected diode-connected transistors. Regulator circuit.

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