JPH04115571A - Master-slice semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a pull-up resistor whose resistance value is variable by a wiring process only by a method wherein the drain diffused regions of one or more P-type channel transistors are electrically connected to an I/O cell. CONSTITUTION:In a basic cell, P-type MOS-FET's 25 and 26 are formed on the parts where a P<+>-type diffused region 21 overlaps polycrystalline silicon layers 23 and 24 which are to be gate electrodes. If a wiring layer is added to the basic cell to utilize it as a P-type channel transistor for a pull-up resistor, the source electrodes 32 of one or more P-type channel transistors among a plurality of the P-type channel transistors whose gate electrodes are fixed to Vss- are fixed to a potential Vdd+. The drain electrodes 33 of one or more P-type channel transistors are connected to an input inverter circuit 13 and an I/O terminal 11 with signal lines 34. With this constitution, a pull-up resistor can be obtained by a wiring process only and its resistance value can be varied if necessary.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a master slice semiconductor integrated circuit that includes:
This is used in the configuration of a pull-up resistor transistor.

[Conventional technology] Conventional master slice semiconductor integrated circuit.

When a pull-up resistor was required, a dedicated type was used, either by attaching a resistor to the outside of the chip, or by using an input/output cell to fix a P-channel transistor as a pull-up resistor transistor.

1. Problems to be Solved by the Invention] However, in the conventional technology described above, when a resistor is attached to the outside of the chip, the wiring around the chip becomes complicated, which reduces the mounting efficiency including the chip, and the number of external parts increases. There was a problem in that this increased the cost. Furthermore, when an input/output cell has a built-in pull-up resistor, since it is a fixed, dedicated type, it requires a chip area even when not in use, and the resistance value is fixed.

The present invention is intended to solve these problems, and its purpose is to provide a master slice semiconductor integrated circuit in which a pull-up resistor can be created only by the wiring process when realizing a dedicated logic circuit using a mask slice type gate array. The purpose is to provide a circuit.

[Means for Solving the Problems] The master slice semiconductor integrated 8f circuit of the present invention has the following features:
a) In a master slice semiconductor integrated circuit formed by arranging a large number of internal logic gate cells (hereinafter referred to as basic cells) in a two-dimensional matrix, b) P channels of input/output cells into which signals from outside the chip are input. C) a P-channel transistor using a basic cell; and d) one or more of the plurality of P-channel transistors whose gate electrodes are fixed to Vss-. The method is characterized in that the sos electrode is fixed at a potential of V d d+, and the drain diffusion region of one or more P-channel transistors and the input/output cell are electrically connected.

[Examples] The present invention will be described in detail below based on Examples.

FIG. 1 shows the structure of a pull-up resistor layer P-channel transistor built into the master slice semiconductor integrated circuit of the present invention.

In FIG. 1, 11 is an input/output terminal, 12 is a pull-up resistance layer P-channel transistor, and 13 is an input inverter circuit. The pull-up resistor layer P-channel transistor 12 is connected to the input/output terminal 11 and the input inverter circuit 1.
Connected to 3. Further, the gate electrode of the pull-up resistor P-channel transistor 12 is connected to Vss-, and the source electrode is connected to Vdd+. Next, a description will be given of means for configuring the pull-up resistor layer P-channel transistor in the master slice semiconductor integrated circuit.

First, FIG. 2 is a diagram showing an example of basic cells, which are internal logic gate cells arranged in an array in a master slice semiconductor integrated circuit. In Figure 2, 23.
24 is an insulated gate field effect transistor (hereinafter MO5
21 is a P+ diffusion, and 22 is an N+ diffusion. 23
．． 24 and P type M at the overlapped part of P + diffusion 21.
OSFETs 25 and 26 are formed. Furthermore, N-type MOSFETs 27 and 28 are formed in the overlapping portions of the polysilicon 23 and 24 and the N+ diffusion 22, respectively.

FIG. 3 shows a case where a wiring layer is added to the basic cell of FIG. 2 and used as a pull-up resistance layer P-channel transistor. In FIG. 3, for simplification, a contact hole connecting polysilicon and aluminum wiring and P;
A contact hole connecting the + diffusion or N0 diffusion and the aluminum wiring is represented by an X mark, and the aluminum wiring taken out from the contact hole is represented by a straight line. Now, the gate electrode of 103FET25 is changed to P type. The source electrode is 32. The drain electrode is 33.

Further, the gate electrode 31, the source electrode and the train electrode of the N-type MO9FET 27 are provided. The sos electrode 32 of the P-type MO3FET 25 is connected to Vdd+, which is the positive power supply potential, and the gate electrode 31 of the P-type MO3FET 25 is connected to Vss-, which is the negative power supply potential.
The drain electrode 33 of the MO3FET 25 is connected to the input inverter circuit and the input/output terminal via a signal 34.

The above configuration constitutes a pull-up resistance layer P-channel transistor circuit.

Figure 4 shows P-type MO3FE by arranging multiple basic cells.
It is a configuration diagram in which four Ts are connected in parallel. FIG. 5 is a circuit diagram of FIG. 4.

If the resistor 51 is 100 kilohms, then the pull amplifier resistance value will be 25 kilohms since it is a quadruple subarray.

Figure 6 shows P-type MO3FE by arranging multiple basic cells.
It is a configuration diagram in which four Ts are connected in series. FIG. 7 is a circuit diagram of FIG. 6.

If the resistor 71 is 100 kilohms, there are four resistors connected in series, so the pull-up resistance value will be 400 kilohms.

Furthermore, although FIG. 2 has been given as an example of a basic cell, the above explanation is not limited to a specific pattern of basic cells and can therefore be applied to other basic cells.

[Effects of the Invention] As described above, according to the master slice semiconductor #-tlcN circuit having the circuit configuration of the present invention, the pull-up resistor is required only in the wiring process when realizing a dedicated logic circuit with a master slice type gate array. There is an effect that can be done. Furthermore, since the resistance value of the pull-up resistor can be varied as necessary, the chip area can be reduced, resulting in an integrated circuit with excellent cost performance.

[Brief explanation of the drawing]

Figure 1 is a P-channel transistor circuit diagram for pull-up resistor, Figure 2 is a pattern diagram of a basic cell, Figure 3,
4 and 6 are configuration diagrams of a pull-up resistor layer P-channel transistor circuit, and FIG. 5 and FIG. 7 are circuit diagrams of the pull-up resistor. 1 ] Input/output terminal P-type MO3FET Input inverter circuit P-diffused N+diffused polysilicon Polysilicon P-type MO3FET P-type MO3FET X-type MO3FET N-type MOS FET Contact hole Contact hole Contact hole Signal resistance Resistance

Claims (1)

[Claims] (1) a) In a master slice semiconductor integrated circuit formed by arranging a large number of internal logic gate cells (hereinafter referred to as basic cells) in a two-dimensional matrix, b) P of an input/output cell into which signals from outside the chip are input.
a channel transistor and an N-channel transistor; c) a P-channel transistor using a basic cell; and d) a plurality of the P-channel transistors with gate electrodes fixed to Vss-.
The source electrode of one or more of the P-channel transistors among the channel transistors is fixed at a potential of Vdd+, and the drain diffusion region of the one or more P-channel transistor is electrically connected to the input/output cell. Master slice semiconductor integrated circuit.