JPH03155669A - Gate array device - Google Patents

Abstract

PURPOSE:To constitute logic circuits having different electrical characteristics in one chip by composing a gate array device of an input-output region, in which input-output cells are arranged, and an internal cell region, in which basic cells are disposed in an array shape, and organizing the internal cell region of (n) kinds of the basic cells. CONSTITUTION:The arrays of basic cells 104 having first characteristics and the arrays of basic cells 105 having second characteristics are divided roughly into upper sections and lower sections and arranged, but mutual cells of adjacent columns (or rows) may have different characteristics or cells having different characteristics may also be disposed at every (m) column (or row) without being limited. When a first logic circuit is constructed of the basic cells having the first characteristics and a second logic circuit is constituted of the basic cells having the second characteristics, it is favorable that each array is divided and arranged. When a logic circuit is organized of a transistor having the first characteristics and a transistor having the second characteristics, however, it is preferable that the basic cells having the first characteristics and the basic cells having the second characteristics are mixed and disposed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of an internal cell region in a gate array device of a one-chip semiconductor integrated circuit.

[Prior Art j] In a conventional gate array device, the internal cell region was composed of one type of basic cell, as shown in FIG.

[Problem to be Solved by the Invention 1] As mentioned above, in the conventional gate array device, the internal cell area is formed from one type of basic cell, so the characteristics of the configured circuit are uniquely determined. It was not possible to configure logic circuits with different characteristics on one chip.

Therefore, the present invention aims to solve the problems of conventional gate array devices, and its purpose is to provide a gate array device that can form one logic circuit with different electrical characteristics in one chip. .

[Means for Solving the Problems 1] A gate array device of the present invention comprises: a) a gate array device for a semiconductor integrated circuit, b) an input/output area where input/output cells are arranged, and c) basic cells arranged in an array. d) The internal cell region has n types (n is a natural number of 2 or more) of basic cells.

〔Example〕

FIG. 1 shows a plan view of a gate array device as a first embodiment of the present invention.

In FIG. 1, 101 is an input/output area, and 103 input/output cells are arranged to interface between the inside of the chip and the outside of the chip. 104 is a basic cell with a first characteristic, and 105 is a basic cell with a second characteristic. Basic cells 104 and basic cells 105 are arranged in an array to form 102 internal cell regions.

Various circuits are constructed using the internal cell area of 102, but due to differences in the characteristics of the basic cells due to differences in threshold voltage, mobility, transistor size, etc. of the transistors that constitute the basic cells 104 and 105, Even if circuits of the same logic are configured in the area where the basic cells 104 are arranged in an array and the area where the basic cells 105 are arranged in an array, the circuits have different capabilities. This difference appears as a difference in characteristics of the logic circuit, such as logic level, delay time, current consumption, and operating voltage. In this way, logic circuits with various characteristics can be created by the configuration of the gate array device consisting of a plurality of types of basic cells as shown in FIG.

In FIG. 1, the array of basic cells 104 having the first characteristic and the array of basic cells 105 having the second characteristic are arranged roughly in the upper and lower parts. The present invention is not limited to the configuration shown in the figure (
, cells in adjacent columns (or rows) may have different characteristics, or cells with different characteristics may be arranged every m columns (or rows). The first characteristic is the basic cell with the first characteristic.
When constructing a logic circuit using basic cells having the second characteristic, it is preferable to arrange each array separately as shown in FIG.
When a logic circuit is configured using transistors having the first characteristic and transistors having the second characteristic, it is preferable to arrange basic cells having the first characteristic and basic cells having the second characteristic in a mixed manner.

[Effect of the Invention J] As described above, according to the present invention, since the internal cell region of the gate array device is constituted by a plurality of types of basic cells, it is possible to configure circuits with various electrical characteristics.

Another advantage is that circuits that were previously constructed from multiple chips can now be constructed from one chip.

101. 102° 103. 104. 105 ・ 01 02 03 04 ・I/O area ・Internal cell area ・Input/output cell ・Base with the first property sick cell ・Base with the second characteristic sick cell that's all

Claims (1)

[Claims] a) A gate array device for a semiconductor integrated circuit, comprising: b) an input/output area where input/output cells are arranged; c) an internal cell area where basic cells are arranged in an array; d ) The gate array device characterized in that the internal cell region has n types of basic cells (n is a natural number of 2 or more).