JPH02284468A - Gate-array type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a high speed and large scale gate array type integrated circuit without increasing the total cell size and power consumption by a method wherein cells whose driving capability is improved are arranged in the arrangement of basic cells into a lattice form or stripe form and the interconnection is changed in accordance with the wiring length. CONSTITUTION:I/O buffers 2 are provided along the circumferential part of a gate array. Bonding pads 4 are provided outside the I/O buffers 2. Basic cells 1 are arranged in the center part into the forms of arrays. Wiring channels 3 are provided between the cells 1 and serve for I/O's between the cells 1 if necessary. A high driving capability cell 6 is a cell composed of an FET whose gate width is designed to be large to improve the wiring driving capability. The high driving capability cells 6 are arranged in the arrangement of the basic cells 1 into a lattice form and the spacings of the lattice are so predetermined as not to change the wiring delay of a GaAs MES-FET so much compared to that of a conventional device and the cell driving capability is changed in accordance with the wiring length. With this constitution, the increase of the total cell size and power consumption can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to gate array type semiconductor integrated circuits, and is particularly applicable to GaAs integrated circuits having thousands or more enemy gates, which increase the chip area. The present invention relates to a gate array type semiconductor integrated circuit that can achieve low power consumption without sacrificing power consumption.

[Semi-required]

The present invention provides a gate array type semiconductor integrated circuit comprising a plurality of basic cells arranged in an array, wherein the basic cells drive transistors constituting the cells, which are arranged at predetermined positions in a predetermined format. It includes multiple high activation capacity cells with increased capacity, and when the wiring length exceeds a certain length, the high drive capacity cells can be used to configure a functional block, thereby eliminating increases in cell size and power consumption. Furthermore, it is possible to obtain a high-speed, large-scale gate array semiconductor integrated circuit.

[Conventional technology]

The electron mobility of GaAs semiconductor is several times faster than that of Sl,
Furthermore, since semi-insulating substrates can be easily obtained,
Parasitic capacitance of the circuit can be reduced when integrating the circuit, and high-speed logic operation is possible. Currently, the mainstream integration of GaAs devices is MESFfET using Schottky junctions, and vigorous research is being carried out in various places with the aim of mass production. Ga
Although some As semiconductor integrated circuits have begun to be commercially available, they are mainly of the SSI and XMSI class, and expectations are high for next-generation developed products such as IK-bit to 4-bit memories and memories with a scale of several thousand gates. . In particular, gate array type semiconductor integrated circuits are in high demand from users because they shorten the time it takes to complete an engineering sample.

As shown in FIG. 4, the structure of the gate array in GaAs devices is similar to that of Si, with input/output huffers 2 arranged around the periphery, basic cells 1 arranged regularly in the center of the chip, and wiring channels 3 It runs in a grid pattern. Basic cell 1 is the basic area for creating gate array functions.
Consists of basic elements such as transistors and resistors,
A function block 5 having useful functions is formed by the basic cell 1 alone or by a collection of basic cells 1. Usually, the functional blocks 5 are prepared in various ways, from simple gates to complex functions such as multiplexers, deniters, flip-flops, and part of ΔLU.

[Problem that the invention seeks to solve]

In the conventional gate array type semiconductor integrated circuit described above, wiring is limited to the wiring channel section running in a grid pattern, so as the gate scale increases, the length of wiring connecting cells increases, resulting in wiring delays. increase In addition, in order to drive wiring at a sufficiently high speed from the beginning of the construction of a gate array type semiconductor integrated circuit, measures such as increasing the gate width of the FET that constitutes the basic cell 1 will increase the cell size itself, which will also increase the overall This results in an increase in wiring length, which has the disadvantage of further increasing power consumption. G
Although the operating speed of an aAs element is sufficiently high compared to that of Sl, as shown in Figure 3, its driving ability is inferior to that of an 81 bipolar device. In this case, the above-mentioned drawbacks become particularly noticeable.

An object of the present invention is to eliminate the above-mentioned drawbacks, thereby achieving a gate array that can reduce power consumption without sacrificing operating speed even in a GaAs gate array type semiconductor integrated circuit having several thousand or more gates. The purpose of this invention is to provide a type semiconductor integrated circuit.

[Means for solving problems]

The present invention provides a gate array type semiconductor integrated circuit including a plurality of basic cells arranged in an array, wherein the basic cells are arranged at predetermined positions in a predetermined format.
It is characterized by including a plurality of high driving capacity cells in which the driving capacity of transistors forming the cells is increased.

[Effect]

When configuring a functional block, if the wiring length is less than a certain length, use a normal basic cell with low power consumption, and if the wiring length is greater than a certain length and wiring delay becomes a problem, use a high drive capacity cell. Use. The wiring length for switching the cell from a normal basic cell to a high drive capacity cell will reduce the increase in power consumption and wiring delay of the entire functional block.
It is determined including the arrangement of high driving capacity cells.

Therefore, it becomes possible to realize a large-scale gate array type semiconductor integrated circuit with lower power consumption and higher speed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a pattern layout diagram showing a first embodiment of the present invention.

In FIG. 1, the input/output cover sofa 2 is arranged at the periphery of the gate array, the bonding pad 4 is further arranged outside the gate array, and the basic cells 1 are arranged in an array in the central part. A wiring channel 3 is provided between the basic cells 1, and a functional block can be configured by connecting human power or output between cells through this channel as necessary. The high driving capacity cells 6, which are characterized by the present invention and in which the gate width of the FET constituting the cell is designed to be large and the wiring driving capacity is increased, are arranged in a lattice shape in the basic cell arrangement.

Now, let us consider a case where a gate array is constructed using GaAs MESFBTs. As shown in Figure 3, when the wiring length is short, it is sufficiently faster than a Si bipolar transistor, but as the wiring becomes longer, the propagation delay increases and the speed becomes slower than that of a Si bipolar transistor. There is a need to. In addition, the FE of the basic cell
If a high-driving-ability cell with increased wiring driving ability by increasing the gate width of T is used as the basic cell of the gate array, the driving ability will improve, as shown by the dashed line in FIG. Cell size increases and power consumption also increases. From the above points, it can be seen that switching the driving capacity of the cell according to the length of the wiring is an effective means. For example, as shown in Figure 3, if the cell drive capacity is switched only at point A and three points, which have relatively long wiring lengths, it is possible to avoid an increase in the overall cell size and power consumption. .

Specifically, as shown in FIG. 1, the high driving capacity cells 6 are arranged in a lattice pattern within the array of ordinary low power consumption basic cells 1, and the intervals between the lattices are as shown in FIG. 3. , GaAsM compared to conventional devices such as S1 bipolar transistors.
Set the length so that the ESFET wiring delay does not change much.

FIG. 2 is a pattern layout diagram showing a second embodiment of the present invention.

In the second embodiment, high driving capacity cells 6 are arranged in a striped pattern. The striped spacing is set at a point where the wiring propagation delay becomes large, as explained in the first embodiment. Even in this case, substantially the same effects as in the first embodiment can be expected, and there is also the advantage that the chip size can be made slightly smaller.

〔Effect of the invention〕

As explained above, the present invention arranges high driving capacity cells with increased wiring driving capacity in an array of basic cells, for example, in a grid pattern or striped pattern, and changes the connection according to the wiring length. This has the effect of suppressing increases in overall cell size and power consumption, and making it possible to obtain a high-speed, large-scale gate array type semiconductor integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a pattern layout diagram showing a first embodiment of the present invention. FIG. 2 is a pattern layout diagram showing a second embodiment of the present invention. Figure 3 shows the S1 bipolar transistor and GaAsMεS
F[ET wiring length versus propagation delay characteristic diagram. FIG. 4 is a pattern layout diagram showing a conventional example. ■...Basic cell, 2...Cover sofa, 3...Wiring channel, 4...Bonding punt, 5...Functional block, 6...High drive capacity cell.

Claims (1)

[Claims] 1. In a gate array type semiconductor integrated circuit comprising a plurality of basic cells arranged in an array, the basic cells include:
1. A gate array type semiconductor integrated circuit comprising a plurality of high drivability cells arranged in a predetermined position in a predetermined format in which the drivability of transistors constituting the cells is increased.