JPH01244642A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device having the excellent efficiency of the usage of gates without preparing multikinds of master slices by cutting the master slice, in which basic cell blocks are arranged to a matrix shape, at a unit containing at least one basic cell block and forming chips. CONSTITUTION:Basic cell blocks in which regions 5 for cutting are shaped around regions 4 for forming input/output pads are arranged to a matrix shape to form a master slice 6, and the master slice 6 is cut at a unit including at least one basic cell block 1 according to the number of gates required, thus shaping chips. Contact holes and input/output cells and input/output pads in a selective manner through a metallic wiring process are formed to the cut chips, thus constituting chips having different gate scale. The cut chips correspond to the number of gates required, thus improving the efficiency of the usage of the gates.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a master slice type semiconductor integrated circuit device.

Conventional technology In the conventional master slice method semiconductor integrated circuit device,
Prepare more than ten types of master slices with different gate sizes,
Each master slice was selected to correspond to different circuit scales.

Problems to be Solved by the Invention However, in this situation, it is possible to reduce the number of unused gates and
In order to increase the efficiency of gate usage, it was necessary to prepare many types of master slices.

The present invention is intended to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a semiconductor integrated circuit device with good gate usage efficiency without having to prepare many types of master slices.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a master slice in which basic cell blocks of a constant gate size are arranged in a matrix, having a cutting area and an input/output pad forming area around the master slice. Chips are formed by cutting into units containing at least one basic cell block.

Furthermore, in the present invention, the input/output pads are formed only in the area adjacent to the part to be actually cut out of the input/output pad forming areas around the plurality of basic cell blocks in the chip.

Effect With the above configuration, by cutting the master slice in an appropriate cutting area according to the required number of gates,
It is now possible to easily configure chips with different gate sizes, eliminating the need to prepare multiple types of master slices as in the past, and since the cut chips correspond to the required number of gates, gate usage efficiency is improved. is in good condition.

Furthermore, by forming input/output pads only in the area adjacent to the part to be actually cut out of the area for forming input/output pads, the area for forming input/output pads where no input/output pads are not formed can be used as an inter-block wiring area. It is possible,
Efficient wiring can be performed.

Example Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a schematic diagram of a semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a schematic diagram of a basic cell block, which is the minimum unit constituting the semiconductor integrated circuit. An example of a slice type semiconductor integrated circuit will be explained.

In FIG. 2, 1 is the minimum unit basic cell block, in which basic cells are arranged in an array across a wiring area 3, and input/output pads are formed around the basic placement area 2 and wiring area 3, which are arranged alternately. A storage area 4 is provided. Then, as shown in FIG. 3, the input/output pad forming area i! ! A master slice 6 is formed by arranging basic cell blocks formed by providing a cutting area 5 around the cell block 114 in a matrix, and this master slice 6 is divided into basic cell blocks 1 according to the required number of gates. Chips are formed by cutting into units containing at least one. For example, if the required gate scale is four times the number of gates provided in basic cell block 1, as shown in FIG. Select 4 of these B ll+ 812. B21.
The cutting area 5 around the basic cell block 1 at the position B22 is cut along the cutting line ρ. That is,
In FIG. 1, a used cutting area 5a of the cutting area 5 is shown.
The unused cutting area 5b between the basic cell blocks 1 is not cut along the line ρ, and in FIG. Input/output pads are formed only in the pad forming area 4a, and the other areas are unused input/output pad forming areas 4b. Similarly, input/output cells are formed only in the input/output cell configuration area 2a of the basic cell arrangement area 2 adjacent to the used input/output pad formation area 4a in which the crowded cabaret is formed, and the input/output cells are formed in the internal macro cell configuration area 2b of the remaining area. Forms an internal macrocell. Then, the basic cell block position B, , B, 2. B2. , B21, the unused pad forming area 4b and the unused cutting area 5b are used as an inter-block wiring area.

In addition, when forming a circuit that can be configured with the number of gates in the minimum unit basic cell block 1, input/output cells are configured with basic cells adjacent to the pad formation area 4,
Pads are formed in all pad forming regions 4, and all cutting regions 5 are cut to obtain a semiconductor integrated circuit device having a structure in which one minimum unit block is included in one chip. When forming a circuit with a larger number of gates than the minimum unit basic cell block 1, cutting is performed so that two block positions B, . . . , 8.2 of the basic cell block positions are included in one chip. If a larger number of gates is required, the basic cell block 1 is cut so that n1xn2 are included in one chip to obtain the required number of gates. In this case, the basic cell block is B1. .

B10..., B1m1, B211..., kt
+...+B m 21...18ml*2 is used. Then, input/output pads are formed along the cut areas to configure input/output cells.

The following method is effective as a method for configuring input/output cells. For example, there is a method in which an input/output protection circuit element, a specially sized transistor necessary for determining an input threshold level, and the like are provided as a dedicated circuit in the pad forming area. In this case, a basic cell transistor adjacent to the pad formation area is used as a transistor that simply realizes logic or buffer capability, and together with the dedicated circuit, the input/output buffer γ is horizontally cleared.

Further, as a method of obtaining a special size transistor for an input/output buffer, there is a method of using a basic cell having a structure as shown in FIG. 4(a).

In this basic cell, the gate width of the general internal basic cell shown in FIG. 4(b) is divided, the number of transistors is doubled to eight, and the gates of NMO8 and PMO8 are separated. For this reason, NMO8, PM in Fig. 4(b)
The circuit can be configured more flexibly in the contact hole and metal wiring process than in the case of a basic cell that is common to OS gates. The gate division ratio is set so that a special size transistor for the input/output buffer can be constructed, and this special size transistor is used when constructing the input/output buffer. When constructing an internal macrocell, the divided gates, sources, or drains are connected through contact holes and metal wiring, and used as a transistor size similar to that shown in FIG. 4(b).

In this way, the basic cell block 1 is cut into units containing one or more cells according to the required number of gates from the same master slice, and the input/output is selectively performed in the cut chips through the contact hole and metal wiring process. By forming cells and input/output pads, chips with different gate sizes can be configured. In addition, since the cut chips correspond to the number of required gates, the gate usage efficiency is good. Since the unused manual pad forming area and the unused cutting area are used as the inter-block wiring area, efficient wiring can be achieved.

As described above, according to the present invention, a master slice in which basic cell blocks of a constant gate size having a cutting area and a capacitor pad forming area around the periphery are arranged in a matrix, and at least one of the basic cell blocks is Since the chips are formed by cutting into units containing the same number of gates, it is possible to construct multiple types of chips depending on the gate scale. Therefore, there is no need to prepare many types of master slices depending on the gate size, and the loss of master slices for one car is reduced. Furthermore, since only the same master slice is manufactured, the chip manufacturing yield is improved due to the mass production effect. Further, fine-grained support for gate scales can be easily achieved by simply creating two or three types of master slices for basic cell blocks with different gate scales.

Furthermore, by forming input/output pads only in the area adjacent to the part to be actually cut out of the GN area for forming input/output pads, the unused area for forming input/output pads can be used as an inter-block wiring area. Enables efficient wiring.

As an additional effect, when combining multiple chips that have already been designed and developed into one chip, the developed mask data can be used as is, and the development period can be shortened because it can be configured only by wiring between the developed chip blocks. The design is highly reliable, with guaranteed characteristics.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an embodiment of the semiconductor integrated circuit device of the present invention, FIG. 2 is a schematic diagram of a basic cell block, which is the minimum unit constituting the semiconductor integrated circuit device, and FIG. 3 is a schematic diagram of the semiconductor integrated circuit device. Schematic diagram of the master slice of the device, Figure 4 (
a) is a transistor level configuration diagram of a basic cell that can configure input/output cells used in the semiconductor integrated circuit;
FIG. 4(b) is a transistor level configuration diagram of a basic CMOS. 1... Basic cell block 52... Basic cell arrangement area, 2a... Input/output cell configuration area, 2b...
... Internal macrocell configuration area, 3... Wiring 9i area, 4
... Input/output pad formation area, 4a... Used input/output pad formation area, 4b... Unused input/output pad formation area, 5... Cutting area, 5a... Used cutting area, 5
b...Unused cutting area, 6...Master slice. Agent Yoshihiro Morimoto 1st Figure R・-・Bage-/7” Shio-772-・-Human Blood Power Tru 4 Arms U8 LB-8 Parts Mafrozel Structure + A 3・- Handout To Ayuuj, rb--・[To Bensho Shimachi 4μ Figure 2

Claims (1)

[Scope of Claims] 1. A master slice in which basic cell blocks of a constant gate size having a cutting area and an input/output pad forming area around the periphery are arranged in a matrix, a unit including at least one basic cell block. A semiconductor integrated circuit device that is cut into chips. 2. The semiconductor integrated circuit device according to claim 1, wherein the input/output pads are formed only in the area adjacent to the portion to be actually cut out of the input/output pad forming areas around the plurality of basic cell blocks.