JPH01152642A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the characteristic of delay time of signal propagation produced owing to capacitance and resistance of a signal wiring by providing logical circuit forming regions, each of which comprises a plurality of rows and columns with use of main power supply buses formed in the shape of a lattice, and providing an assembly cell region including groups of transistors and resistors enough to form each logical circuit. CONSTITUTION:Main power supply buses 2 are provided in the shape of a lattice on one principal surface of a semiconductor chip 1. Logical circuit forming regions are provided, which are partitioned in the form of a matrix with used of the main power supply buses 2. Further, an assembly cell region 3, which includes transistors and resistors for forming the logical circuits, is formed on the center of the logical circuit forming region. And, a signal connecting wiring region 4 of the assembly cell region 3 is formed on the outer periphery of the assembly cell region 3 of the logical circuit forming region. The semiconductor chip 1 is adapted to included on the peripheral edge thereof a power supply and an input/output signal connecting pad 5, further including an output gate element 6 adjoining to the main power supply bus 2 on the inner periphery of the pad 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a master slice type semiconductor integrated circuit.

[Conventional technology]

Conventionally, in this type of master slice type semiconductor integrated circuit, as shown in FIG. An intercell wiring area 8 is provided between the (or columns), power supply and input/output signal connection pads 5 are arranged and provided on the periphery of the semiconductor chip 1, and external wiring is provided in the area between the logic circuit self and the pads 5. Output gate elements 6 are arranged and provided.

[Problem that the invention seeks to solve]

In the conventional semiconductor integrated circuit described above, as the number of mounted cells increases, the power supply wiring for applying voltage to each cell must be made thicker due to restrictions on electrical characteristics, so the cell size becomes smaller. It tended to get bigger. In addition, as the scale of the logic circuits installed increases, the placement of the cells that make up the logic circuits has to cover a wider area, which means that the length of the interconnections between these cells is increasing and the area for forming signal interconnections. This has the disadvantage that the wiring capacity of the signal wiring increases, and furthermore, the wiring resistance increases with miniaturization, and the delay time characteristics deteriorate.

An object of the present invention is to provide a semiconductor integrated circuit that can effectively shorten the length of signal wiring within a semiconductor chip, reduce the dimensions of logic circuit cells, and increase the number of mounted gates.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes a main power supply bus provided in a lattice pattern on one main surface of a semiconductor chip, a logic circuit formation area divided by the main power supply bus and arranged in a matrix, and a center of the logic circuit formation area. an aggregated cell area in which transistors and resistors for forming a logic circuit are arranged; a wiring area for signal connection between the aggregated cell areas provided on the outer periphery of the aggregated cell area of the logic circuit forming area; and the semiconductor chip. The power supply and input/output signal connection pads are arranged on the periphery of the pad, and an output gate element is provided adjacent to the main power supply bus on the inner periphery of the pad.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor chip showing a circuit arrangement according to a first embodiment of the present invention.

As shown in FIG. 1, a main power supply bus 2 arranged in a lattice pattern is provided on one main surface of a semiconductor chip 1, and a logic circuit forming area partitioned into rows and columns by the main power supply bus 2 is provided. An aggregated cell area 3 in which transistors and resistors for forming a logic circuit are arranged is formed in the center of the area, and a signal connection wiring area 4 of the aggregated cell area 3 is formed around the outer periphery of the aggregated cell area 3 of the logic circuit formation area. do. semiconductor chip 1
Power supply and input/output signal connection pads 5 are arranged and provided on the periphery of the pads 5, and output gate elements 6 are arranged and provided adjacent to the main power supply bus 2 on the inner periphery of the pads 5. Here, the output gate element 6 is generally composed of a transistor with a large current capacity and a resistor for driving an external circuit.

In addition, although Fig. 1 shows the case where the main power supply bus 2 is one system, when using two power supplies, the main power supply bus 2
is divided into two systems.

FIG. 2 is a partially cutaway plan view showing a first example of a detailed circuit layout of the logic circuit forming area of FIG. 1. FIG.

As shown in FIG. 2, in the logic circuit forming area partitioned by the main power supply bus 2, logic circuit self cells arranged in, for example, 18 rows are arranged in 19 rows in the column direction. An aggregated cell area 3 provided with a wiring area 8, a wiring area 4 for signal connection provided on the outer periphery of the aggregated cell area 3, and an internal power supply bus 9 connected to the main power supply bus 2 are arranged in nine rows.

FIG. 3 is a plan view showing a second example of the detailed circuit layout of the logic circuit forming area of FIG. 1.

As shown in FIG. 3, cells (hereinafter referred to as functional cells) 10 that satisfy a specific circuit function are appropriately arranged in a logic circuit forming area partitioned by a main power supply bus 2, and power supply to each functional cell 10 is provided. The power supply is connected by an internal power supply bus 9 connected to the main power supply bus 2 in the row or column direction at the shortest distance.

FIG. 4 is a plan view of a semiconductor chip showing the circuit layout of a second embodiment of the present invention.

As shown in Figure 4, the basic configuration is as shown in Figure 1.
However, if the aggregated cell area 11 has an area four times that of the aggregated cell area 3 and the functional circuit cannot be accommodated within the area of the aggregated cell area 3, then the aggregated cell area 3
The aggregate cell area 11 and the aggregate cell area 11 corresponding to four times
A logic circuit forming area consisting of a signal connection wiring area 12 provided on the outer periphery of the area is provided. However, in this case as well, the main power supply bus 2
is laid out in the same way as in the first embodiment.

〔Effect of the invention〕

As explained above, in the present invention, the area excluding the power supply and input/output signal connection pads and output gate elements formed on the peripheral part of the semiconductor chip is connected to a plurality of rows by main power supply buses provided in a lattice shape. By providing logic circuit formation areas divided into columns, each of which has an aggregate cell area having enough transistors and resistor groups to form a logic circuit, and a signal connection wiring area around the outer periphery of the aggregate cell area, The following effects can be obtained.

The first point is that when we look at large-scale LSIs with an equivalent number of gates ranging from several thousand gates to tens of thousands, they are often formed from several to several tens of functional blocks. Furthermore, each functional block has its own characteristics in terms of logical configuration. For example, a circuit that uses a lot of flip-flops, a circuit that uses exclusive logic a lot, or a circuit that consists of only simple gates. In the present invention, a collective cell area is formed in each functional block, and the signal wiring within the functional block is concentrated in one unit area called the collective cell area without being distributed over the entire semiconductor chip in terms of layout. Since the wiring length can be shortened compared to the conventional method, the wiring capacity of the signal wiring,
It is possible to improve signal propagation delay time (tpd) characteristics associated with wiring resistance.

The second point is that a characteristic layout structure corresponding to the functional block can be created for each aggregated cell area. In other words, a functional block that uses many flip-flops can have a layout structure that prioritizes the performance of the flip-flops, and a functional block that uses many exclusive logics can have a layout structure that prioritizes the performance of exclusive logic circuits. It is possible to create a layout structure that prioritizes performance. Or,
The aggregate cell area may be used as one RAM aggregate cell, which has the advantage of improving the circuit performance of each functional block and allowing separate design of each block when developing large chips. .

The third point is that the size of logic circuit cells arranged in an array (generally composed of several AND/NAND gates) can be further reduced in a so-called collective cell region of a gate array configuration. That is, in the conventional case, the width dimension of the internal power supply bus is determined by taking into account the cell columns or cell rows arranged throughout the chip, whereas in the aggregated cell area of the present invention, Since the main power supply bus is arranged, the width of the internal power supply bus is determined by considering the cell columns or cell rows arranged in the collective cell area, so if the current in the cells is the same, Internal power bus width dimensions are reduced. For this reason, the bipolar logic circuit cells, which occupy a large proportion of the cells, are reduced in size, and the number of logic circuit cells that can be accommodated within the same area can be greatly increased.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor chip showing a circuit layout according to a first embodiment of the present invention, and FIG. 2 is a partially cutaway diagram showing a first example of a detailed circuit layout of the logic circuit forming area of FIG. 1. Floor plan, 3rd
The figure is the second detailed circuit layout of the logic circuit formation area in Figure 1.
4 is a plan view of a semiconductor chip showing an example of the circuit layout of a second embodiment of the present invention, and FIG. 5 is a plan view of a semiconductor chip showing an example of the circuit layout of a conventional semiconductor integrated circuit. It is a diagram. l...Semiconductor chip, 2...Main power supply bus, 3...
・Aggregation cell area, 4... Wiring area for signal connection, 5...
・Pad, 6... Gate element, 7... Logic circuit cell, 8... Inter-cell wiring area, 9... Internal power supply bus, 1
o...Functional cell, 11...Aggregation cell area, 12...
・Wiring area for signal connections.

Claims (1)

[Claims] A main power supply bus provided in a lattice shape on one main surface of a semiconductor chip, a logic circuit formation area partitioned by the main power supply bus and arranged in a matrix, and a logic circuit formation area provided in the center of the logic circuit formation area for forming a logic circuit. an aggregated cell area in which transistors and resistors are arranged; a wiring area for signal connection between the aggregated cell areas provided on the outer periphery of the aggregated cell area in the logic circuit formation area; and a wiring area arranged at the periphery of the semiconductor chip. What is claimed is: 1. A semiconductor integrated circuit comprising: a power supply and input/output signal connection pad; and an output gate element provided adjacent to the main power supply bus on the inner periphery of the pad.