JPS59132144A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten and facilitate the wiring between variable length cells, by providing an arrangement improving process, by which the variable length cells are exchanged and arranged when the areas of the cells are different. CONSTITUTION:The areas of all variable length cells other than basic variable length cell are the integer times the area of the variable length cell. The variable length cell 3B has the area twice the basic variable length cell 3A. The variable length cell 3A and a variable length cell 3C in the vicinity thereof are combined so that the area becomes equal to the area of the variable cell 3B. The variable length cells 3A and 3B are exchanged and arranged. In this way, the restriction of the arranging pattern of the variable length cells can be eased, and the wiring between the variable length cells is shortened and facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a large-scale integrated circuit (LSI).
'16 engineering integration)), very large scale integrated circuit [VLEI engineering (vB1r7 Large 5ca
The present invention relates to improvements in the manufacturing method of semiconductor integrated circuit devices such as LE Engineering, 1 On).

2. Description of the Related Art Demand for semiconductor integrated circuit devices, which can be constructed by arranging basic cells each consisting of a plurality of semiconductor elements on a semiconductor substrate, has been increasing in recent years. In order to meet this demand, or to meet the needs of those who want to meet the demand, the adoption of the mask slicing method has become commonplace. Semiconductor integrated circuit devices that use the mask slicing method use an automatic design system (nesign Auto) to design their patterns.
Matton). Is this a basic cell by logical design rules? It consists of a placement process for placement on a semiconductor substrate and a wiring process for connecting seven basic cells. Further, the placement process consists of an initial placement process in which basic cells are placed according to logical design rules, and a placement improvement process for further optimization. Detailed information regarding these is provided below.

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OM, Farua'IaI "Automatic Design of Digital Computers" Industrial Book In the above-mentioned layout improvement process, if all basic cells have the same area, predetermined basic cells should be completely exchanged and placed with each other for optimization. It was possible. A semiconductor integrated circuit device in which all the basic cells have the same area has the advantage that there are fewer restrictions on the arrangement form of the basic cells due to the arrangement improvement process, as described above.

However, when constructing a complete logic circuit with a large function, it must be constructed by combining multiple basic circuits with the same area, and the wiring for the connections becomes complicated, and the area occupied by the wiring increases. This has the disadvantage that the degree of integration of the semiconductor integrated circuit device is reduced.

For this reason, variable length cells have come to be used, each having a different basic cell area depending on its logical function. However, in a semiconductor integrated circuit device made up of variable length cells, the arrangement cannot be exchanged unless the variable length cells have the same area in the arrangement improvement process.

Therefore, it is not possible to achieve sufficient optimization through the placement improvement process, which limits the arrangement form of variable-length cells, and the disadvantages are that the wiring that connects variable-length cells becomes sloppy. Ta.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can alleviate restrictions on the arrangement form of variable-length cells arranged on a semiconductor substrate and facilitate wiring between variable-length cells. It is in.

Hereinafter, the present invention will be described in detail along with one embodiment.

In all the figures, those having similar functions are given the same reference numerals, and repeated explanations will be omitted.

FIG. 1 relates to the present invention and shows a schematic diagram of a semiconductor integrated circuit device.

In FIG. 1, reference numeral 1 denotes a semiconductor integrated circuit device constituted by a semiconductor substrate 2, and is equipped with logic functions and the like. Numeral 3 is a plurality of variable length cells arranged in the central part of the semiconductor substrate 2, each having a predetermined logic function, and the area of the variable length cells varies depending on the logic function. . A plurality of variable length cells 3 are arranged adjacent to each other in the horizontal direction to form a cell column with a -1 inclination 2, and the plurality of cell columns are arranged in rows in the vertical direction via respective wiring areas. . This allows integrated circuits such as logic functions to be constructed. Reference numeral 4 denotes an external terminal (ponding pad) provided on the periphery of the semiconductor substrate 2, for transmitting and receiving signals from the outside to the integrated circuit of the semiconductor integrated circuit device 1, or vice versa. belongs to. At the periphery of the 5-piece external terminal 4, connect the external terminal 4 and the front W.
e This is a buffer circuit provided between the integrated circuits, and is probably used to control the signal level from the external terminal 4 to the integrated circuit, or vice versa. 1 is a diagram illustrating a schematic diagram of a main part of an example variable length cell according to the invention; FIG. In addition, in this example, 0MO8 (Oomplemental7 Metal
0Xide se'mtcona -uctor
) will be explained using a variable length cell.

In FIG. 2, 3A is a variable length cell with the minimum area (hereinafter referred to as a basic variable length cell) provided in the semiconductor integrated circuit device 1.
In this case, a three-person NAND circuit is constructed. Reference numeral 6 denotes an n-type part which is a part of the semiconductor substrate l located on the upper part of the basic variable length cell 3A. This is a ycp type part (p-Well) provided on the semiconductor substrate l below the seven basic variable length cells 3A. 8A, 8B
Gate 1 electrodes b and 8C are provided on the n53 part 6 and the p-type part 7 of the basic variable length cell 3A, and are made of polycrystalline silicon and have electrical conductivity. 9ke game
They are provided in the n-type portions 6 on both sides of the gate electrodes 8A, 8B, and 80, and are p+ type semiconductor regions having conductivity. IO is gate voltage 8ii8A.

8B, 7'Cn provided in the R-shaped part 7 on both sides of 8a
It is a + type semiconductor region and has am conductivity. By applying a voltage to the gate electrodes ftjsA, sB, 80Fi, the gate electrodes 8A, gB,
*n through the gate insulating film (not shown) below 80
W part 6. Inversion layer (channel region) near the surface of p-type part 7
5, conduction is established between the semiconductor regions 9 and 1G on both sides of the gate electrodes sA, BB, and Bc. 11 is a contact hole cI for gate electrodes 8A, +3E, 8Q
These wirings are connected to each other and are for applying voltage to the gate electrodes 8A, 8B, and 8G. 12 is a V provided at a predetermined portion on the basic variable length cell 3A. . Wiring required, operating voltage V. This is for applying 0. The VOA wiring 12' is connected to a predetermined semiconductor region 9.
and is connected through a contact hole c2. Reference numeral 13 is an fcGND wiring provided at another predetermined portion on the basic variable length cell 3A, to which a ground potential can be applied. The GND wiring 13 is connected to a predetermined semiconductor region 10 through a contact hole c2. 14 is a wiring connected to the central part of the gate electrode 8A through a contact hole C1, and 6D is for transmitting a signal from another variable length cell (not shown) to the gate electrode 8A. be. 1
Reference numeral 5 denotes a wiring that connects a predetermined semiconductor region 9 and a predetermined semiconductor region 10 through a contact hole c2, and transmits a signal from the basic variable length cell 3A to other variable length cells through a wire t5A. It is for the purpose of

In FIG. 3, 3B is an example of a variable length cell provided in a semiconductor integrated circuit device @i, and this variable length cell 3B is configured to constitute a two-man EXNOR circuit. The areas of the variable length cells other than the basic variable length cell 3A are all integral multiples of the area of the basic variable length cell 3A, and this variable length cell 3B has an area twice that of the basic variable length cell 3A. It's happening.

8D to 8th are gate electrodes. A wiring 16 is connected to the gate electrode 8 through 8H and a contact hole cI, and is for connecting between the gate electrodes 8E and 8B. 17 is Gate Electric! 8th floor, 8th floor and contact hole O.

This is a wiring that can be connected by connecting the gate electrode 8F and 8 wires. 18
It is a wiring that is connected to the semiconductor region 9, 10 and the contact hole C2, and is connected to the central part of the gate electrode 8G and the contact hole cI, and is used to connect them. . Reference numeral 19 denotes a wiring which is connected to a predetermined semiconductor region 10 through a contact hole 02, and is used to connect these semiconductor heads 10.

Next, a manufacturing method according to an embodiment of the present invention will be described.

4 to 6 are schematic diagrams of main parts of a semiconductor integrated circuit device in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention.

As shown in the manufacturing process of FIG. 4, an initial placement process of variable length cells is performed according to logic design rules. Through this initial arrangement step, variable length cells 3B are arranged at predetermined positions in the cell row 20, and variable length cells 3A having different cell areas are arranged at predetermined positions in the cell row 21. The output signal of the variable length cell 3A is required to be input to the terminal 22, and the output signal of the variable length cell 3B is
There is a desire to input the output signal to the terminal 23. These terminals 22 and -23 may be considered, for example, as terminals for inputting to other variable length cells or as terminals connected to external terminals. The wiring route for which p is predicted according to the above request is shown by a dotted line. According to Kone, each variable length cell 3
The wiring paths from A and 3B may become long, and a portion with high wiring density may occur in a predetermined portion of the wiring area.

For this purpose, as shown in the manufacturing process of FIG. 5, the variable length cell 3A is
A placement improvement process is performed in which the variable length cells 3A and 3B are combined and the variable length cells 3C around them are exchanged with each other.

After the manufacturing process shown in FIG. 5, a wiring process is performed to connect each variable length cell 3A, 3B and each terminal 22, 23, as shown in the construction process shown in FIG. , wirings 24 and 25 are formed. The variable length cell 3A and the variable length cell 3c may or may not be connected in a logical manner.

It should be noted that the present invention is not limited to the embodiments described above, and can of course be modified in various ways without changing the gist thereof.

As explained above, according to the present invention, in the manufacturing process of a semiconductor integrated circuit device consisting of variable length cells, one variable length cell with a large area is made to have the same area as the other small variable length cell. By combining peripheral variable length cells, it is possible to carry out an arrangement improvement process in which variable length cells are exchanged and arranged in cases where the cell areas are different.

Therefore, restrictions on the arrangement of variable length cells can be relaxed, and wiring between variable length cells can be shortened and easily made. As a result, it is possible to reduce unwired automatic wiring by the automatic installation system and to reduce additional wiring work due to unwired wiring.

Furthermore, the power distribution improvement process significantly shortens the wiring, reducing the resistance and capacitance of the wiring, thereby reducing wiring delay speed and improving the operating speed of semiconductor integrated circuit devices. .

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a semiconductor integrated circuit device according to the present invention, FIGS. 2 and 3 are schematic diagrams of main parts of an example of a variable length cell according to the present invention, and FIGS. 4 to 6 are: FIG. 2 is a schematic diagram of a main part of a semiconductor integrated circuit device at each configuration step for explaining a configuration method according to an embodiment of the present invention. In the figure, ]...Semiconductor integrated circuit device, 2...Semiconductor substrate, 3, 3A, 3B, 30...Variable length cell, 4...
External terminal, 5... Buffer circuit, 6... N-type part, 7
... p-type part, 9. IO...Semiconductor area, 8A-8...Gate electrode, 11.14-19, 24.25...
・Wiring, 12-V. Wiring, 13.GND wiring, 20.
21... Cell column, 22.23... Terminal. Agent Patent Attorney Akira Takahashi and 5) Figure 1 Figure 24 Figure 2

Claims (1)

[Scope of Claims] 1. In a method for manufacturing a semiconductor integrated circuit device including a plurality of variable length cells having 8t different surfaces depending on logic functions, the variable length cells are formed into a semiconductor integrated circuit device according to logic design rules. a step of arranging variable length cells of predetermined different areas in order to further optimize the arranged variable length cells; and a step of wiring each of the variable length cells. To be made of 'kIv! ! A fJjJ fabrication method for a semiconductor integrated circuit device. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of replacing and arranging variable length cells with different areas includes one variable length cell with a small area and a variable length cell with a peripheral area thereof. A method for manufacturing a semiconductor integrated circuit device, in which a long cell is combined with a variable length cell to have the same area as another variable length cell having a larger area, and both variable length cells are arranged interchangeably. 3. Range of percentage allowance The method for manufacturing a semiconductor integrated circuit device according to item 1, wherein each of the variable length cells having different areas has a variable length cell area that is at least an integral multiple of the variable length cell having the smallest area. A method of manufacturing a semiconductor integrated circuit device having luxurious features.