JPH0434307B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a large-scale integrated circuit having a multilayer wiring structure, and particularly to a pattern layout of power wiring in a master slice method.

As shown in the chip pattern diagram shown in FIG. 1, the master slicing method uses a power pad 2 with the highest potential (hereinafter referred to as V _CC ) and the lowest potential (hereinafter referred to as V _ee ) provided near the center of the opposing sides of the semiconductor substrate 1 . The power supply pad 3 is alternately connected to an internal region 4 called "cells" in which blocks, which can constitute at least a basic logic circuit by wiring between semiconductor elements formed in advance on the semiconductor substrate 1, are arranged in a matrix. It has a configuration in which a V _CC power supply wiring pattern 5 and a V _ee power supply wiring pattern 6 are wired in parallel to the cells, and the cells are connected via a standardized wiring area called a "wiring channel", and further input An input/output pad 7 arranged around the semiconductor substrate 1 via an output circuit
This is a method to obtain the desired electrical circuit by wiring the cell, but in particular the circuit configured by the cell is
When using ECL (Emitter Coupled Logic), large errors tend to occur in the output voltage of the circuit due to the wiring resistance of the power supply wirings 5 and 6 at the ends of the power supply wirings 5 and 6 routed from the power supply pads 2 and 3. .

That is, in the basic ECL circuit shown in FIG. 2, transistors T1, T2, and T3 have the same shape, and collector resistors R _C1 and R _C2 connected from the collectors of transistors T1 and T2 are V as shown in FIG. It is connected to the V _CC power supply pad 2 via the wiring resistance r _c of the _CC power supply wiring 5, and the emitter resistor R _E3 connected to the emitter of the transistor T3 is connected to the Vee power supply wiring 6 shown in FIG.
The base terminal B1 of the transistor T1 is a signal input terminal, the base terminal B2 of the transistor T2 is a reference input terminal, and the base terminal B3 of the transistor T3 is connected to the Vee power supply pad 3 via a wiring _resistance r e. teeth
These are terminals into which a constant voltage that drives the ECL circuit is input, and the respective base terminal voltages are expressed as V _B1 , V _B2 , and V _B3 .

Now when we pay attention to the output voltage output from collector terminal C2 of transistor T2, the output voltage V _L
If the voltage between B and E of T3 is set as V _F(T3) , then V _B1 < V _B2
When Vee is set to 0v, it can be expressed as V _L = V _CC - (r _c + R _C2 ) x {V _B3 - _{V F(T3)} )}/( _re + R _E3 )...

As a concrete example, V _CC =5v, V _B3 =1.3v, V _F(T3) is
800mv at 1mA, R _C1 = R _C2 = R _E3 = 500Ω, or
When r _c = 100Ω, V _L ≒ 4.5 V when r _c = r _e = 0 Ω, but due to the influence of wiring resistance, V _L ≒
The output voltage increased to 4.575v and 75mv.

The conventional method was to reduce the potential fluctuation of the power supply by increasing the thickness of the power supply wiring and reducing the wiring resistance of the power supply wiring, but increasing the thickness of the wiring requires a process change. This method has the disadvantage of complicating the method and lowering the yield, and there is a limit to the increase in wiring film thickness.Furthermore, this method does not fundamentally prevent potential fluctuations, so large-scale integration is progressing. As time went on, the drawback was that it became impossible to prevent fluctuations in the potential of the power supply.

Furthermore, in the conventional method, the increase due to the wiring resistance of the power supply can be compensated for by changing the resistance value of the collector resistor R _C and emitter resistor R _{E prepared in advance inside the cell (for example, by changing the resistance value of the collector resistor R C and the emitter resistor R E} prepared in advance by contacting the resistor ) by moving the position of
Absorb the increase in the power supply wiring resistance (that is, in the equation, the Vee side resistance is the emitter resistance value R _E3
By changing the value of R _E3 to the value of R E3 −r _e , the value of R _E3 is set, and the V _CC side resistance changes the collector resistance value R _C2 to the value of R _C2 − r _c
The output voltage value V _L was kept constant by changing the value to the value R _C2 ), but this method has the advantage of the master slicing method of designing a large variety of products in small quantities in a short time using DA processing. The disadvantage was that it would result in damage and that it would take time to design. Furthermore, the conventional method is to change the resistance value of the collector resistor R C and the resistance value of the emitter resistor R _E in order to keep the ratio of the terms (r _c + R _C2 ) and ( _re + R _E3 ) constant in the _equation . However, like the conventional example described above, it had the disadvantage that it took a long time to design.

The purpose of the present invention is to make it possible to expect the output of highly accurate logic circuits using conventional processes and pattern layouts, and to take advantage of the advantages of master slicing.
The purpose of the present invention is to provide a semiconductor device that can be designed in a short time with a wide variety of products in small quantities using DA processing.

The present invention provides that the uppermost layer wiring pattern of a semiconductor substrate having a multilayer wiring structure includes a bonding pad pattern arranged around the semiconductor substrate and a pattern divided into two parts in an internal region of the semiconductor substrate surrounded by the pad pattern, Each of the two divided patterns is electrically connected to any of the bonding pad patterns.

Embodiments of the present invention will be described in detail below with reference to the drawings.

3 and 4 are _a series of diagrams for explaining an embodiment of the present invention.
The Vee power supply pad 13 and the V _CC power supply wiring patterns 15 and Vee power supply wiring patterns 16, which are alternately arranged in parallel on the internal region 14 in which cells are arranged in a matrix, have an independent pattern configuration. , is a master slice type chip pattern diagram in which wires are wired between the cells and from the cells via input/output circuits to input/output pads 17 arranged around the semiconductor substrate 11, and the chip has an insulating film covering the surface. It has openings 18 on the power supply pads 12 and 13, on the input/output pad 17, and on the center of the power supply wirings 15 and 16.

FIG. 4 shows a wiring pattern that covers the opening 18 provided on the semiconductor substrate 11 shown in FIG. The wiring patterns 25 and 26 correspond to the positions of the power supply pads 12 and 13 and the input/output pad 17 shown in the figure, and are divided into two parts in the internal area surrounded by the pads 12, 13 and 17. The pattern 25 connects the V _CC power wiring pattern 15 and the V _CC power pad 22 through the opening 18 provided on the V _CC power wiring 15 shown in FIG.
is connected to the Vee power supply wiring pattern 16 through the opening 18 provided on the Vee power supply wiring 16 shown in FIG.
Since the Vee power supply pad 23 is electrically connected, the ECL circuit composed of cells has the same supply position of V _CC and Vee to the ECL circuit at any cell position. When the widths of the Vcc wiring 15 and the Vee wiring 16 shown are the same,
The wiring resistance shown in Figure 2 is r _e = r _c , so in the equation, the output voltage V _L is V _L = V _CC −{V _B3 −
V _F(T3) }, and when inputting the numerical values shown in the specific example,
V _L ≒4.5v, and the calculated value is output.

Generally, in the ECL circuit shown in Figure 2, when the circuit configuration is designed with a ratio of collector resistors R _C1 and R _C2 and emitter resistor R _E3 of 1:k, R _E3 = k・R _C2 . The output voltage value V _L is calculated from the formula V _L = V _CC − (r _c + R _C2 ) × {V _B3 − _{V F(T3)} }/( _re + k・R _C2 ) because it holds true. If the ratio of the wiring width of the V _CC power wiring 15 and the wiring width of the Vee power wiring 16 in FIG. 3 is set to 1:1/k, the wiring resistance r _c and r _e of the power wiring will be r _e =k.・The relationship r _c is established, so the output voltage value V _L is V _L = V _CC − {V _B3 − V _F(T3) }, and the value as designed is output, so that sufficiently satisfactory circuit characteristics are obtained. Furthermore, since the pattern layout can specify the wiring width without waste, the chip size can be reduced.

The wiring pattern shown in FIG. 4 has one additional step compared to the conventional example, but if the wiring pattern sufficiently covers the opening 18 shown in FIG. 3, the design margin can be improved. Since a loose margin system suitable for the process can be created, the decrease in yield due to the addition of one process can be almost ignored.Furthermore, the potential fluctuation at the end of the power supply wiring due to the wiring resistance of the power supply wiring is less than half that of the conventional example, and the chip Even if the power supply pad is provided at an arbitrary position according to the mounting case, if the present invention is used as in the above embodiment, a semiconductor device with sufficiently satisfactory characteristics can be designed in a short time.

According to the present invention, it is possible to obtain a circuit function that is sufficiently satisfactory even with respect to variations in the layer resistance of wiring and potential fluctuations due to wiring resistance of power supply wiring, so it is expected to improve yields, and furthermore, it is possible to improve the miniaturization of semiconductor elements. As integration progresses, power consumption increases,
Therefore, it is accompanied by significant potential fluctuations, especially in the power supply, but according to the present invention, sufficiently satisfactory characteristics can be obtained, and furthermore, the wiring width of the power supply wiring can be suppressed, so the chip size can be reduced, and it is highly anticipated that the yield will improve. can.

In addition, the design using the master slice method can also reduce the wiring width of the power supply, which increases the area of the wiring channel.Therefore, it is highly anticipated that DA processing of a wide variety of products in small quantities in a short period of time will lead to large-scale integration in the future. It is clear that a great effect can be expected in semiconductor devices that must be produced with high yield.

[Brief explanation of drawings]

Figure 1 shows a conventional example of a chip configured using the Master Marais method, Figure 2 shows the circuit configuration of an ECL, which is one of the basic circuits configured with cells, and Figures 3 and 4 are used in this book. It is a chip pattern illustrating an embodiment of the invention. 1, 11...Semiconductor substrate, 2, 12, 22...V _CC
Power pad, 3, 13, 23...Vee power pad,
4, 14...Inner region where cells are arranged in a matrix, 5,15,25...V _CC power supply wiring pattern, 6,16,26...Vee power supply wiring pattern,
7, 17, 27...input/output pad, 18...opening part,
Regarding the symbols in Figure 2, T1, T2, T3
...Transistor, R _C1 , R _C2 ...T1, T2 respectively
A collector resistor connected to the collector of R _E3
...Emitter resistance connected to the emitter of T3, r _c ...Wiring resistance of V _CC power supply wiring, r _e ...Wiring resistance of Vee power supply wiring, B1, B2, B3...Base terminals of transistors T1, T2, T3, respectively, C2 ...Collector terminal of transistor T2.

Claims (1)

[Claims] 1. An internal region in which a plurality of cells constituting an ECL circuit are arranged in a matrix, a highest potential power supply pad and a lowest potential power supply pad provided at the periphery of the internal region, and alternately parallel to the internal region. and a plurality of highest potential power supply wiring patterns and lowest potential power supply wiring patterns arranged independently from each other and each having the same width; an insulating film provided on the highest potential power supply wiring pattern and the lowest potential power supply wiring pattern; A first opening provided in the insulating film by exposing the central portions of the plurality of highest potential power wiring patterns, and a first opening provided in the insulating film by exposing the central portions of the plurality of lowest potential power wiring patterns, respectively. a second opening provided in the inner region, and a second opening provided on almost the entire surface of the insulating film on the internal region, one of which is connected to the highest potential power supply pad, and one of which is connected to the first The other is connected to the plurality of highest potential power supply wiring patterns through the openings, and the other is connected to the lowest potential power supply pad and connected to the plurality of lowest potential power supply wiring patterns through the second opening. A semiconductor device comprising first and second wiring patterns connected to each other.