JPS6254939A - Monolithic integrated circuit - Google Patents

Abstract

PURPOSE:To perform high speed of a monolithic integrated circuit by preparing two power source potential supply lines for respective circuits to be wired to suppress the noise margin of the circuit, and increasing the degree of freedom of the signal wirings without increasing a chip size. CONSTITUTION:The first type of power source potential supply wiring region 13 and the second type of power source potential supply wiring region 15 are disposed on the upper layer of a basic cell 11, and the first and second types of circuit components are provided on the lower layer. Thus, when supplying the external power source potential to the internal cell array region of a gate array, the power source potential supply wirings to the circuit component having a noise margin and the power source potential supply wirings to the circuit component having no noise margin are separated to supply the external power source potential. Thus,the noise margin of the circuit can be obtained while reducing the power source potential wiring region laid in the internal cell array region as small as possible, the wiring degree of freedom of signal wirings is increased without increasing the chip size and the internal cell array region to perform electric characteristic and particularly high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a monolithic integrated circuit, and particularly to a gate array type master slice type monolithic integrated circuit in which basic cells are arranged in rows and columns to constitute an internal cell array region.

[Conventional technology]

Conventionally, gate array-type master slice integrated circuits have been developed in which basic cells are arranged in rows and columns to form an internal cell array area.
When supplying an external power supply potential to an internal cell array region (hereinafter referred to as a gate array), it is necessary to supply it to the basic cells within the internal cell array region. Power supply potential supply wiring is laid vertically over the internal cell array area so that all types of external power supply potentials are located on each basic cell, and each basic cell part is provided with the external power supply wiring required by that basic cell. A method of supplying electric potential was used.

Most conventional large-scale gate arrays are CMOS gate arrays. In the case of CMOS gate arrays, the noise margin of the circuit itself is large and the steady current of the circuit is small, so even if very thin power supply potential supply wiring is laid within the internal cell array area using the conventional method, no problems will occur. There wasn't. In addition, in the case of conventional bipolar gate arrays, the scale is relatively small and the noise margin of the circuit itself is small, and even in ECL gate arrays where the steady current of the circuit is large, conventional methods are used to By laying thick power supply potential supply wiring, it was possible to sufficiently obtain the desired electrical characteristics. However, as the electrical characteristics of CMOS gate arrays, especially their speeds, have improved, ECL gate arrays are now required to be large-scale and even faster. The inconvenience caused by laying the supply wiring has become noticeable. The high speed of the ECL gate array depends largely on the driving impedance and load capacitance of the circuit. Therefore, in order to provide a logic amplitude that ensures the minimum necessary noise margin for circuit operation and to suppress drive impedance to a low level, the steady current of the ECL circuit inevitably becomes large.

As the scale of the gate array increases, the number of basic cells to be supplied per power supply potential supply arrangement 1! which runs vertically within the internal cell array region and supplies external power supply potential to the basic cells usually increases. In the case of large-scale ECL gate arrays that require high speed, each basic cell has a large steady-state current, so when using the conventional power supply potential supply wiring wiring method, it is possible to minimize the reduction in noise margin due to level shift of the power supply potential. Therefore, it is necessary to set the wiring width of one power supply potential supply wiring extending vertically in the internal cell array region to be quite wide. However, setting the power supply potential supply wiring width to be thick does not reduce the area for signal wiring because the area for wiring is limited in gate arrays, and it is necessary to expand the wiring for signal wiring. In this case, the chip size increases, the average wiring length of signal wiring connecting basic cells increases, the electrical characteristics of the integrated circuit as a whole, especially the high speed, are impaired, and the manufacturing yield decreases. Furthermore, when the wiring width of the power supply potential supply wiring is set to be large, the intersection area of the signal wiring that is formed in a wiring layer different from the wiring layer in which the power supply potential supply wiring is formed and intersects with the power supply potential supply wiring increases. The parasitic capacitance added to the signal wiring increases, resulting in a loss of high-speed circuit operation.

A conventional gate array type integrated circuit will be explained with reference to the drawings.

FIG. 2 is a layout diagram of an example of a conventional gate array type integrated circuit.

In this integrated circuit, basic cells 11' are arranged in a matrix of 20 rows and 10 columns to form an internal cell array area 25, and an external power supply potential supply wiring 23 is provided on the opposite side. It is constructed by providing the following.

The external terminal 21 is supplied with the highest external power supply potential from the outside, and this potential is supplied to the internal cell array region 25 through the external power supply potential supply wiring 23. The external terminal 22 is similarly supplied with the lowest external power supply potential, and this potential is similarly supplied to the internal cell array region 25 through the power supply potential supply wiring 24.

FIG. 3 is a layout diagram of the basic cell shown in FIG. 2.

Circuit components are formed in the lower layer of the basic cell 11', and power supply potential supply wiring regions 32 and 33 are provided in the upper layer.

The power supply potential supply wiring area 32 is connected to the external power supply potential supply wiring 3 of the adjacent basic cell 11' connected vertically in FIG.
Connect with 2. Similarly, the power supply potential supply wiring area 33 is connected to the second
It is connected to the external power supply potential supply wiring 24 in the figure. In this way, the power supply potential supply wirings 23 and 24 in FIG.
As a result, each of the basic cells 11' of the internal cell array region 25 is vertically traversed.゛Figure 4 is the conventional EC
FIG. 2 is a circuit diagram of an L basic circuit.

The ECL basic circuit consists of two circuit components: a current switch section 45 and an emitter lower section 46. The current switch section 45 includes a transistor Q3, a resistor R,
A constant current section is configured and the constant current is passed through the transistor Q1.
and resistance R1 due to the switching operation of transistor Q2.
Alternatively, it flows through resistor R8. One end of the resistor R1 and the resistor R2 is a power supply potential supply wiring 4 to which a high external power supply potential is applied.
1, and one end of the resistor R3 is connected to a power supply potential supply wiring 43 to which a low external power supply potential is applied.

Transistor Q of resistor R1 or resistor R2! Alternatively, at one end connected to the collector terminal of the transistor Q2, a high level potential is generated when no current flows through the resistor R or R1, and a low level potential is generated when the current flows. It is input to the pace terminal of transistor Q4. The difference between the high level potential and the low level potential is called a logic amplitude. The emitter-follower section 46 outputs to the emitter terminal a high-level potential or a low-level potential whose level is shifted by the forward voltage between the pace and emitter of each transistor compared to the level input to the pace terminal c'C of the transistor Q4 or Q5. do. Emitter fist 7 oroa part 46
The collector terminals of transistor Q4 and transistor Qs are connected to a power supply potential supply wiring 42 to which a high external power supply potential is applied, and one end of the resistor R4 and resistor R6 is connected to a power supply potential supply wiring 42 to which a low external power supply potential is applied. It is connected to the wiring 44.

This ECL basic circuit is incorporated into the basic cell of FIG.

Now, the current in the current switch section 45 in FIG. 4 is 1 mA, the total current in the emitter follower section 46 is 2 mA,
Assume that the logic amplitude of the current switch section 45 is 50 QmV, and consider a case in which two sets of circuits shown in FIG. 4 are included in each basic cell 11' of FIG. 2. To simplify the explanation, only the highest potential external power supply potential system will be explained. The highest potential applied to the external terminal 21 in FIG. 2 is connected to the wiring in the power supply potential supply wiring area 32 in FIG. Width is 100μm, length is 250μm, wiring layer resistance is 0.03
Ω/ To make a stone with your mouth. If the conventional method is adopted, since the highest potential supply wiring on the basic cell 11' is only in the power supply potential supply wiring area 32, both the power supply potential supply wirings 41 and 42 are connected to the wiring in the power supply potential supply wiring area 32. .

As a result, when the level shift amount of the basic cell 11' on the same column in FIG. The level shift amount is 85.5 mV. The fundamental level shift difference between different columns is 120mV
If so, all basic cells 1 in the internal cell array area 25
The difference in level shift i between 1' is 105.5 mV.

For ECL gate arrays, level shifting of high potential power supply potentials directly leads to a reduction in noise margin. Since a level shift of a low power supply potential normally appears as a decrease in logic amplitude, 1/2 of this is involved in reducing the noise margin.

For the sake of simplicity, let's assume that the value is 1/2 of the noise margin reduction due to the level shift of the high potential power supply potential, and the value will be 5.
2.5 mN'.

When the logic amplitude is 50 omv, the threshold value is 1/2 of it, and the point where the differential gain in the transfer characteristic is 1, that is, the unity gain point, is 100 omv from the threshold value.
If it is mV, the allowable noise margin is 150 mV. If the amount due to other factors that reduce the noise margin is 30 mV, the total amount of noise margin reduction in the above example is 188 mV, which is less than the Schnitty gain reference point, and is a value that cannot guarantee stable operation of the circuit. Now, in order to keep the total noise margin reduction within 150 mV, the width of the wiring in the power supply potential supply wiring area 32 in FIG. 3 is set to 128 μm.
Must be set above. At this time, it is necessary to similarly increase the wiring width of the wiring in the power supply potential supply wiring region 33 on the low potential side, and the total power wiring width increase in the basic cell 11' is required to be 56 μm or more.

[Problem that the invention seeks to solve]

As mentioned above, conventional wiring methods are used to lay power supply potential supply wiring for supplying external power supply potential within the internal cell array area of large-scale gate arrays, especially ECL gate arrays, where the steady current per basic cell is large. In this case, it is necessary to set the power supply potential supply wiring width wide enough to ensure the noise margin of the circuit, and the parasitic wiring capacitance of the signal wiring that is formed in a wiring layer different from the power supply potential supply wiring and intersects with it is significantly reduced. The first drawback is that the electrical characteristics of the integrated circuit as a whole, especially its high speed performance, are impaired. Furthermore, if the width of the power supply potential supply wiring is set to be large without enlarging the internal cell array area, there is a second drawback that the degree of freedom in laying the signal wiring within the limited wiring laying area is reduced.

In addition, when expanding the internal cell array area and increasing the degree of freedom in laying signal wiring, the average wiring length of the signal wiring connecting basic cells increases, which increases the parasitic capacitance added to the wiring and reduces the electrical power of the integrated circuit as a whole. The third drawback of flL4 is that the characteristics, especially the speedup, are impaired, and the chip size is increased and the manufacturing yield is reduced.

The purpose of the present invention is to create a monolithic integrated circuit that uses two power supply potential supply lines for each target circuit, suppresses the noise margin of the circuit, increases the degree of freedom in signal wiring without increasing the chip size, and exhibits high speed. decide to provide.

[Means for Solving the Problems] The monolithic integrated circuit of the present invention has an internal cell array region in which basic cells having circuit components and power supply potential supply wiring are arranged in rows and columns, and a power supply potential is supplied to the internal cell array region. a monolink integrated circuit having an external power supply potential supply wiring and an external terminal, the power supply potential supply wiring mainly supplying a first power supply potential across the basic cell and supplying the first type of circuit component section; The power supply potential supply wiring is divided into a supply wiring and a second power supply potential supply wiring that runs vertically over the basic cell with the second type of circuit component section as the main supply target, and the first and second power supply potential supply wiring are connected to the These are connected outside the internal cell array area.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of an embodiment of the present invention. A first type of power supply potential supply wiring area 1 is provided in the upper layer of the basic cell 11.
3 and a second type of power supply potential supply wiring area 15 are arranged, and first and second types of circuit components (not shown) are provided in the lower layer.

The first type of circuit component is divided into a current switch section 4tl' in FIG. 4, and the second type of circuit component is divided into an emitter follower section 46. Then, a wiring for supplying a potential to the current switch section 44, which is a circuit component of the first type, is placed in the first type of power supply potential supply wiring area 11.12, and a second type of wiring is placed in the second type of power supply potential supply wiring area. Wiring for supplying a potential to the emitter 7 oror portion 46, which is the second type of circuit component, is provided respectively. Further, the wiring provided in the first type of power supply potential supply wiring region 12 supplies the highest potential to the current switch section 44, and is connected to the power supply potential supply line flj41. The wiring provided in the first power supply potential supply wiring area 13 supplies the lowest potential to the current switch section 44, and the wiring provided in the first power supply potential supply wiring area 13
Connect to. The wiring provided in the second power supply potential supply wiring region 14 supplies the highest potential to the emitter follower section 46 and is connected to the stain source potential supply wiring 42.

The wiring provided in the second power supply potential supply wiring region 15 supplies the lowest potential to the emitter follower section 46 and is connected to the power supply potential supply wiring 44 .

The wiring provided in the first power supply potential supply wiring area 12.13 has a width of 60 μm and a length of 250 μm in the basic cell 11.
The wiring provided in the power supply potential supply wiring area 14.15 is @
Assume that if the dimensions are 3ONm and the length is 25011m, the resistance of all wiring layers is 0.030/hole. The wiring in the power supply potential supply wiring region 12 and 14 are both at the highest potential, and are short-circuited at the end of the internal cell array region 25 by connecting to the power supply potential supply wiring 23 in FIG. Similarly, the wirings in the power supply potential supply wiring regions 13 and 15 both have the lowest potential of 6B, and are connected to the external power supply potential supply wiring 24 and short-circuited.

These power supply potential supply wiring regions 12, 13, 14, and 15 extend vertically over the basic cells 11' of the internal cell array region 25 in FIG. Now, to explain the highest potential side, inside the basic cell 11' on the same column in FIG. At this time, the level shift amount of the wiring in the power supply potential supply wiring area 12 of the basic cell 11 corresponding to the farthest basic cell position 11' is 475 mV,
The level shift i of the wiring within the power supply potential supply wiring region 14 is 190 mV. Assuming that the difference in level shift amount between different columns is 20 mV as in the conventional example, the maximum level shift amount difference between all the basic cells 11' in the internal cell array region 25 of the current switch section 45 is 67.5 mV. Further, the maximum level shift amount difference between all the basic cells in the internal cell array region 25 of the emitter/7-year-old lower section 46 is 210 mV.

The same result is obtained on the lowest potential side, so the explanation will be omitted.0 As described in the conventional example, in the current φ switch section 45 shown in FIG. Leads to. The amount by which the level shift amount of the lowest potential power supply potential affects the noise margin is the same as in the conventional example, and if it is 1/2 of that, the value is 33.5.
It is rnV. As in the conventional example, the threshold value is set at 1/2 of the logic amplitude of 500 mV, the unity gain point is set at 100 mV from there, and the amount due to various other factors that reduce the noise margin is set at 3 Qrr: V
Then, the total noise margin reduction in this embodiment is 131 mV, and there is a margin of 19 mV up to the unity gain point. Although the power supply potential supplied to the emitter follower section 46 in FIG. 4 has a level shift of 210 mV, this degree of level shift does not cause any problem to the circuit operation of the emitter 7 follower. As described above, in this embodiment, although the total width of the power supply potential supply wiring provided in the basic cell 11 that supplies the highest potential or the lowest potential is 180 μm,
The total width of the power supply potential supply wiring in the conventional example is 256μ
The results showed that the noise margin was larger than that of the M type, and the electrical characteristics were not impaired in any way.

In the above embodiment, the first type of circuit component is
Although the switch type circuit and the ECL gate array in which the second type of circuit component is an emitter/7-orer have been described as an example, the present invention also provides a switch type circuit in which the first type of circuit component is a TTL logic circuit section and the second type of circuit component is a TTL logic circuit section. Applicable to TTL gate arrays with output buffer circuits as the circuit components, bipolar/0MO8 mixed gate arrays with the first type of circuit components as CMO8 circuit sections, and the second type of circuit components as bipolar circuit sections, etc. This has the effect of isolating one circuit component from noise caused by the other circuit component and ensuring a noise margin.

〔Effect of the invention〕

As described above, the present invention provides power supply potential supply wiring for circuit components with sufficient noise margin when supplying external power supply potential to the internal cell array region of a gate array, and power supply potential supply wiring for circuit components with no margin for noise margin. By separating the power supply potential supply wiring and supplying the external power supply potential, it is possible to minimize the power supply potential wiring area laid within the internal cell array area while ensuring a noise margin for the circuit, resulting in a reduction in chip size. Moreover, it is possible to provide an integrated circuit that increases the degree of freedom in laying signal wiring and exhibits electrical characteristics, particularly high speed, without expanding the internal cell array area. Furthermore, when the present invention is used, circuit components that undergo transient current changes can be separated from circuit components that are susceptible to noise, making it possible to improve the electrical characteristics and reliability of the integrated circuit itself.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of an embodiment of the present invention, FIG. 2 is a layout diagram of a conventional gate array type integrated circuit, FIG. 3 is a layout diagram of the basic cell shown in FIG. 2, and FIG. 4 is a layout diagram of a conventional gate array integrated circuit.
FIG. 2 is a circuit diagram of a CL basic circuit. 11.11'...Song basic cell, 12,13...
First type of power supply potential supply wiring area, 14.15...
...Second type power supply potential supply wiring area, 21, 22
...External terminal, 23.24... External power supply potential supply wiring, 25... Internal cell array area, 32.33... Power supply potential supply wiring area, 41
, 42, 43. 44... Power supply potential supply wiring, 4
5...Current switch section, 46...
・Emitter follower section, Qt, Qt. Qs * Q4 e Qs--) transistor, R+1.
R,,R+,. R4, R,...Resistor. Agent: Susumu Uchihara, patent attorney 1. 2′”j”,,
”'.\,'J Cow 1 Figure Car 3 Figure

Claims (2)

[Claims] (1) Monolithic integration having an internal cell array area in which basic cells having circuit components and power supply potential supply lines are arranged in rows and columns, and external terminals and external power supply potential supply lines that supply external power supply potential to the internal cell array area. In the circuit, the circuit component includes a first type of circuit component section and a second type of circuit component section, and the power supply potential supply wiring mainly connects the first type of circuit component section. divided into a first power supply potential supply wiring that runs vertically over the basic cell as a supply target and a second power supply potential supply wiring that runs vertically over the basic cell and mainly supplies the second type of circuit component section. and the first and second power supply potential supply wirings are connected outside the internal cell array region. (2) Claim (1) wherein the circuit component is an ECL type, the first type of circuit component is a current switch type circuit, and the second type of circuit component is an emitter follower. The monolithic integrated circuit described.