JP2852051B2 - Complementary clock donand circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a clocked NAND circuit integrated into a semiconductor integrated circuit.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional example of a clock NAND circuit.

In this conventional example, a source is connected to a power supply V _CC , and digital signals A and B are respectively input to a gate between PMOS transistors T1 and T2, and a common drain between the PMOS transistors T1 and T2 and a ground (GND). NMOS transistors T5, T6, T3, T with source / drain paths connected in series
4 to obtain an output signal from a connection point between the NMOS transistors T5 and T6. A clock signal is input to the gate of the transistor T5, an opposite-phase clock signal φ is input to the gate of the transistor T6, and the transistor
The digital signal A is input to the gate of T3, and the digital signal B is input to the gate of the transistor T4.

 Next, the circuit operation will be described.

When the clock signal φ is at a low level (O) (that is, when the clock signal is at a high level), both the PMOS transistor T5 and the NMOS transistor T6 are turned off, and the digital signals A and
The output is in a high impedance state regardless of the level of B. When the clock signal φ goes high, the PMOS
When both the transistor T5 and the NMOS transistor T6 are turned on and the digital signals A and B are both at the high level, the NMO
Both the S transistors T3 and T4 turn on, the output goes to low level, otherwise the PMOS transistor T1
Alternatively, T2 is turned on, and the output goes high. Table 1
Is a truth table of the conventional example.

FIG. 4 is a diagram showing a layout pattern when the circuit of FIG. 3 is formed into a semiconductor integrated circuit.

4, parts corresponding to those in FIG. 3 are denoted by reference numerals of the respective parts described in FIG. 3 to clarify the correspondence. The gate electrode of each transistor (a portion provided with a number of points in the figure) is made of, for example, polysilicon, and the wiring 20 is made of, for example, aluminum. The wiring 20 and the source or drain of the transistor are connected via a contact hole 19.

[Problems to be solved by the invention]

In the case of the above-described conventional complementary clock NAND circuit, when the IC is formed, as shown in FIG. 4, the common drain electrode 11 of the P-channel transistors T1 and T2 and the source electrode 13 of the P-channel transistor T5 are separated from each other. In order to connect these electrodes, one extra contact hole 19 and wiring 20 are required, and in order to take out the output, the drain electrode of the transistor T5 is required.
One additional contact hole 19 is required for 14 and PMOS
In the logic circuit composed of the transistors T1, T2, T5,
There is a drawback that the occupied area increases and the pattern becomes complicated, so that the electrical characteristics deteriorate due to an increase in parasitic capacitance.

[Means for solving the problem]

A complementary clock donand circuit according to the present invention includes a first transistor of one conductivity type connected between a first power supply line and a first node and having a gate to which a first input signal is input;
The second transistor of one conductivity type, which is connected between the first node and an output terminal and whose gate receives a control signal, and which is connected between the first power supply line and a second node; A third transistor of the one conductivity type, the gate of which is input with a second input signal, and the one conductivity type of a third transistor connected between the second node and the output terminal, the gate of which is input with the control signal; A fourth transistor, and fifth, sixth and seventh transistors of the second conductivity type connected in series between the output terminal and a second power supply line, wherein the gate of the fifth transistor is Receives the inverted signal of the control signal, inputs the first input signal to the sixth transistor gate, and inputs the second input signal to the gate of the seventh transistor. Complementary clocked NAND circuit , The first transistor,
A first diffusion layer connected to the first power supply line; and a second diffusion layer provided to face the first diffusion layer via a gate electrode to which the first input signal is supplied. Wherein the second transistor is provided to face the second diffusion layer via a gate electrode to which the control signal is input, and the second diffusion layer shared with the first transistor. A third diffusion layer connected to the output terminal, wherein the third transistor is supplied with a fourth diffusion layer connected to the first power supply line and the second input signal. A fifth diffusion layer provided opposite to the fourth diffusion layer via a gate electrode, wherein the fourth transistor is shared with the third transistor.
And a third diffusion layer provided to face the fifth diffusion layer via a gate electrode to which the control signal is input and shared with the second transistor, And the third transistor and the fourth transistor are symmetrically arranged with the output terminal interposed therebetween.

[Action]

By changing the parallel-series connection of the P-channel type transistors to a logically equivalent series-parallel connection, the source and drain electrodes of each transistor can be shared, and furthermore, the connection The number of wirings and contact holes can be reduced, so that the occupied area can be reduced and the switching speed can be improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of a complementary clock donand circuit of the present invention, and FIG. 2 is a diagram showing a layout pattern when the present embodiment is integrated into an IC.

In this embodiment, in a circuit portion composed of PMOS transistors, a PMOS transistor T7 is newly added to divide a transistor into which a clock signal is input into two, and an A signal gate input transistor T1 and a clock signal gate input transistor T5 is connected in series, one B signal gate input transistor T2 and one clock signal gate input transistor T7 are connected in series, and the two series circuits are connected in parallel. In the present embodiment, it is obvious that only the position of the MOS transistor to which the clock signal is input is changed, and it is logically equivalent to the conventional example.

In the conventional example, when the IC is used, the clock signal gate input transistor T5 and the transistors T1 and T2 to which the digital signals A and B are input cannot share the source and drain electrodes. In this embodiment, as shown in FIG. 2, transistors T5 and T5 to which a clock signal is input are provided.
7 and transistors T1 and T2 to which digital signals A and B are input, respectively, are connected in series, so that the source and drain electrodes can be shared. Thus, the number of contact holes can be reduced, and extra wiring between transistors can be eliminated. The above description has been made with reference to the example of the two-input clock NAND circuit. However, the present invention is not limited to this. The present invention can be similarly applied to a three-input or more clock NAND circuit.

〔The invention's effect〕

As described above, according to the present invention, by changing the circuit configuration of the clock NAND circuit in a semiconductor integrated circuit, the area occupied by the circuit can be reduced, the degree of integration can be improved, and a low-cost LSI can be manufactured. is there. Further, the pattern shape is simplified, and the area of the contact hole and the diffusion layer is reduced, whereby the parasitic capacitance can be reduced and the high-speed switching operation can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of a complementary clocked NAND circuit of the present invention, FIG. 2 is a diagram showing a layout pattern when the circuit of FIG. 1 is formed into an IC, and FIG. 3 is a circuit of a conventional example. Figure,
FIG. 4 is a diagram showing a layout pattern when the conventional circuit of FIG. 3 is integrated into an IC. A, B: Digital gate input signal, φ: Clock signal, Clock reverse phase signal, Transistor output, V _CC: Power supply, GND: Ground, T1, T2, T5, T7: P channel Type transistors, T3, T4, T6: N-channel type transistors, 1 to 18: Source or drain electrode of each transistor, 19: Contact hole, 20: Wiring.

Claims (1)

(57) [Claims] 1. A first transistor of one conductivity type connected between a first power supply line and a first node and having a gate to which a first input signal is input, and the first node and an output terminal And the second transistor of one conductivity type, the control signal being input to the gate, between the first power supply line and the second power supply line.
The third transistor of one conductivity type, which is connected between the second transistor and a node of
The fourth transistor of one conductivity type, which is connected between the output terminal and the node and is connected in series to the gate, to which the control signal is input, and is connected in series between the output terminal and a second power supply line. Fifth, sixth, and seventh transistors of the second conductivity type, wherein the inverted signal of the control signal is input to the gate of the fifth transistor, and the first transistor is connected to the gate of the sixth transistor. An input signal is input and the seventh
A complementary clocked NAND circuit in which the second input signal is input to a gate of the transistor, wherein the first transistor has a first diffusion layer connected to the first power supply line; A second diffusion layer provided opposite to the first diffusion layer via a gate electrode to which the first input signal is supplied, wherein the second transistor is a first transistor And a third diffusion layer provided opposite to the second diffusion layer via a gate electrode to which the control signal is input and connected to the output terminal. The third transistor is opposed to the fourth diffusion layer via a fourth diffusion layer connected to the first power supply line and a gate electrode to which the second input signal is supplied. And a fifth diffusion layer provided, wherein the fourth transistor The transistor is provided opposite to the fifth diffusion layer via a gate electrode to which the control signal is input, and is shared with the second transistor, the fifth diffusion layer being shared with the third transistor. The first transistor and the second transistor, and the third transistor and the fourth transistor are symmetrically arranged with the output terminal interposed therebetween. Complementary clocked NAND circuit.