JPS6068718A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a tri-state type drive circuit with high speed and small chip area by using mainly MOSFETs and combining bipolar transistors (TRs) to them. CONSTITUTION:NOR circuits 5, 6 inputting an enable signal (INE)CS selecting one of plural IC chips and a signal 1 from a chip are provided, and since N- MOSFETs 52, 62 are turned on when the INESC is at high level, a TR8 and an N-MOSFET9 are turned off and an output terminal 2 is in the floating state. Since the INECS is at L level, since P-MOSFETs 51, 61 are turned on, any of the N-MOSFET9 and the TR8 is turned on in response to the level H/L of the signal 1 and the output terminal goes to L/H.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an insulated gate field effect transistor (hereinafter referred to as
This invention relates to a semiconductor integrated circuit that is faster than conventional semiconductor integrated circuits, which is based on a MOS-F'BT (abbreviated as MOS-F'BT) and is further combined with bipolar transistors.

[Background of the invention]

Conventionally, enhancement type P channel MO8-FET
and Enhancement Men) Type N-1-Yannel MO8-FET
O-MOS (Oompl
In the elementary-MOS) circuit, a drive circuit as shown in FIG. 1 is used. In the same figure.

1 is an input terminal, 2 is an output terminal with a load capacitance 3, 4 is a power supply terminal, and PI is a P-channel MO5-FET.

N1 is an N-channel MO8-FET, and VDD is a positive power supply voltage. C! composed of this (Pi, Nl)! -M.O.
The disadvantage of the 8llK dynamic circuit is that the load capacitance 3 is large, and when charging this at high speed, the dimension of Pl (for example, channel width W) must be increased. Therefore, this drive circuit occupies a large area, resulting in a large loss in terms of integration.

Therefore, the inventors of the present application provided an improved drive circuit shown in FIG. 2 in Japanese Patent Application No. 52-1490. In the figure, P2 is a P-channel MO whose drain and source are p-type high concentration impurity layers formed in an n-type semiconductor device.
8-FETs, N2 and N3 are N-channel MO8-FETs whose drain and source are n-type high concentration impurity layers formed in wells of p-type impurity layers provided on the substrate surface, and Bl is p-type impurity layers provided on the substrate surface region. a planar type bipolar type impurity layer as a base, the substrate as a collector, and an n-type high concentration impurity layer provided in the p-type impurity layer base as an emitter;
It is a transistor. What is distinctive about this figure is that the above bipolar transistors are integrated on the same chip.
It is recommended to configure the drive circuit with the wiring shown in Figure 2.
When input terminal 1 is at ground potential, N2 and N3 are cut off, B2 is conductive, current flows from power supply terminal 4 to the base of 81, and B1 is conductive, so output terminal 2 is at a high potential. .

Also, when input terminal 1 is at a high potential, B2 is cut off and B
1 is also cut off and N2 becomes conductive, so the output terminal becomes the ground potential. When 1 transitions from high potential to ground potential, a large current flows from 4 through B1, and a large load 3
can be charged quickly.

Note that the transistor P2 only needs to have a driving ability sufficient to charge the junction capacitance formed by the base and collector of the transistor B1. As a result, the dimensions of B2 are reduced, and the area occupied by the drive circuit is reduced. In addition, the diffusion depth of the n-type high concentration impurity layer that becomes the emitter of B1 is made deeper than the diffusion depth of the n-type high concentration impurity layer that becomes the source and drain of a normal N-channel MO8-FET. - The base width of the transistor can be reduced. In this case, since the bipolar transistor B1 has a small base width and a large hFE, it contributes even more to speeding up the present drive circuit.

The N-channel MO8-FET, N3, is designed to rapidly lower the potential of the base of the bipolar transistor B1 to the ground potential via N3 when the potential of the input terminal 1 transitions from the ground potential to the high potential. It is advantageous in terms of power consumption and low power consumption.

FIG. 3 is a circuit connection diagram of a modification of the drive circuit shown in FIG. 2. The P-channel MO8-FET B3 can raise the potential of the output terminal 2 to the power supply voltage vDD when the potential of the input terminal 1 is at the ground potential, which improves the operating performance of the next stage circuit connected to the output terminal 2. improve.

The drive circuits shown in FIGS. 2 and 3 described above can provide a drive circuit that occupies a small area and has high-speed performance. However, the drawback of the above drive circuit is that when used as an output buffer circuit etc., the so-called logic "0", "1'", "
Tri-state or three-value float
It cannot be used as a state (three 5-state) type.

In other words, when increasing the capacity by using a large number of IC memories with a limited word structure, it is necessary to eliminate the amount of information read from each IC memory in terms of mounting space and cost. In order to configure a so-called wired OR, which can realize the O-OR function just by connecting, each memo 1. The IIO data output circuit must be configured in the above-mentioned tri-state method. In other words, only the IC memory chip selected by the chip enable signal is connected to the data bus, and the others are disconnected from the data bus and left floating.
) or high impedance 7. (HighImp
edance ) state.

Further, as an example of a tri-state drive circuit, ROA-0087MO8-Lntegrated Oi
rcuitsManual 1972, Techn.
ical 5eries OMS-271, P, 20
As an example of using a bipolar transistor for the output, there is Japanese Patent Publication No. 50-40977.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a tri-state drive circuit that can quickly determine an output signal even when a large load is applied to the output terminal (or output pin) by half.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples. FIG. 4 is a diagram showing a first embodiment of the present invention.

5.6 in the front stage of the output inverter circuit consisting of
- A circuit composed of Mo8 is provided, and a NO signal for the chip enable signal D applied to terminal 4 and the input signal is provided.
It forms an R circuit. As a result, C8 is set to High level (.1. That is, each 0-Mo8 circuit (7) of (51, 52), (61, 62)) has a positive voltage above the threshold, for example, a voltage at the power supply voltage VDD level. ), the P-channel MOS transistors 51 and 61 are in the off state, and the N-channel MOS transistors 52 and 62 are in the on state.
Base 81 of bipolar transistor 8 and gate 91 of N-channel MOS transistor 9 are always set to ground potential, transistors 8.9 are always cut off, and output terminal 2 is in a floating state. Also, O8 is at a low level (“0”, i.e. (51, 52)
, (61, 62), when the voltage is lower than the threshold voltage of each 0-Mo8 circuit (for example, ground potential or 0 voltage), the transistors 51 and 61 are on, and the transistors 5 and 5 are in the on state.
2.62 is in the off state, and the circuit outputs according to the input signal, for example, the signal at terminal 1. That is, the signal at the input terminal l is a "0" low level signal, that is, (53, 54),
When the threshold voltage of each 0-M08 circuit (63, 64) is low (e.g., ground potential or 0-4), the output terminal 2 receives a "1" signal (high level, that is, the power supply voltage VDD).
appears.

Also, the input terminal signal is “1” (high level, that is, (53,
54) Output terminal 2 when the positive voltage signal is higher than the threshold value of each 0-Mo8 circuit (63, 64), e.g. vDD level)
A signal of "0" (low level, ie, ground voltage or 0 voltage) appears.

In the manner described above, the circuit of FIG. 4 can maintain high-speed operation while allowing the output terminal to obtain all three values. Furthermore, the area occupied by the circuit is kept as small as possible.

In FIG. 4, 7 is an 0-Mo S inverter constituted by a P-channel MOS transistor 71 and an N-channel MO'S transistor 72. Further, in FIG. 4, P channel MO8) transistor 5
3 and 63 correspond to the transistor P2 of the circuit of FIG. 2, and the N-channel transistor 54 corresponds to the transistor N3 of the circuit of FIG. 2, respectively.

On the other hand, if the output terminal 2 is accompanied by a larger load and needs to be driven at high speed, it is necessary to use a P-channel MO8-FET51.5 cascade-connected in a 5.60 circuit.
3 or 61.63 (for example, channel width) must be increased, and the area occupied by the circuit itself increases. FIG. 5 shows the output inverter circuit of 8.9 and 12.
A 0-MOS inverter circuit of 0.11 is provided as a buffer between the 13 logic circuits, and this creates a tri-stage output buffer circuit that occupies a small area and can be driven at high speed. You can get it.

In the circuit of Fig. 5, 71.101.111.121
, ]31.123.133 is an ennouncment type P-channel MO8-FET, 72.102.112.12
2.132.124.134 is an enhancement type N-channel MO8-FET, (71, 72), (1
01,102), (111,112), (121,12
2), (123, Engineering 24), (131, 132), (1
33, 134) constitutes each C-MO8 circuit. This causes the chip enable signal O8 to go high (C
8), transistors 121 and 131 are off, transistors 122 and 132 are on, and the input signal is sent to the base 81 of transistor 8 through two sets of 0-MOS inverters (123, 124) and (101, 102). and is transmitted to the gate 91 of the transistor 9 through three sets of (, -M
OS inverter (71, 72), (133, 134),
(101, 102), and the circuit outputs according to the input signal.

That is, if the input signal is "0", the output signal is "1", and if the O1 input signal is "1", the output signal is "1".

On the other hand, the chip enable signal O8 is at a low level (C
8), transistors 121 and 131 are on and transistors 122 and 123 are off.
(121, 122), (131°132) each 0-MO
The output of the 8 circuit is always set to "1", the base 81 of the transistor 8 and the gate 91 of the transistor 9 are always set to the ground potential, and the transistors 8 and 9 are always cut off.
In the off state, the output terminal 9 becomes in a floating state.

In the above, using a positive voltage power supply, the P-channel MO
An 0-MO8 circuit was used in which an 8-FET was used as a load and an N-channel MO8-FET was used as a driver. However, using a negative voltage power supply, an N-channel MO8-FET as a load,
0 using P-channel MO8-FET as driver
- The present invention may be configured with an MO8 circuit. (That is, change the N-channel MO8-FET in Figures 4 to 6 to P-channel, and the P-channel MO8-FI8T to N-channel.) In this case, a PNP bipolar transistor is used as transistor 8, and the polarity of the signal is also reversed. Just use it.

[Brief explanation of drawings]

1, 2 and 3 are diagrams showing a conventional 0-MO8 drive circuit, and FIGS. 4 and 5 are diagrams showing an embodiment of the drive circuit of the present invention. 51.53.61.63.71...Ennomination type P channel MO8-FET, 9.52.54.6
2.64.72...Enhancement type N-channel MO8-FET, 8...NPN pibosi transistor. 81 Figure 2 Concave Figure 4

Claims (1)

[Claims] 1. A first NOR circuit that receives a plurality of 10 chips, a chip enable signal for selecting the chip, a signal from the chip, a signal obtained by inverting the signal from the chip, and a signal that selects the chip. a second NOR circuit which receives as input a chip enable signal of the first NOR circuit;
A semiconductor integrated circuit characterized in that an output signal of the OR circuit is input to a base electrode of a bipolar transistor as a load, and an output signal of the second NOR circuit is input to a gate electrode of a MOSFET as a driver.