JPH05326890A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To provide the output buffer circuit of a semiconductor integrated circuit provided with a read-only memory, where the output buffer circuit can be set optimal in characteristics even if the operating voltage of a power supply is different. CONSTITUTION:The output S4 of a drive circuit 4 and the output S5 of a drive circuit 5 are inputted into the gates of a P-type MOS transistor P1 and an N-type MOS transistor N1 which drive a data output terminal 2, and a control circuit 14 possessed of a memory element MC of the same structure with a read-only memory is provided. An N-type MOS transistor N4 and a P-type MOS transistor P4 are set into a conductive state or a non-conductive state corresponding to data which are written in the memory MC, whereby the P-type MOS transistor P1 and the N-type MOS transistor N1 are changed in conduction speed, and thus an output buffer circuit optimal in characteristics to the different voltage of a power supply can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit used in a semiconductor integrated circuit including a read-only memory element for writing information during a manufacturing process.

[0002]

2. Description of the Related Art For a read-only memory element in which information is written in a manufacturing process of a semiconductor integrated circuit, for example, a threshold voltage of a MOS field effect transistor (hereinafter referred to as a MOS transistor) is selectively used in the manufacturing process. Mask RO that changes and stores information
There is a read-only memory element called M (Read Only Memory).

In this memory element, as shown in the sectional view of FIG. 4A, N-type source / drain diffusion layers 42 and 43 are provided on a P-type substrate 41, and gate insulation is performed on the P-type substrate 41. An N-type enhancement MOS transistor having a gate electrode 45 arranged via a layer 44, and N-type source / drain diffusion layers 42 and 43 on a P-type substrate 41 as shown in the sectional view of FIG. 4B. Further, a gate electrode 45 is arranged on the P-type substrate 41 via a gate insulating layer 44, and a channel portion 46 under the gate electrode 45 is channel-doped with an N-type impurity such as phosphorus to make the threshold voltage negative. This N-type enhancement MO transistor is prepared and stored according to the information to be stored.
Information is stored by selecting an S transistor or an N-type depletion MOS transistor.

That is, the gate voltage shown in FIG.
In the drain current characteristic diagram, N-type enhancement M
The characteristic of the OS transistor is that the threshold voltage is positive, as indicated by the solid line NE, and the gate voltage V _G is 1 in this example.
When V or more, it becomes conductive. N-type depletion MOS
The characteristic of the FET is that the threshold voltage is negative as shown by the solid line ND, and in this example, it becomes conductive when the gate voltage V _G is -3 V or higher. When reading information from this storage element, if the gate voltage V _{G is set} to 0 V, the storage element becomes non-conductive in the case of an N-type enhancement MOS transistor, and the storage element becomes conductive in the case of an N-type depletion MOS transistor. As a result, the current can be detected by reading the current flowing through the memory element.
The information to be stored is written in the manufacturing process of the semiconductor integrated circuit by the data supplied by the customer.

A semiconductor integrated circuit having such a read-only memory element is provided with an output buffer circuit for outputting information to the outside of the semiconductor integrated circuit. Figure 5
A circuit diagram of an example of a conventional output buffer circuit is shown in (a). Referring to the figure, this output buffer circuit includes a P-type MOS transistor P1 provided between a power supply line (potential V _CC ) 1 and a data output terminal 2 and a ground line (potential V _SS ).
3 and the data output terminal 2 and an N-type MOS transistor N1. Further, between the power line 1 and the ground line 3, a P-type MOS transistor P2 and a resistance element R are provided.
1 and the N-type MOS transistor N2 are connected in series,
A drive circuit 4 whose output end is a connection point between the P-type MOS transistor P2 and the resistance element R1 is provided, and the output end is P
Type MOSFET transistor P1.

Further, between the power line 1 and the ground line 3, a P-type M
The OS transistor P3, the resistance element R2, and the N-type MOS transistor N3 are connected in series, and the resistance element R2 and the N-type M transistor are connected.
A drive circuit 5 whose output end is the connection point of the OS transistor N3 is provided, and the output end is an N-type MOS transistor N.
1 is connected to the gate. The output data signal D is input to the gates of the P-type MOS transistors P2 and P3 and the N-type MOS transistors N2 and N3 via the input terminal 6.

The operation of this circuit will be described below with reference to the voltage waveform diagram shown in FIG. As shown in FIG.
When the output data signal D changes from the high level to the low level at time T1, the P-type MOS transistor P2 of the drive circuit 4
Becomes conductive and the N-type MOS transistor N2 becomes non-conductive, so that the output S4 becomes high level by the P-type MOS transistor P2. At the same time, P of the drive circuit 5
Type MOS transistor P3 becomes conductive and N type MOS
Since the transistor N3 becomes non-conductive, the output S5 becomes high level by the P-type MOS transistor P3 via the resistance element R2. That is, the output S4 which is the gate signal of the P-type MOS transistor P1 becomes high level, so that the P-type MOS transistor P1 becomes non-conductive,
The output S which is the gate signal of the N-type MOS transistor N1
When 5 becomes high level, N-type MOS transistor N1
Becomes conductive. As a result, the data output terminal 2 is discharged through the N-type MOS transistor N1 and becomes low level. Next, when the output data signal D changes from the low level to the high level at time T2, the P-type MOS transistor P2 of the drive circuit 4 becomes non-conductive and the N-type MOS transistor N2 becomes conductive, so that the output S4 Is a resistance element R
1 and low level via the N-type MOS transistor N2. At the same time, the P-type MOS transistor P of the drive circuit 5
Since 3 becomes non-conductive and the N-type MOS transistor N3 becomes conductive, the output S5 becomes low level by this N-type MOS transistor N3. That is, P-type MO
When the output S4 which is the gate signal of the S transistor P1 becomes low level, the P-type MOS transistor P1 becomes conductive, and when the output S5 which is the gate signal of the N-type MOS transistor N1 becomes low level, the N-type MOS transistor becomes The transistor N1 becomes non-conductive. As a result, the data output terminal 2 is charged by the P-type MOS transistor P1 and becomes high level.

Here, considering the output buffer circuit on the chip of the actual integrated circuit, as shown in FIG. 5B, in this semiconductor integrated circuit 8, on the semiconductor chip 7,
A circuit block (not shown) including the above-mentioned output buffer circuit is formed. The power supply voltage and the ground potential necessary for the operation of these circuits are externally input to the lead terminals 9CC and 9SS of the integrated circuit package, and the bonding pads on the chip 7 are connected through the thin metal wires 10CC and 10SS such as bonding wires. 11CC, 11S
It is transmitted to S and further supplied to each circuit by the power supply line 1 and the ground line 3 on the chip 7. Therefore, inductances L _CC and L _SS parasitic on the wiring exist between the lead terminals 9CC and 9SS and the power supply line 1 and the ground line 3 of the circuit such as the output buffer circuit on the chip.

Therefore, in the output buffer circuit shown in FIG. 5A, when the data output terminal 2 is charged and discharged at high speed, the power supply voltage V _CC and the ground potential V _SS fluctuate, and the same semiconductor chip as the output buffer circuit is provided. The other circuit formed in the above will malfunction. Conventionally, in order to suppress the fluctuations of the power supply voltage V _CC and the ground potential V _SS to be small, the mutual transfer conductance of the P-type MOS transistor P1 and the N-type MOS transistor N1 is reduced within a range satisfying the operation speed, or FIG. As shown in (a), the drive circuits 4, 5
Resistor elements R1 and R2 are provided in the circuit to smooth the changes in the gate voltage of the P-type MOS transistor P1 and the N-type transistor N1 to prevent a sudden change in current.

[0010]

In the above conventional output buffer circuit, the external power supply voltage during operation is generally 5
Since the external power supply voltage is 5V, the power supply voltage V inside the semiconductor integrated circuit is determined by the operation of the output buffer circuit when the external power supply voltage is 5V.
_It is usually optimally designed in consideration of the magnitude of fluctuations in _CC and ground potential V _SS and the operating speed of the output buffer circuit. However, in recent years, a semiconductor integrated circuit in which the external power supply voltage during operation is other than 5 V is also required. For example, Nikkei Microdevice, 1991, February issue, 83-87.
Page, "Lower voltage of MOS LSI spreading from dedicated products to general-purpose products", P83 left 1st to 4th lines, "Low voltage MOS LSI products with external power supply reduced from 5V to 3V or 3.3V are general-purpose memory , General-purpose processors, gate arrays, etc. ”, the external power supply voltage is 3V.
There is a demand for semiconductor integrated circuits set in the vicinity. However, in such a low power supply voltage semiconductor integrated circuit,
When the conventional output buffer circuit shown in FIG. 4A is operated with an external power supply voltage of 3V, the power supply voltage V _CC and the ground potential V _SS inside the semiconductor integrated circuit due to the operation of the output buffer circuit are increased.
Fluctuation is small, but the operation speed is slow. Therefore, when the external power supply voltage is used in the vicinity of 3 V, the size of the MOS transistor forming the output buffer circuit is changed, or the resistance values of the resistance elements R1 and R2 in FIG. 4A are changed. Or, it needs to be deleted. Such a change requires a change in a mask pattern used in a photolithography process, which is a manufacturing process of a semiconductor integrated circuit, and a product having an external power supply voltage of 5V and a product having an external power supply voltage of 3V are developed by distinguishing the mask pattern. You have to produce it. As a result, man-hours for development and management for production increase. Further, in the mask ROM, in general, a semiconductor substrate (hereinafter, referred to as an intermediate product), which has been processed up to the step immediately before the step of writing information in the manufacturing process, is manufactured in advance. Then, after receiving the data from the customer, the remaining manufacturing processes are performed and shipped. However, if the change of the mask pattern described above is a step prior to the step of writing information, it is necessary to make many kinds of intermediate products, and there is a drawback that production management becomes complicated.

The present invention has been made in view of the above problems, and for semiconductor integrated circuits having different power supply voltages, an output buffer circuit having optimum output characteristics for each power supply voltage is modified. Another object of the present invention is to enable easy formation without changing the mask pattern in the photolithography process.

[0012]

An output buffer circuit of the present invention is an output buffer circuit of a semiconductor integrated circuit including a read-only memory element for writing information during a manufacturing process, which comprises a first power line and a first power line. 1M between the second power line
A circuit in which an OS field effect transistor and a second MOS field effect transistor are connected in series via a data output terminal, and a first drive circuit for driving the gate of the first MOS field effect transistor by receiving at least a data signal from the outside as an input. In an output buffer circuit having a driving circuit and at least a second driving circuit for driving the gate of the second MOS field effect transistor by receiving the data signal as input, control for writing information in the information writing step of the read-only storage element And a data output terminal drive characteristic of the first MOS field-effect transistor and the second MOS field-effect transistor based on information stored in the control storage element, the data output terminal drive characteristics of the first MOS field-effect transistor and the second MOS field-effect transistor being determined by the first drive circuit and the second drive circuit. Characterized by having a control circuit that changes through There.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of the first embodiment of the present invention. Referring to the figure, in this embodiment, a P-type MOS transistor P1 is provided between the power supply line 1 and the data output terminal 2, and an N-type MOS transistor N1 is provided between the ground line 3 and the data output terminal 2. It is provided. Further, a P-type MOS transistor P is provided between the power supply line 1 and the ground line 3.
2 and N-type MOS transistors N4 and N2 are connected in series,
A resistance element R1 is provided between a connection point between the P-type MOS transistor P2 and the N-type MOS transistor N4 and a connection point between the N-type MOS transistors N4 and N2, and the P-type MOS transistor P2, the N-type MOS transistor N4 and the resistance element R1.
A drive circuit 4 having an output S4 at the connection point potential thereof is provided, and the output S4 is connected to the gate of the P-type MOS transistor P1. Further, P-type MOS transistors P3, P4 and N-type MOS transistor N3 are connected in series between the power supply line 1 and the ground line 3, and the connection point of the P-type MOS transistors P3 and P4 and the P-type MOS transistor P4 are connected. A resistance element R2 is provided between the connection point of the N-type MOS transistor N3 and the P-type MOS transistor P4 and the N-type MO transistor.
A drive circuit 5 having an output S5 that is the potential at the connection point between the S transistor N3 and the resistance element R2 is provided, and the output S5 is N
-Type MOSFET is connected to the gate. P-type MOS
Transistors P2 and P3 and N-type MOS transistor N
The data signal D is input to the gates of 2 and N3, respectively. Further, the source and gate of the memory element MC having the same structure as the read-only memory element shown in FIGS. 4A and 4B are connected to the ground line 3, and the drain operates as a load MOS transistor. Connected to the power supply line 1 through the MOS transistor P5, and the inverter circuit 1
The input terminal of 2 is connected to the memory element MC and the P-type MOS transistor P.
A control circuit 14 is provided, which is connected to the connection point of No. 5, and the input end of the inverter circuit 13 is connected to the output end of the inverter circuit 12, and the output of the inverter circuit 12 is controlled by the control signal C.
1 is input to the gate of the P-type MOS transistor P4, and the output of the inverter circuit 13 is set to N as the control signal C2.
It is input to the gate of the MOS transistor N4.

The operation of this embodiment will be described below. First, when the memory element MC is an N-type depletion MOS transistor, the memory element MC is in the conductive state although the gate is at the ground potential V _SS . Therefore, if the mutual transfer conductance of the storage element MC at this time is set to be sufficiently larger than that of the P-type MOS transistor P5, the input end of the inverter circuit 12 is discharged by the storage element MC to a low level. The control signal C1 which is the output of the inverter circuit 12 becomes high level. Further, the control signal C2, which is the output of the inverter circuit 13, becomes low level. In this case, since the control signal C1 is at high level,
The P-type MOS transistor P4 is non-conductive, and
Since the control signal C2 is at low level, the N-type MOS transistor N4 becomes non-conductive. Therefore, in this case, the circuit operation when the data signal D changes is the same as that of the conventional output buffer circuit shown in FIG. 4A, and similar characteristics can be obtained.

Next, when the memory element MC is an N-type enhancement MOS transistor, the memory element MC
Has a non-conductive state because the gate is at the ground potential. Therefore, the input end of the inverter circuit 12 is charged by the P-type MOS transistor P5 and becomes high level, and the control signal C1 which is the output of the inverter circuit 12 becomes low level.
Further, the control signal C2, which is the output of the inverter circuit 13, becomes high level. The circuit operation in this case will be described with reference to the voltage waveform diagram shown in FIG.

As shown in FIG. 2, when the output data D changes from the high level to the low level at time T1, the P-type MOS transistor P2 of the drive circuit 4 becomes conductive and the N-type MO transistor.
Since the S transistor N2 is turned off, the output S4
Becomes high level by the P-type MOS transistor P2. On the other hand, since the P-type MOS transistor P3 of the drive circuit 5 becomes conductive and the N-type MOS transistor N3 becomes non-conductive, the output S5 is the P-type MOS transistor P3.
P type MOS transistor P4 and resistance element R2
High level via parallel circuit. As a result, P type M
The OS transistor P1 becomes non-conductive when the output S4 which is the gate signal becomes high level, while the N-type M
The OS transistor N1 becomes conductive when the output S5 which is a gate signal becomes high level. Therefore, the data output terminal 2 is discharged through the N-type MOS transistor N1 and becomes low level. In this case, the output S5, which is the gate signal of the N-type MOS transistor N1, becomes a high level at a high speed as compared with the conventional output buffer circuit because the P-type MOS transistor P4 is in a conductive state. Since the N-type MOS transistor N1 also becomes conductive at a high speed, the speed at which the data output terminal 2 is discharged and becomes low level is also higher than in the conventional case. Variation of the ground potential V _SS in this case is increased in comparison with the conventional output buffer circuit, for example, power line 1 potential V _CC
Is about 3 V, the fluctuation itself of the ground potential V _SS is small, so that no problem occurs.

Next, when the output data signal D changes from the low level to the high level at time T2, the P-type MO of the drive circuit 4 is generated.
Since the S transistor P2 is turned off and the N-type MOS transistor N2 is turned on, the output S4 is output from the N-type MOS transistor N4 and the resistance element R1 which are connected in parallel.
To the low level by the N-type MOS transistor N13. On the other hand, since the P-type MOS transistor P5 of the drive circuit 5 becomes non-conductive and the N-type MOS transistor N3 becomes conductive, the output S5 becomes low level by the N-type MOS transistor N3. Therefore, the P-type MOS transistor P1 becomes conductive when the output S4 which is a gate signal becomes low level, and the N-type MOS transistor N1 becomes non-conductive when the output S5 which is a gate signal becomes low level. become. As a result, the data output terminal 2
Is charged by the P-type MOS transistor P1 and becomes a high voltage. Also in this case, the N-type MOS transistor N4
Is conductive, the output S4 which is the gate signal of the P-type MOS transistor P1 becomes low level at high speed, as compared with the conventional output buffer circuit. Due to this high-speed level transition, the P-type MOS transistor P1 also becomes conductive at a high speed, so that the data output terminal 2 is charged and brought to a high level at a high speed. In this case, the fluctuation of the power supply voltage V _CC becomes larger than that of the conventional output buffer circuit. For example, if the power supply voltage V _CC is about 3 V,
Since the fluctuation of the power supply voltage V _CC itself is small, it does not matter.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram of the second embodiment of the present invention. Referring to the drawing, in this embodiment, a P-type MOS transistor P provided in parallel between the power supply line 1 and the data output terminal 2 is provided.
1 and P12, and N-type MOS transistors N1 and N12 provided in parallel between the ground line 3 and the data output terminal 2. Then, the data signal D is input to the input terminal of the inverter circuit 15, and its output S6 is input to the gate of the P-type MOS transistor P1. Further, the data signal D is input to the input terminal of the inverter circuit 16 and its output S
7 is input to the gate of the N-type MOS transistor N1. Further, a control circuit having the same circuit configuration as the control circuit 14 shown in FIG. 1, a 2-input NAND circuit 17 and a 2-input NOR circuit 18 are provided. 2-input NAND circuit 17
Receives the data signal D and the control signal C2, and outputs S
8 is input to the gate of the P-type MOS transistor P12. The 2-input NOR circuit 18 receives the data signal D and the control signal C1 as input, and the output S9 is input to the gate of the N-type MOS transistor N12.

The circuit operation of this embodiment will be described below. First, the memory element MC is an N-type depletion MO.
If it is an S-transistor, the control signal C1 becomes high level and the control signal C becomes the same as in the first embodiment shown in FIG.
2 goes low. Then, the NAND circuit 17 does not depend on the data signal D which is the other input signal because the control signal C2 which is one input signal is at the low level,
Its output signal S8 remains high. Also, NO
Since the control signal C1 which is one input signal is at a high level, the R circuit 18 receives the data signal D which is the other input signal.
Output signal S9 remains low. As a result, P-type MOS transistor P12 and N-type M
The OS transistor N12 is always off. Here, the conventional output buffer circuit shown in FIG. 4A and the drive circuit 4 and the inverter circuit 15 in this embodiment are designed in the same manner, and further, the drive circuit 5 and the inverter circuit 16 are provided.
And P-type MOS transistors and N-type MOS transistors in the output stage are designed to be the same, the present embodiment and the conventional output buffer circuit shown in FIG. Shows the characteristics of.

Next, when the memory element MC is an N-type enhancement MOS transistor, the control signal C1 becomes low level and the control signal C2 becomes high level as in the first embodiment shown in FIG. Then, the NAND circuit 17 and N
The OR circuit 18 operates similarly to the inverter circuits 15 and 16. Therefore, when the data output terminal 2 is set to the high level due to the change of the data signal D, the P-type MOS transistors P1 and P12 charge the load, and when the data output terminal 2 is set to the low level, N is set. The type MOS transistors N1 and N12 discharge the load. As a result, the output signal makes a level transition at a higher speed than the conventional output buffer circuit. Also in this case, the fluctuations of the power supply voltage V _CC and the ground potential V _SS are larger than those of the conventional output buffer circuit, but if the power supply voltage V _CC is about 3 V, the fluctuations themselves are small, which causes a problem. I won't.

[0021]

As described above, the output buffer circuit of the present invention has the first MOS transistor provided between the first power supply line and the data output terminal, the second power supply line and the data output terminal. A second MOS transistor provided between the first and second MOS transistors, a first drive circuit for driving the gate of the first MOS transistor, a second drive circuit for driving the gate of the second MOS transistor, and a read-only circuit A memory element having a structure similar to that of the memory element is provided, and a control circuit which changes characteristics for driving the data output terminal of the first MOS transistor and the second MOS transistor according to information stored in the memory element is provided. ing.

Thus, according to the present invention, the characteristics of the output buffer circuit can be easily changed only by changing the information stored in the storage element. For example, when the memory element is an N-type depletion MOS transistor, the characteristics indicated by the output buffer circuit are designed to be optimum when operating near a power supply voltage of 5 V, and the memory element is an N-type enhancement MO transistor.
In the case of an S transistor, if the characteristics indicated by the output buffer circuit are designed to be optimum when operating near a power supply voltage of 3V, it is only necessary to change the information to be written in the memory element.
Even if the power supply voltage is different, there is no need to change the circuit and optimum characteristics can be obtained.

Further, the writing of information to the memory element is performed in the same step as the step of writing information to the read-only memory element in the manufacturing process of the semiconductor integrated circuit. Since the mask pattern used in the photolithography process of this manufacturing process is created each time by the data supplied by the customer, the information to be written in the memory element in consideration of the power supply voltage required by the customer at the time of manufacturing the mask pattern. Should be decided. Therefore, the number of types of mask patterns does not increase and the number of types of intermediate products does not increase, and there is an effect that production management becomes easy.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a voltage waveform diagram for explaining the operation of the circuit shown in FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4A is a sectional view of a memory element using an N-type enhancement MOS transistor. The diagram (b) is a cross-sectional view of a memory element using an N-type depletion MOS transistor. Diagram (c) is a diagram showing the voltage-current characteristics of the memory element shown in diagrams (a) and (b).

FIG. 5A is a circuit diagram of an example of a conventional output buffer circuit. The partial diagram (b) is an equivalent circuit diagram of the parasitic inductance in the power supply path of the semiconductor integrated circuit.

FIG. 6 is a voltage waveform diagram for explaining the operation of the conventional output buffer circuit shown in FIG. 5 (a).

[Explanation of symbols]

 1 High-level power supply line 2 Data output terminal 3 Ground line 4, 5 Drive circuit 6 Input terminal 7 Semiconductor chip 8 Semiconductor integrated circuit 9CC, 9SS Lead terminal 10CC, 10SS Metal wire 11CC, 11SS Bonding pad 12, 13, 15, 16 Inverter circuit 14 Control Circuit 17 NAND Circuit 18 OR Circuit 41 P-type Substrate 42, 43 Source / Drain Diffusion Layer 44 Gate Insulation Layer 45 Gate Electrode 46 Channel Portion

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical display location H01L 27/092 27/10 481 8728-4M H03K 17/687 19/0175 6741-5L G11C 17/00 306 Z 9054-4M H01L 27/08 321 L 8221-5J H03K 17/687 F 8941-5J 19/00 101 F

Claims (5)

[Claims] 1. An output buffer circuit of a semiconductor integrated circuit including a read-only memory element for writing information during a manufacturing process, wherein a first MOS field effect is provided between a first power supply line and a second power supply line. A circuit in which a transistor and a second MOS field effect transistor are connected in series via a data output terminal; and a first drive circuit which drives a gate of the first MOS field effect transistor by receiving at least a data signal from the outside as an input. An output buffer circuit having at least the data signal as an input and a second drive circuit for driving the gate of the second MOS field effect transistor, wherein a control storage element in which information is written in an information writing step of the read-only storage element And the information stored in the control storage element, the first MOS field effect transistor Output buffer circuit and having data and a data output terminal driving characteristics of the first 2MOS field effect transistor, a control circuit for changing over the first driving circuit and the second driving circuit. 2. The control circuit changes an output drive characteristic of the first drive circuit and an output drive characteristic of the second drive circuit, and the change causes an output drive characteristic of the first MOS field effect transistor and the second MOS field effect transistor to change. 2. The output buffer circuit according to claim 1, wherein the transition speed of the gate voltage is changed to change the drive characteristic of the data output terminal. 3. The control circuit changes the drive characteristic of the data output terminal by changing the effective channel width of the first MOS field effect transistor and the second MOS field effect transistor. 1. The output buffer circuit described in 1. 4. The output buffer circuit according to claim 2, wherein the control circuit is connected to a high-potential power line through a P-channel MOS field effect transistor in which a source and a gate are connected to a ground line and a drain operates as a load. A connected control memory element, a first inverter circuit having an input terminal connected to the drain of the control memory element and outputting a first control signal to an output terminal, and an input terminal of the first inverter circuit. A second inverter circuit connected to the output end and outputting a second control signal to the output end, wherein the first drive circuit is connected in series between the high-potential power line and the ground line. P-channel type third MOS field effect transistor, N-channel type fourth MOS field-effect transistor, N-channel type fifth MOS field-effect transistor, and the fourth M A first resistance element connected in parallel to the S field effect transistor, wherein the drain of the third MOS field effect transistor serves as an output terminal, and the second drive circuit is provided between the high-potential power line and the ground line. P-channel type sixth MOS field-effect transistor, P-channel type seventh MOS field-effect transistor and N-channel type eighth MOS field-effect transistor connected in series, and a second resistor connected in parallel to the seventh MOS field-effect transistor A drain of the eighth MOS field effect transistor as an output terminal, the data signal is input to the gates of the third, fifth, sixth and eighth MOS field effect transistors, and the fourth MO field effect transistor is provided.
The second control signal is input to the gate of the S field effect transistor, the first control signal is input to the gate of the seventh MOS field effect transistor, and the output signal of the first drive circuit is the P-channel type first MOS. An output buffer circuit, wherein an output signal of the second drive circuit is input to a gate of a field effect transistor, and an output signal of the second drive circuit is input to a gate of the N-channel type second MOS field effect transistor. 5. The output buffer circuit according to claim 3, wherein the first MOS field effect transistor is formed by connecting a P-channel type third MOS field effect transistor and a P-channel type fourth MOS field effect transistor in parallel. The second MOS field effect transistor comprises an N-channel type fifth MOS field effect transistor and an N-channel type sixth MOS field effect transistor connected in parallel, and the control circuit has a source and a gate connected to a ground line. A control memory element whose drain is connected to a high-potential power line through a P-channel MOS field effect transistor operating as a load, and an input terminal connected to the drain of the control memory element and a first control terminal at an output terminal. First to output a signal
And an input terminal connected to an output terminal of the first inverter circuit, and a second inverter circuit outputting a second control signal to an output terminal. A third inverter circuit to which the data signal is input and whose output end is connected to the gate of the third MOS field effect transistor; and the data signal and the second control signal which are input, and the output end of which is the fourth
A two-input NAND circuit connected to the gate of the MOS field effect transistor, wherein the second drive circuit is configured such that the input terminal receives the data signal and the output terminal is connected to the gate of the fifth MOS field effect transistor. 4 inverter circuit, the data signal and the first control signal as an input, the output end is the sixth
An output buffer circuit including a 2-input NOR circuit connected to the gate of a MOS field effect transistor.